CN105161535B - 多沟道全包围栅极鳍式半导体器件制备方法 - Google Patents
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Abstract
一种多沟道全包围栅极鳍式半导体器件制备方法,包括:提供衬底,在衬底上形成有非掺杂的翅片结构硅基体,该翅片结构硅基体包含源极结构、漏极结构以及位于所述源极结构和漏极结构之间的鳍形沟道结构;在翅片结构硅基体上的覆盖掩膜层;布置氧化物层以覆盖鳍形沟道结构两侧的衬底表面;第一次部分地蚀刻氧化物层至露出鳍形沟道结构的上段部分;部分地蚀刻上段部分以在上段部分外两侧分别形成第一内凹和第二内凹;在所述第一内凹和所述第二内凹中分别进行掺杂外延以形成第一外延部分和第二外延部分;第二次部分地蚀刻氧化物层;去除掩膜层;蚀刻暴露出来的鳍形沟道结构,使得第一外延部分和所述第二外延部分形成为悬空于衬底上方的双沟道结构。
Description
技术领域
本发明涉及半导体制造领域,更具体地说,本发明涉及一种多沟道全包围栅极鳍式半导体器件制备方法。
背景技术
随着集成电路的发展,器件尺寸越来越小,集成度越来越高。随着半导体器件特征尺寸由于器件尺寸越来越小而不断减小,传统的平面半导体制造技术已经无法使用,非平面技术的半导体器件应运而生,例如绝缘体上硅,双栅,多栅等新工艺的应用。
目前鳍式场效应管在小尺寸领域被广发使用,而具有全包围栅极(gate-all-around)结构的半导体器件由于在器件性能及能有效抑制短沟道效应(short channeleffect)的特殊性能,正是半导体业界所追求的。由于器件沟道被栅极包围,所以器件漏场的影响也被消除,有效抑制了器件的漏电及穿通问题。由于全包围栅极悬空于底部衬底,因此全包围栅极器件的制造工艺较为复杂。
发明内容
本发明所要解决的技术问题是针对现有技术中存在上述缺陷,提供一种多沟道全包围栅极鳍式半导体器件制备方法,能够形成全包围的金属栅极结构,在鳍式场效应管结构中有效地抑制了短沟道效应、漏场和穿通等问题,提高了器件性能。
为了实现上述技术目的,根据本发明,提供了一种多沟道全包围栅极鳍式半导体器件制备方法,包括:
第一步骤,提供衬底,在所述衬底上形成有非掺杂的翅片结构硅基体,该翅片结构硅基体包含源极结构、漏极结构以及位于所述源极结构和漏极结构之间的鳍形沟道结构;
第二步骤,在所述翅片结构硅基体上的覆盖掩膜层;
第三步骤,布置氧化物层,以覆盖鳍形沟道结构两侧的衬底表面并露出鳍形沟道结构上的覆盖掩膜层;
第四步骤,第一次部分地蚀刻氧化物层至露出鳍形沟道结构的上段部分;
第五步骤,部分地蚀刻所述上段部分以在所述上段部分外两侧分别形成第一内凹和第二内凹;
第六步骤,在所述第一内凹和所述第二内凹中分别进行掺杂外延以形成第一外延部分和第二外延部分;
第七步骤,其中第二次部分地蚀刻氧化物层;
第八步骤,其中去除掩膜层;
第九步骤,其中蚀刻暴露出来的鳍形沟道结构,使得所述第一外延部分和所述第二外延部分形成为悬空于衬底上方的双沟道结构。
优选地,所述多沟道全包围栅极鳍式半导体器件制备方法还包括第十步骤,在第一外延部分和第二外延部分外周分别依次沉积一高介电常数材料层和一金属材料层。
优选地,所述多沟道全包围栅极鳍式半导体器件制备方法还包括第十步骤,在第一外延部分和第二外延部分外周分别依次沉积氧化层和多晶硅。
优选地,所述翅片结构硅基体由单晶硅构成、锗硅或碳硅构成。
优选地,在第十步骤通过原子层沉积高介电常数材料层。
优选地,在第十步骤通过溅射沉积金属材料层。
优选地,第一次部分地蚀刻氧化物层和第二次部分地蚀刻氧化物层采用干法蚀刻、湿法蚀刻或者SiCoNi蚀刻。
优选地,掺杂外延的方式是锗掺杂外延或碳掺杂。
优选地,在第九步骤中,湿法蚀刻暴露出来的鳍形沟道结构。
附图说明
结合附图,并通过参考下面的详细描述,将会更容易地对本发明有更完整的理解并且更容易地理解其伴随的优点和特征,其中:
图1和图2示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第一步骤。
图3示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第二步骤。
图4示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第三步骤。
图5示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第四步骤。
图6示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第五步骤。
图7示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第六步骤。
图8示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第七步骤。
图9示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第八步骤。
图10示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第九步骤。
图11和图12示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的第十步骤。
需要说明的是,附图用于说明本发明,而非限制本发明。注意,表示结构的附图可能并非按比例绘制。并且,附图中,相同或者类似的元件标有相同或者类似的标号。
具体实施方式
为了使本发明的内容更加清楚和易懂,下面结合具体实施例和附图对本发明的内容进行详细描述。
图1至图12示意性地示出了根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法的各个步骤。
如图1至图12所示,根据本发明优选实施例的多沟道全包围栅极鳍式半导体器件制备方法包括:
如图1的立体图和图2沿图1所示的虚线平面截取的截面图所示,第一步骤,其中提供衬底100,在所述衬底100上形成有非掺杂的翅片结构硅基体,该翅片结构硅基体包含源极结构10、漏极结构20以及位于所述源极结构和漏极结构之间的鳍形沟道结构30;
如图3所示,第二步骤,其中在所述翅片结构硅基体上的覆盖掩膜层40;
如图4所示,第三步骤,其中布置氧化物层50,以覆盖鳍形沟道结构30两侧的衬底100表面并露出鳍形沟道结构30上的覆盖掩膜层40;
如图5所示,第四步骤,其中第一次部分地蚀刻氧化物层50至露出鳍形沟道结构30的上段部分31;
如图6所示,第五步骤,其中部分地蚀刻所述上段部分31以在所述上段部分31外两侧分别形成第一内凹32和第二内凹33;
如图7所示,第六步骤,其中在所述第一内凹32和所述第二内凹33中分别进行掺杂外延以形成第一外延部分33和第二外延部分34;
如图8所示,第七步骤,其中第二次部分地蚀刻氧化物层50;
如图9所示,第八步骤,其中去除掩膜层40;
如图9所示,第九步骤,其中蚀刻暴露出来的鳍形沟道结构30,使得所述第一外延部分33和所述第二外延部分34形成为悬空于衬底上方的双沟道结构;
如图11的截面图和图12的立体图所示,第十步骤,其中在沟道外周依次沉积一高介电常数材料层和一金属材料层。
显然,本发明并不限于双沟道结构,而且适合于形成多于两个的并行沟道结构。
而且,本发明并非一定要采用金属栅极,也可以采用氧化工艺或者原位水汽生成工艺(ISSG)等工艺在沟道外侧形成氧化层,沉积多晶硅作为栅极。
优选地,所述翅片结构硅基体由单晶硅构成,但是也可以是锗硅,碳硅等。
在第十步骤,可以通过原子层沉积高介电常数材料层60。
在第十步骤,可以通过溅射沉积金属材料层70。
优选地,第一次部分地蚀刻氧化物层50和第二次部分地蚀刻氧化物层50可以采用干法蚀刻,也可以采用湿法蚀刻,或者采用SiCoNi蚀刻去除。
优选地,掺杂外延的方式可以是锗掺杂外延也可以是碳掺杂。
优选地,在第九步骤中湿法蚀刻暴露出来的鳍形沟道结构30。
本发明可以利用鳍形沟道结构中掺杂层和非掺杂层的湿法蚀刻速度的差异,蚀刻去除栅极底部结构形成悬空于衬底上方的沟道。由此,本发明提供一种多沟道全包围栅极鳍式半导体器件制备方法,能够形成全包围的金属栅极结构,在鳍式场效应管结构中有效地抑制了短沟道效应、漏场和穿通等问题,提高了器件性能。
此外,需要说明的是,除非特别说明或者指出,否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等,而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。
可以理解的是,虽然本发明已以较佳实施例披露如上,然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言,在不脱离本发明技术方案范围情况下,都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (9)
1.一种多沟道全包围栅极鳍式半导体器件制备方法,其特征在于包括:
第一步骤,提供衬底,在所述衬底上形成有非掺杂的翅片结构硅基体,该翅片结构硅基体包含源极结构、漏极结构以及位于所述源极结构和漏极结构之间的鳍形沟道结构;
第二步骤,在所述翅片结构硅基体上覆盖掩膜层;
第三步骤,布置氧化物层,以覆盖鳍形沟道结构两侧的衬底表面并露出鳍形沟道结构上的覆盖掩膜层;
第四步骤,第一次部分地蚀刻氧化物层至露出鳍形沟道结构的上段部分;
第五步骤,部分地蚀刻所述上段部分以在所述上段部分外两侧分别形成第一内凹和第二内凹;
第六步骤,在所述第一内凹和所述第二内凹中分别进行掺杂外延以形成第一外延部分和第二外延部分;
第七步骤,其中第二次部分地蚀刻氧化物层;
第八步骤,其中去除掩膜层;
第九步骤,其中蚀刻暴露出来的鳍形沟道结构,使得所述第一外延部分和所述第二外延部分形成为悬空于衬底上方的双沟道结构。
2.根据权利要求1所述的多沟道全包围栅极鳍式半导体器件制备方法,其特征在于还包括第十步骤,在第一外延部分和第二外延部分外周分别依次沉积一高介电常数材料层和一金属材料层。
3.根据权利要求1所述的多沟道全包围栅极鳍式半导体器件制备方法,其特征在于还包括第十步骤,在第一外延部分和第二外延部分外周分别依次沉积氧化层和多晶硅。
4.根据权利要求1或2所述的多沟道全包围栅极鳍式半导体器件制备方法,其特征在于,所述翅片结构硅基体由单晶硅构成、锗硅或碳硅构成。
5.根据权利要求2所述的多沟道全包围栅极鳍式半导体器件制备方法,其特征在于,在第十步骤通过原子层沉积高介电常数材料层。
6.根据权利要求2所述的多沟道全包围栅极鳍式半导体器件制备方法,其特征在于,在第十步骤通过溅射沉积金属材料层。
7.根据权利要求1或2所述的多沟道全包围栅极鳍式半导体器件制备方法,其特征在于,第一次部分地蚀刻氧化物层和第二次部分地蚀刻氧化物层采用干法蚀刻、湿法蚀刻或者SiCoNi蚀刻。
8.根据权利要求1或2所述的多沟道全包围栅极鳍式半导体器件制备方法,其特征在于,掺杂外延的方式是锗掺杂外延或碳掺杂外延。
9.根据权利要求1或2所述的多沟道全包围栅极鳍式半导体器件制备方法,其特征在于,在第九步骤中,湿法蚀刻暴露出来的鳍形沟道结构。
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