CN105122433A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN105122433A CN105122433A CN201480020186.5A CN201480020186A CN105122433A CN 105122433 A CN105122433 A CN 105122433A CN 201480020186 A CN201480020186 A CN 201480020186A CN 105122433 A CN105122433 A CN 105122433A
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- semiconductor substrate
- semiconductor
- seal
- manufacture method
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 227
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 158
- 241000283216 Phocidae Species 0.000 claims description 162
- 238000000034 method Methods 0.000 claims description 82
- 239000000565 sealant Substances 0.000 claims description 38
- 229920005989 resin Polymers 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 14
- 238000007711 solidification Methods 0.000 claims description 5
- 230000008023 solidification Effects 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 abstract description 14
- 239000000463 material Substances 0.000 description 35
- 238000005520 cutting process Methods 0.000 description 33
- 238000003825 pressing Methods 0.000 description 7
- 238000001179 sorption measurement Methods 0.000 description 7
- 238000002788 crimping Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- 238000010521 absorption reaction Methods 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 4
- 238000009740 moulding (composite fabrication) Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000006837 decompression Effects 0.000 description 2
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- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 206010007247 Carbuncle Diseases 0.000 description 1
- 239000004641 Diallyl-phthalate Substances 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
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- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229920001807 Urea-formaldehyde Polymers 0.000 description 1
- QUDWYFHPNIMBFC-UHFFFAOYSA-N bis(prop-2-enyl) benzene-1,2-dicarboxylate Chemical compound C=CCOC(=O)C1=CC=CC=C1C(=O)OCC=C QUDWYFHPNIMBFC-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
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- 229910052731 fluorine Inorganic materials 0.000 description 1
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- 239000002223 garnet Substances 0.000 description 1
- 238000010191 image analysis Methods 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
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- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 229920005749 polyurethane resin Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
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- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Across the entire surface of a distribution area for a plurality of semiconductor elements, which are formed on a semiconductor substrate, a plurality of sealing sheet pieces of areas smaller than the distribution area and which are cut in accordance with scribe lines surrounding the plurality of the semiconductor elements, are attached. A semiconductor substrate (W), in which the sealing layer is cured so as to seal the semiconductor elements therein, is held in a ring frame via dicing tape and subsequently transported to a dicing step, cut along the scribe lines, and the dicing tape is expanded so as to manufacture a semiconductor device.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, in the manufacture method of this semiconductor device, paste the seal stock being formed with the sealant formed by resin combination and carry out sealing semiconductor element.
Background technology
After the surrounding enclosing 1 semiconductor chip by framework, the 1st sealing resin sheet material that is made up of the prepreg being impregnated with resin and the 2nd sealing resin sheet material is utilized to carry out sealing semiconductor chips from two of this semiconductor chip faces clampings respectively and have manufactured semiconductor device (with reference to patent documentation 1).
Patent documentation 1: Japanese Unexamined Patent Publication 5-291319 publication
Summary of the invention
the problem that invention will solve
But, in above-mentioned method in the past, produce following problem.
That is, in recent years, the requirement produced high-density installation according to the develop rapidly along with application, semiconductor device tends to miniaturization.Thus, to be divided by semiconductor crystal wafer after being broken into semiconductor element utilizing cutting process, with resin sealing semiconductor element one by one, therefore, production capacity declines, and then creates that production efficiency is reduced is so bad.
Namely the present invention completes in view of such situation, and its main purpose is to provide a kind of manufacture method that can manufacture the semiconductor device of semiconductor device while the speed of production promoting semiconductor device accurately.
for the scheme of dealing with problems
Therefore, the present inventor etc. are bad in order to solve this, repeatedly carry out testing, simulating and further investigate, result, drawn following opinion.
Attempted whole of semiconductor substrate paste individual the seal stock that has been formed with the sealant formed by resin combination and make its solidify after its point is broken into this semiconductor device.But, create following new problem in the method.First, in the cooling procedure after the process that is heating and curing of the sealant of seal stock, semiconductor substrate is made to there occurs warpage due to the contraction of sealant.This warpage can cause at absorption semiconductor substrate and carry out conveying mistake occurs in the process of carrying.In addition, when the amount of warpage of semiconductor substrate is larger, if pressing semiconductor substrate corrects this warpage, then semiconductor substrate can be damaged.Further, when pasting large-area seal stock, in taping process, bubble is easy to be rolled into the bonding interface of itself and semiconductor substrate, produces space, make semiconductor device become defective item in sealant.
The present invention, in order to reach this object, takes following structure.
That is, a manufacture method for semiconductor device, it manufactures semiconductor device for being pasted onto on semiconductor element by the seal stock being formed with the sealant formed by resin combination on release liner, and the feature of the manufacture method of this semiconductor device is,
This manufacture method comprises following process:
Taping process, will be pasted onto on whole of the distributed areas of this semiconductor element with the area less than the area of these distributed areas and according to point multiple diaphragm seals that broken string cuts off of the multiple semiconductor element of encirclement in the distributed areas of multiple described semiconductor element being formed at semiconductor substrate;
Solidification process, makes described sealant solidify; And
Breaking course, will utilize the described sealant that have cured by the semiconductor substrate disjunction after semiconductor element encapsulation.
(action effect) adopts said method, owing to being divided into multiple diaphragm seals the distributed areas being pasted onto this semiconductor element of being cut into the area less than the area of the whole distributed areas being formed with semiconductor element, therefore, diaphragm seal each self-constriction on a semiconductor substrate.When being pasted on a semiconductor substrate by 1 seal stock of shape roughly the same with semiconductor substrate, sealing sheet material shrinks towards a direction at the center of semiconductor substrate.But, when having pasted multiple diaphragm seals as the method, because the shrinkage direction of diaphragm seal disperses, therefore, it is possible to suppress the warpage of semiconductor substrate.In addition, at this, distributed areas refer to and are configured with predetermined multiple semiconductor element of semiconductor substrate singualtion and comprise the region of the cut-out preset lines of its outermost perimembranous.In addition, in the present invention, diaphragm seal refers to the form of adding the state having release liner on sealant.
In addition, because multiple diaphragm seals have the profile conformed to that point break with semiconductor substrate, therefore, it is possible to less than sealing semiconductor element in bias.In addition, because adjacent diaphragm seal is equivalent to a point broken string, each other therefore, it is possible to easily cut off semiconductor device along this position from semiconductor substrate.
In addition, the size due to multiple diaphragm seals is less than the size of semiconductor substrate, and therefore, process during stickup is easy.That is, bubble can be suppressed to be rolled into the bonding interface of semiconductor substrate and seal stock.Thus, can suppress to produce space in sealant.
In addition, in the method, taping process can be implemented as follows.
Such as, as a technical scheme, multiple diaphragm seals hemisection being slit into individual seal stock of the size of more than the shape with semiconductor substrate are pasted on a semiconductor substrate,
The part be positioned at around diaphragm seal that cuts out of described release liner and seal stock is peeled off from semiconductor substrate.
Adopt the method, utilize 1 sticking placement just multiple diaphragm seals can be pasted on a semiconductor substrate.In addition, namely individual seal stock can be the shape identical with semiconductor substrate, also can be the size larger than the size of semiconductor substrate.
When individual seal stock is the size larger than the size of semiconductor substrate, preferably, while giving tension force to individual seal stock, multiple diaphragm seals are pasted on a semiconductor substrate, before breaking course, release liner self sealss sheet material is peeled off.
Adopt the method, owing to giving tension force to seal stock, therefore, sealing sheet material can not produce lax.Thus, can while suppression bubble is rolled into the bonding interface of seal stock and semiconductor substrate accurately by sealing sheet attaching on a semiconductor substrate.
As another technical scheme, multiple diaphragm seals of temporary bond on individual release liner of size with more than the shape of semiconductor substrate,
Described release liner across individual on described semiconductor substrate pastes multiple diaphragm seals,
Before described breaking course, individual described release liner self sealss sheet is peeled off.
In the method, 1 sticking placement is also utilized just multiple diaphragm seals can be pasted on a semiconductor substrate in the same manner as technique scheme.In addition, namely individual release liner can be the shape identical with semiconductor substrate, also can be the size larger than the size of semiconductor substrate.
When individual release liner is the size larger than the size of semiconductor substrate, preferably, while giving tension force to this release liner, multiple diaphragm seals are pasted on a semiconductor substrate, before breaking course, release liner self sealss sheet material is peeled off.
Adopt the method, owing to giving tension force to release liner, therefore, diaphragm seal can not produce lax.Thus, while the bonding interface of the bonding interface and diaphragm seal and semiconductor substrate that suppress bubble to be rolled into diaphragm seal and semiconductor substrate produces fold, sealing sheet can be pasted on a semiconductor substrate.
In addition, in this technical scheme, also can paste the seal stock of different qualities according to the region of semiconductor substrate.
That is, by pasting the little diaphragm seal of other the shrinkage of diaphragm seal of shrinkage ratio at the position being easy to occur warpage of semiconductor substrate, the warpage of semiconductor substrate can be suppressed.
In addition, the diaphragm seal of different size and shape also can be pasted according to the distributed areas of semiconductor element.
Adopt the method, even if multiple identical diaphragm seal shrinkages are identical, if the less shape of seal stock and end limit shorter, then the contract by distance of sealant is also less.That is, pasted the diaphragm seal of different size and shape by mixing, the contraction of sealant can be adjusted and suppress the warpage of semiconductor substrate.
In addition, in above-mentioned each technical scheme, preferably, adhesive seal sheet material on a semiconductor substrate in reduced atmosphere.
Be compared with the situation of the seal stock of semiconductor substrate same size with seal stock, adopt the method, shorter for the displacement of discharging the bubble be entangled between seal stock and semiconductor substrate.Thus, can at short notice more reliably self bonding interface removing bubble.
the effect of invention
Adopt the manufacture method of semiconductor device of the present invention, while the speed of production promoting semiconductor device, also can manufacture semiconductor device accurately.
Accompanying drawing explanation
Fig. 1 is the stereogram of the material webs representing seal stock.
Fig. 2 is the longitudinal section of seal stock.
Fig. 3 is the front view of the schematic configuration representing the device be provided in feeding sheet materials operation.
Fig. 4 is the integrally-built front view representing the device be provided in adhering processes.
Fig. 5 is the integrally-built vertical view representing the device be provided in adhering processes.
Fig. 6 is the front view of the schematic configuration representing liner mechanism for stripping.
Fig. 7 is the partial sectional view of the chamber forming sheet attaching mechanism.
Fig. 8 is the front view of the schematic configuration representing heater.
Fig. 9 is the front view of the peeling action representing the 2nd release liner.
Figure 10 is the figure of the action representing temporary bond seal stock on a semiconductor substrate.
Figure 11 is the figure of the action representing temporary bond seal stock on a semiconductor substrate.
Figure 12 is the figure representing action seal stock being formally adhered to semiconductor substrate.
Figure 13 is the figure representing the action formally crimping seal stock on a semiconductor substrate.
Figure 14 is the vertical view representing the semiconductor substrate after eliminating unwanted sealant and the 1st release liner.
Figure 15 is the stereogram representing the semiconductor substrate remained on ring frame.
Figure 16 represents figure semiconductor substrate being divided the action being broken into semiconductor device.
Figure 17 is the vertical view of the seal stock representing variation.
Figure 18 is the stereogram of the structure representing application jig.
Figure 19 is the figure representing the action of laying seal stock in application jig.
Figure 20 is the figure representing the action of laying seal stock in application jig.
Figure 21 is the vertical view representing the state of laying seal stock in application jig.
Figure 22 is the figure representing the action temporarily crimping seal stock on a semiconductor substrate.
Figure 23 is the figure representing the action temporarily crimping seal stock on a semiconductor substrate.
Figure 24 is the figure of the feed status representing the semiconductor substrate being temporarily crimped with seal stock.
Figure 25 is the figure representing the action formally crimping seal stock on a semiconductor substrate.
Figure 26 is the figure of the action representing the unwanted sealant of removing and the 1st release liner.
description of reference numerals
3, sheet cutting mechanism; 20, sheet material mounting table; 21, sheet conveying mechanism; 22, liner mechanism for stripping; 23, the 1st holding station; 24, substrate carrying mechanism; 25, sheet attaching mechanism; 45, the 2nd holding station; 46, chamber; 59, pressing plate; 60, heater; 61, heater; 64, heating plate; T, seal stock; C, semiconductor element; CT, diaphragm seal; M, sealant; S1, S2, release liner; W, semiconductor substrate.
Embodiment
Hereinafter, with reference to the accompanying drawings of one embodiment of the present of invention.Be described for the situation of the semiconductor substrate being formed with multiple semiconductor element on surface being pasted the seal stock being formed with the sealant formed by resin combination.
< seal stock >
As depicted in figs. 1 and 2, seal stock T is such as supplied by the material webs of the rectangular seal stock T that reels.In addition, sealing sheet material T adds the 1st release liner S1 and the 2nd release liner S2 that there are protection in two faces of sealant M.
Sealant M is formed as plate shape by encapsulant.As encapsulant, such as, can list the thermosetting resins such as heat-curable silicone, epoxy resin, thermoset polyimide resin, phenolic resins, urea resin, melamine resin, unsaturated polyester resin, diallyl phthalate resin, thermosetting polyurethane resin.In addition, as encapsulant, the compositions of thermosetting resin containing above-mentioned thermosetting resin and additive in suitable ratio can also be listed.
As additive, such as, filler, fluorophor etc. can be listed.As filler, such as, can list organic fine particles etc. such as the fine inorganic particles such as silicon dioxide, titanium dioxide, talcum, aluminium oxide, aluminium nitride, silicon nitride, such as silicon grain.Fluorophor has wavelength convert function, such as, can list the yellow fluorophor that blue light can be converted to sodium yellow, the red-emitting phosphors etc. that blue light can be become red light.As yellow fluorophor, such as, Y can be listed
3al
5o
12: the carbuncle type fluorophor such as Ce (YAG (yttrium-aluminium-garnet): Ce).As red-emitting phosphors, such as, CaAlSiN can be listed
3: Eu, CaSiN
2: the nitride phosphors etc. such as Eu.
Sealant M was adjusted to semisolid shape before sealing semiconductor element, specifically, when encapsulant contains thermosetting resin, such as, solidifying before (C is staged) completely, namely adjusting under semi-solid preparation (B-stage) state.
The size of sealant M is suitably set according to the size of semiconductor element and substrate.Specifically, seal stock be sealant when being prepared to rectangular sheet material left and right directions on length, namely width be such as more than 100mm, being preferably more than 200mm, such as, be below 1500mm, preferably below 700mm.In addition, suitably set the thickness of sealant accordingly with the size of semiconductor element, such as, be more than 30 μm, be preferably more than 100 μm, and be such as less than 3000 μm, be preferably less than 1000 μm.
1st release liner S1 and the 2nd release liner S2 such as can list polymer sheet, such as ceramic sheet material, the such as metal formings etc. such as polyethylene sheets, polyester sheet (PET etc.), polystyrene sheet material, polycarbonate sheet, polyimides sheet material.Also can in release liner, the contact-making surface that contacts with sealant implements the demoulding process such as fluorine process.Suitably set the size of the 1st release liner and the 2nd release liner according to stripping conditions, thickness is such as more than 15 μm, is preferably more than 25 μm, and is such as less than 125 μm, is preferably less than 75 μm.
Then, to seal stock T being pasted onto the operation that semiconductor substrate manufactures semiconductor device and device is described.In addition, in the present embodiment, be described for the situation of adhesive seal sheet material on the semiconductor substrate of circle.
The manufacturing process of semiconductor device is formed by cutting off operation, adhering processes, solidification treatment process and cutting action.
As shown in Figure 3, in cut-out operation, be made up of feeding sheet materials portion 1, shut-off mechanism 2 and sheet material recoverer 3 etc.
Feeding sheet materials portion 1 utilize feeding roller 5 and guide reel 6 guide from supply winch spool 4 release wear the seal stock T of release liner S1, S2 at two and be directed to shut-off mechanism 2.
Shut-off mechanism 2 is such as made up of Cutting table 7, the 1st shut-off mechanism 8 and the 2nd shut-off mechanism 9 etc.
Cutting table 7 is made up of the chuck table larger than the width of seal stock T.1st shut-off mechanism 8 is made up of drawing cutting unit 12 etc., this drawing cutting unit 12 utilizes the movable table 11 be arranged in movable frame 10 to move horizontally and be elevated in this movable frame 10, and this movable frame 10 moves forward and backward along guide rail R under the state across Cutting table 7.This drawing cutting unit 12 possesses point of a knife cutting knife 13 down.Thus, drawing cutting unit 12 only remains the release liner S2 of rear side, as shown in Figure 1, seal stock T hemisection is slit into the diaphragm seal CT of reservation shape.In addition, in the present embodiment, diaphragm seal refers to the form of adding the state having release liner on sealant.
2nd shut-off mechanism 9 be equipped with supporting arm 16 in the bottom of liftable movable table in the mode can circled round around the supercentral vertical axis line X driving being positioned at Cutting table 7.In addition, the cutting knife unit 17 of free end side being equipped on this supporting arm 16 is provided with point of a knife cutting knife 18 down.And be configured to be circled round around vertical axis line X by this supporting arm 16, seal stock T is cut into the shape roughly the same with semiconductor substrate by cutting knife 18.Thus, individual the seal stock T after cut-out is not completely consistent with the profile of the otch formed on a semiconductor substrate, plane of orientation, but comprises the form of the circle covering otch etc.
The part that sheet material recoverer 3 is configured to the shape cutting into semiconductor substrate of seal stock T to be obtained is batched on recovery winch spool 19.
In addition, the peel plate 14 of tapering taper is equipped with in the downstream of Cutting table 7.That is, be configured to utilize peel plate 14 to be turned back by seal stock T and the conglobate part that cuts of seal stock T is peeled off.Peel plate 14 utilizes the conveying mechanism 15 possessing adsorption plate adsorb and keep seal stock T.Conveying mechanism 15 is configured to synchronously move horizontally with the feeding speed of seal stock T, and the seal stock T peeled off from peel plate 14 is adsorbed and taken out of.
Sheet material mounting table 20, sheet conveying mechanism 21, liner mechanism for stripping 22, the 1st holding station 23, substrate carrying mechanism 24 and sheet attaching mechanism 25 etc. are equipped with as shown in Figure 4 and Figure 5, in adhering processes.
Sheet material mounting table 20 is made up of the chuck table of shape larger than seal stock T.
Sheet conveying mechanism 21 possesses the adsorption plate 26 that can move horizontally and be elevated all around.That is, possess the 1st movable table 28 of movement on guide rail R1, this guide rail R1 extends along the frame 27 crossed out to apparatus main body.Fore-and-aft direction towards apparatus main body is arranged on frame 27 by the guide rail R2 that level keeps.Adsorption plate the 26,2nd movable table 30 possessing the vertical frame lifting that can be bearing in the 2nd movable table 30 along pendency can move forward and backward along guide rail R2.
As shown in Figure 6, liner mechanism for stripping 22 has release band supply unit 31, peels off unit 32, is with recoverer 33 and camera 34.
Release band supply unit 31 supplies the width rectangular release band TS narrower than the width of seal stock T towards stripping unit 32.
Stripping unit 32 possesses the stripper roll 35 for the release band TS that reels.This stripper roll 35 can be elevated, and it rises to the position higher than sheet material mounting table 20.That is, utilizing sheet conveying mechanism 21 adsorb maintenance seal stock T and carry out in the process of carrying, release band TS presses and is pasted onto on the release liner S2 at the seal stock T back side by stripper roll 35.
With recoverer 33 by batching release band TS under the state utilizing stripper roll 35 to be pasted on the release liner S2 of the rear side of seal stock T, the release liner S2 that release band TS and self sealss sheet material T peels off together being batched to be recovered in and reclaims on winch spool.
The position of multiple diaphragm seals CT of the seal stock T hemisect after being peeled off by the 2nd release liner S2 taken by camera 34 from the back side, this view data is sent to control part 100.
As shown in Figure 4 and Figure 5, the 1st holding station 23 is made up of the chuck table of shape larger than semiconductor substrate W.1st holding station 23 is configured to rotate around the longitudinal axis, aims at semiconductor substrate W.In addition, the 1st holding station 23 is configured to move back and forth between the mounting position and the aligned position of device inboard of semiconductor substrate W along guide rail 38.
Above aligned position, be equipped with two cameras 39, two view data are sent to control part 100 by the profile of shooting semiconductor substrate W and point broken string (line).
Substrate carrying mechanism 24 possesses the movable table 42 of putting movement at the enterprising luggage of guide rail R3, and this guide rail R3 arrives sheet attaching mechanism 25 side along the frame 41 crossed out to apparatus main body.Possesses the adsorption plate 44 that can be supported on the vertical frame lifting in this movable table 42 along pendency.Adsorption plate 44 has the size of more than the shape of semiconductor substrate W.That is, substrate carrying mechanism 24 is configured to the 2nd holding station 45 moving back and forth adhering processes described later from the 1st holding station 23.
Adhering processes possesses sheet attaching mechanism 25.This sheet attaching mechanism 25 is made up of the 2nd holding station 45 and chamber 46 etc.
As shown in Figure 7, the 2nd holding station 45 is accommodated in the lower casing 46B in a pair upper casing 46A and lower casing 46B up and down forming chamber 46.
In addition, lower casing 46B is configured to move back and forth between the below accepting position and upper casing 46A of the semiconductor substrate W of the front side of apparatus main body along guide rail 48.
The upper casing 46A forming chamber 46 is equipped with lift drive mechanism 50.This lift drive mechanism 50 comprises movable table 53 that the track 52 that can be configured in the back of longitudinal wall 51 is along the longitudinal elevated, can regulate the mode arm 55 that is bearing in the movable frame 54 in this movable table 53 and stretches out toward the front from this movable frame 54 of height.The bolster 56 stretched out downwards from the top ends of this arm 55 is provided with upper casing 46A.
By utilizing motor 58 to make lead screw shaft 57 forward/reverse, movable table 53 can be made to be elevated in the mode of screwfeed.In addition, in the inside of upper casing 46A built with liftable pressing plate 59.Heater 60 is embedded with in this pressing plate 59.
As shown in Figure 8, solidify treatment process and possess heater 61.Heater 61 is such as made up of the 3rd holding station 62 and the liftable heating plate 64 etc. being embedded with heater 63 for loading maintenance semiconductor substrate W.
Cutting action possesses and divides the semiconductor substrate W across the bonding maintenance of cutting belt the shearing device being broken into semiconductor device.
Then, a series of action manufacturing semiconductor device is described in detail.
In cut-out operation, the rectangular seal stock T utilizing drawing cutting unit 12 that absorption is held in Cutting table 7 is with the little area of the area of the whole distributed areas than the multiple semiconductor elements formed on a semiconductor substrate and become diaphragm seal CT according to a point broken string hemisect of surrounding multiple semiconductor element.As shown in Figure 1, multiple diaphragm seals CT is not superposed to cover the mode layout in advance of the whole distributed areas of semiconductor element.That is, hemisect is carried out according to below the size of the line inside disjunction line width.In addition, at this, as shown in the single dotted broken line of Fig. 5, distributed areas refer to and are configured with predetermined multiple semiconductor element of semiconductor substrate singualtion and comprise the region DA of the cut-out preset lines of its outermost perimembranous.
Then, utilize the 2nd shut-off mechanism 9 that the seal stock T being formed with diaphragm seal CT is cut into the shape of semiconductor substrate W.Remove the absorption of Cutting table 7, individual the seal stock T becoming the shape of semiconductor substrate W is positioned in the sheet material mounting table 20 of adhering processes.In addition, the part cutting circle of rectangular seal stock T is taken up and is recovered on sheet material recoverer 3.
When seal stock T is positioned in sheet material mounting table 20, utilizes sheet conveying mechanism 21 to adsorb and keep, be transported to the top of camera 34.Now, as shown in Figure 6, stripper roll 35 rises slightly from sheet material mounting table 20, rises to the anterior position of the throughput direction departing from this sheet material mounting table 20 in the process of horizontal feed.As shown in Figure 9, the release band TS be wound in this stripper roll 35 is pressed against the 2nd release liner S2 of the rear side of seal stock T.Afterwards, batch release band TS with the speed synchronous with the transporting velocity of sheet conveying mechanism 21, the sheet material of self sealss on one side T peels off the 2nd release liner S2.The 2nd release liner S2 and release band TS under peeling off together is taken up to be recovered in and reclaims on winch spool.
Time above seal stock T arrives camera 34, the profile of seal stock T and the laying out images of seal stock T are taken.This view data is sent to control part 100.When photographing process completes, sheet conveying mechanism 21 adsorb remain seal stock T state under move in the 1st holding station 23.
Be positioned in sheet material mounting table 20 with seal stock T and roughly side by side in the 1st holding station 23, load semiconductor substrate W.The 1st holding station 23 that absorption remains semiconductor substrate W moves to aligned position, utilizes camera 39 to take surface.The view data photographed is sent to control part 100.
When photographing process completes, the 1st holding station 23 turns back to mounting position.At this, semiconductor substrate W is aimed at, the profile of layout of the diaphragm seal CT that the image analysis process utilizing control part 100 is obtained is consistent with the line of point broken string inner side of the semiconductor element of semiconductor substrate W, and whole of the distributed areas of covering semiconductor element.The 1st holding station 23 is made to rotate around longitudinal axis and aim at.
When the aligning of semiconductor substrate W completes, as shown in Figure 10, the seal stock T transported by sheet conveying mechanism 21 and semiconductor substrate W is oppositely disposed.Afterwards, as shown in figure 11, adsorption plate 26 drops to predetermined altitude.Now, seal stock T is crimped on semiconductor substrate W by moderately pressing temporarily.When the interim crimping of seal stock T completes, sheet conveying mechanism 21 turns back to sheet material mounting table 20 side.
The semiconductor substrate W being temporarily crimped with seal stock T utilizes substrate carrying mechanism 24 to adsorb maintenance, is transported to the 2nd holding station 45.
When semiconductor substrate W is placed in the 2nd holding station 45, substrate carrying mechanism 24 rises and turns back to the 1st holding station 23 side.2nd holding station 45 is moved to the below of upper casing 46 adsorbing the state that remain semiconductor substrate W.
As shown in Figure 12 and Figure 13, the lower end of upper casing 46A drops to the position abutted with lower casing 46B.Namely form chamber 46.Afterwards, by decompression in chamber 46.Further, make pressing plate 59 decline and press seal stock T and heat, it is formally crimped on semiconductor substrate W.In this moment, sealant M is not completely crued state.
When formally having crimped, atmospheric pressure will be returned in chamber 46 and upper casing 46A has been opened.Lower casing 46B and the 2nd holding station 45 together turn back to the delivery position of substrate.The semiconductor substrate W being formally crimped with seal stock T shown in Figure 14 is transported to solidification handling part after unwanted sealant M and release liner being peeled off.
Make heating plate 64 abut with the semiconductor substrate W be positioned in the 3rd holding station 62 and be heated, sealant M is heating and curing.That is, after rising to predetermined temperature, be cooled to vitrification point and sealant M is solidified completely.
Afterwards, as shown in figure 15, cutting belt DT is held in by ring frame f by bonding for semiconductor substrate W.Be transported to cutting action in this condition, utilize cutting knife along a point broken string disjunction semiconductor substrate.When disjunction process completes, as shown in figure 16, only make substrate holder 85 rise slightly and make it expand from rear side jack-up cutting belt, each semiconductor device CP is separated completely.Above, a series of process completes, and repeats identical process.
As described above, be pasted onto whole of the distributed areas of this semiconductor element owing to being divided into multiple diaphragm seals CT of cutting into the area less than the area of the whole distributed areas being formed with semiconductor element, therefore, it is possible to suppress the warpage of semiconductor substrate W.That is, when being pasted onto on semiconductor substrate W by 1 seal stock T with semiconductor substrate same shape, seal stock T shrinks towards a direction at the center of semiconductor substrate W.But when multiple diaphragm seals CT being divided into semiconductor substrate W and paste, shrinkage direction disperses, and can suppress the warpage of semiconductor substrate W.
In addition, the size due to diaphragm seal CT is less than the size of semiconductor substrate W, and therefore, process during stickup is easy.That is, bubble can be suppressed to be rolled into the bonding interface of semiconductor substrate W and diaphragm seal CT.Thus, can suppress to produce space in sealant.
In addition, the present invention also can implement according to following such mode.
(1) in the above-described embodiments, individual seal stock T is not limited to the shape of semiconductor substrate W.Such as, as shown in figure 17, individual the seal stock T cutting into the rectangle of shape larger than semiconductor substrate W also can utilize hemisect diaphragm seal CT and the material formed.
In this case, preferably, in sheet attaching operation, be pasted onto under the state that tension force is imparted to seal stock T on semiconductor substrate W.
Such as, the application jig 70 shown in Figure 18 installs seal stock T to process.The clamping plate 72 of application jig 70 exerts a force to the direction utilizing helical spring 73 to press support plate 74 at the two ends of the framework 71 of rectangle.In addition, the top of the ball axle 76 of the through fixed block 75 be fixed on framework 71 is connected to the adjacent bottom portions of the side of the support plate 74 of the master L-shape of falling word.The helical spring 77 between this ball axle 76 and fixed block 75 is utilized to apply spring force towards foreign side to support plate 74.In addition, nut 78 has been threadedly engaged in another side of this ball axle 76.By making this nut 78 forward/reverse, the outstanding distance of ball axle 76 changes, and is configured to the force outwardly that can adjust clamping plate 72 and support plate 74.
Then, the action utilizing this application jig 70 seal stock T to be formally crimped on a circulation of semiconductor substrate W is described.
As shown in figure 19, overcome spring force and open clamping plate 72, seal stock T is positioned on framework 71.Afterwards, as shown in Figure 20 and Figure 21, the two ends of clamping plate 72 pinch seal sheet material are utilized.
Semiconductor substrate W in the 1st holding station 23 making registration process complete is relative with application jig 70, as shown in figure 22, makes application jig 70 drop to predetermined altitude.Now, as shown in figure 23, erect the location hole 79 that the alignment pin P being arranged on the 2nd holding station 45 is sticked in application jig 70, carry out contraposition.In this condition, predetermined load is applied to seal stock T and it is crimped on semiconductor substrate W temporarily.
As shown in figure 24, utilize the substrate carrying mechanism 24 changing to sucker 80 from adsorption plate 44 to adsorb application jig 70, carried and be positioned in the 2nd holding station 45.Now, in the same manner as in time application jig 70 being placed in the 1st holding station 23, the alignment pin P be formed in the 2nd holding station 45 is sticked in the location hole 79 be formed on the framework 71 of application jig 70, carries out contraposition.
Make the lower casing 46B being accommodated with the 2nd holding station 45 move to the below of upper casing 46A, as shown in figure 25, form chamber 46.By decompression in chamber 46, and utilize pressing plate 59, while heating, seal stock T is formally crimped on semiconductor substrate W.
When formally having crimped, the 2nd holding station 45 has been made to move to the delivery position of substrate, the cooling scheduled time.Afterwards, as shown in figure 26, adsorb application jig 70 by utilizing substrate carrying mechanism 24 and make it increase, thus the low unwanted sealant M of bonding force remains in the 1st release liner S1 side and peels off from semiconductor substrate W.
Sealant M is formally crimped into the semiconductor substrate W of the shape of diaphragm seal CT in the same manner as above-described embodiment, through overcuring treatment process and cutting action broken become semiconductor device.
Adopting the method, by utilizing application jig 70 to clamp the position of exposing from the profile of semiconductor substrate W, under the state that moderate tension is imparted to seal stock T, seal stock T can be pasted onto on semiconductor substrate W.That is, because seal stock T does not relax when pasting, therefore, it is possible to suppress bubble be rolled into the bonding interface of seal stock T and semiconductor substrate W or produce fold.
(2) in the above-described embodiments, also can peel off the 2nd release liner S2 of rear side from the diaphragm seal CT cutting into reservation shape from rectangular seal stock T, be pasted onto the precalculated position of semiconductor substrate W in order.Or, also can utilize the seal stock having the diaphragm seal CT cutting into reservation shape in advance on the release liner of the shape or shape larger than semiconductor substrate that cut into semiconductor substrate with the layout temporary bond determined.
When having a diaphragm seal CT with temporary bond on the release liner of semiconductor substrate W same shape, peeling off the 2nd release liner S2 from the back side and after having carried out contraposition with semiconductor substrate W, semiconductor substrate W crimping temporarily.Treatment process afterwards carries out the process identical with above-mentioned main embodiment.
In addition, on the release liner of shape larger than semiconductor substrate W, temporary bond has a diaphragm seal CT, the two ends of release liner are clamped in application jig 70 and release liner are given to the tension force of appropriateness.The 2nd release liner S2 is peeled off at the back side of self sealss sheet CT in this condition, carries out contraposition and it crimped temporarily with semiconductor substrate W.Carry out the process identical with above-mentioned variation afterwards.
Adopt these execution modes, diaphragm seal CT different for characteristic can be pasted onto on semiconductor substrate W.Such as utilize the diaphragm seal CT that the shrinkage of sealant M is different, semiconductor substrate W be easy to occur warpage region and be difficult to occur warpage region in use respectively.Such as, the diaphragm seal CT that shrinkage ratio is pasted onto the little sealant M of the shrinkage of the sealant M of the diaphragm seal CT of other parts has been formed with being easy to occur the bonding partially of warpage.Adopt the method, the amount of warpage of semiconductor substrate W can be adjusted.
(3) in the various embodiments described above, utilize the 1st shut-off mechanism 8 and the 2nd shut-off mechanism 9 to cut off diaphragm seal CT and individual seal stock T respectively, but also can be configured to utilize the Thomson cutter of the layout imitating semiconductor substrate W and diaphragm seal CT to carry out stamping-out or hemisect in advance.
(4) in the various embodiments described above, till also can proceeding to the solidification process of sealant in sheet attaching operation.
(5) in the various embodiments described above, the shape of semiconductor substrate W is not limited to circle.Thus, semiconductor substrate W also can be the quadrangles such as square or rectangular.
(6) in the above-described embodiments, both can be the size larger than the size of this semiconductor substrate with the seal stock T of individual semiconductor substrate same shape, also can be in outside distributed areas to the size less than this semiconductor substrate in the scope of the periphery of semiconductor substrate.
utilizability in industry
As above, the present invention also manufactures semiconductor device while being adapted at the speed of production of lifting semiconductor device accurately.
Claims (12)
1. a manufacture method for semiconductor device, it manufactures semiconductor device for being pasted onto on semiconductor element by the seal stock being formed with the sealant formed by resin combination on release liner, and the feature of the manufacture method of this semiconductor device is,
This manufacture method comprises following process:
Taping process, will be pasted onto on whole of the distributed areas of this semiconductor element with the area less than the area of these distributed areas and according to point multiple diaphragm seals that broken string cuts off of the multiple semiconductor element of encirclement in the distributed areas of multiple described semiconductor element being formed at semiconductor substrate;
Solidification process, makes described sealant solidify; And
Breaking course, will utilize the described sealant that have cured by the semiconductor substrate disjunction after semiconductor element encapsulation.
2. the manufacture method of semiconductor device according to claim 1, is characterized in that,
In described taping process, multiple diaphragm seals hemisection being slit into individual seal stock of the size of more than the shape with semiconductor substrate are pasted on a semiconductor substrate,
The part be positioned at around diaphragm seal that cut out of described release liner and seal stock is peeled off from semiconductor substrate.
3. the manufacture method of semiconductor device according to claim 2, is characterized in that,
Individual the shape of seal stock described is identical with the shape of semiconductor substrate.
4. the manufacture method of semiconductor device according to claim 2, is characterized in that,
Individual the size of seal stock described is larger than the size of semiconductor substrate.
5. the manufacture method of semiconductor device according to claim 4, is characterized in that,
In described taping process, while giving tension force to individual seal stock, multiple seal stocks are pasted on a semiconductor substrate.
6. the manufacture method of semiconductor device according to claim 1, is characterized in that,
In described taping process, multiple diaphragm seals of temporary bond on individual the release liner of size with more than the shape of semiconductor substrate,
Described release liner across individual on described semiconductor substrate pastes multiple diaphragm seals,
Before described breaking course, individual described release liner self sealss sheet is peeled off.
7. the manufacture method of semiconductor device according to claim 6, is characterized in that,
Individual the shape of release liner described is identical with the shape of semiconductor substrate.
8. the manufacture method of semiconductor device according to claim 6, is characterized in that,
Individual the size of release liner described is larger than the size of semiconductor substrate.
9. the manufacture method of semiconductor device according to claim 8, is characterized in that,
In described taping process, while giving tension force to individual release liner, multiple diaphragm seals are pasted on a semiconductor substrate.
10. the manufacture method of semiconductor device according to claim 6, is characterized in that,
In described taping process, paste the diaphragm seal of different qualities according to the region of semiconductor substrate.
The manufacture method of 11. semiconductor devices according to claim 1, is characterized in that,
In described taping process, paste the diaphragm seal of different size and shape according to the distributed areas of semiconductor element.
The manufacture method of 12. semiconductor devices according to claim 1, is characterized in that,
In described taping process, adhesive seal sheet on a semiconductor substrate in reduced atmosphere.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013080601A JP2014204033A (en) | 2013-04-08 | 2013-04-08 | Semiconductor device manufacturing method |
| JP2013-080601 | 2013-04-08 | ||
| PCT/JP2014/057175 WO2014167947A1 (en) | 2013-04-08 | 2014-03-17 | Manufacturing method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105122433A true CN105122433A (en) | 2015-12-02 |
Family
ID=51689361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480020186.5A Pending CN105122433A (en) | 2013-04-08 | 2014-03-17 | Manufacturing method for semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JP2014204033A (en) |
| KR (1) | KR20150140340A (en) |
| CN (1) | CN105122433A (en) |
| SG (1) | SG11201508204RA (en) |
| TW (1) | TW201448062A (en) |
| WO (1) | WO2014167947A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112020768A (en) * | 2018-04-24 | 2020-12-01 | 迪思科高科技(欧洲)有限公司 | Apparatus and method for attaching protective tape to semiconductor wafer |
| CN112020769A (en) * | 2018-04-24 | 2020-12-01 | 迪思科高科技(欧洲)有限公司 | Alignment apparatus and alignment method |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102400826B1 (en) * | 2017-09-13 | 2022-05-23 | 제뉴인 솔루션스 피티이. 엘티디. | Cutting method and system for polymer resin mold compound-based substrate |
| CN108601241B (en) | 2018-06-14 | 2021-12-24 | 环旭电子股份有限公司 | SiP module and manufacturing method thereof |
| WO2022163763A1 (en) * | 2021-02-01 | 2022-08-04 | ナガセケムテックス株式会社 | Method for sealing electronic component mounting substrate, and heat-curable sheet |
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| JPH11251347A (en) * | 1998-03-03 | 1999-09-17 | Hitachi Cable Ltd | Manufacture of semiconductor package |
| CN1655353A (en) * | 2004-02-13 | 2005-08-17 | 株式会社东芝 | Stack MCP and manufacturing method thereof |
| US20060128065A1 (en) * | 2003-06-06 | 2006-06-15 | Teiichi Inada | Adhesive sheet, dicing tape intergrated type adhesive sheet, and semiconductor device producing method |
| JP2008218496A (en) * | 2007-02-28 | 2008-09-18 | Namics Corp | Sealing resin film |
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- 2013-04-08 JP JP2013080601A patent/JP2014204033A/en active Pending
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- 2014-03-17 WO PCT/JP2014/057175 patent/WO2014167947A1/en active Application Filing
- 2014-03-17 KR KR1020157031649A patent/KR20150140340A/en not_active Application Discontinuation
- 2014-03-17 SG SG11201508204RA patent/SG11201508204RA/en unknown
- 2014-03-17 CN CN201480020186.5A patent/CN105122433A/en active Pending
- 2014-04-07 TW TW103112647A patent/TW201448062A/en unknown
Patent Citations (4)
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| JPH11251347A (en) * | 1998-03-03 | 1999-09-17 | Hitachi Cable Ltd | Manufacture of semiconductor package |
| US20060128065A1 (en) * | 2003-06-06 | 2006-06-15 | Teiichi Inada | Adhesive sheet, dicing tape intergrated type adhesive sheet, and semiconductor device producing method |
| CN1655353A (en) * | 2004-02-13 | 2005-08-17 | 株式会社东芝 | Stack MCP and manufacturing method thereof |
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| CN112020768A (en) * | 2018-04-24 | 2020-12-01 | 迪思科高科技(欧洲)有限公司 | Apparatus and method for attaching protective tape to semiconductor wafer |
| CN112020769A (en) * | 2018-04-24 | 2020-12-01 | 迪思科高科技(欧洲)有限公司 | Alignment apparatus and alignment method |
| US11935768B2 (en) | 2018-04-24 | 2024-03-19 | Disco Hi-Tec Europe Gmbh | Device and method for attaching protective tape on semiconductor wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| SG11201508204RA (en) | 2015-11-27 |
| WO2014167947A1 (en) | 2014-10-16 |
| JP2014204033A (en) | 2014-10-27 |
| KR20150140340A (en) | 2015-12-15 |
| TW201448062A (en) | 2014-12-16 |
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