CN105097644A - 制造具有绝缘层的集成电路的方法 - Google Patents

制造具有绝缘层的集成电路的方法 Download PDF

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CN105097644A
CN105097644A CN201510261419.7A CN201510261419A CN105097644A CN 105097644 A CN105097644 A CN 105097644A CN 201510261419 A CN201510261419 A CN 201510261419A CN 105097644 A CN105097644 A CN 105097644A
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insulating barrier
annealing
density
fin
groove
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E·T·瑞恩
S·洪
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GlobalFoundries Inc
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Abstract

本发明提供制造具有绝缘层的集成电路的方法。一种制造集成电路的方法包括：形成覆于基板上的一绝缘层，该绝缘层在此形成于沟槽内。用水浸渍该绝缘层，以及退火该绝缘层同时照射它。以约800℃或更低的干退火温度退火该绝缘层。

Description

制造具有绝缘层的集成电路的方法
技术领域
本发明大致涉及制造集成电路的方法，且尤涉及制造具有绝缘层的集成电路同时遵循集成电路的热预算的方法。
背景技术
二氧化硅在许多集成电路中用来作为绝缘体，而二氧化硅的品质会随着密度增加而提高。高品质二氧化硅对于某些蚀刻剂更有抵抗力，而且可以比低品质二氧化硅更加一致的速率蚀刻，因此高品质二氧化硅可简化下游加工操作。有些现有制程将绝缘层沉积于沟槽内，以及沟槽的高宽比倾向随着集成电路的大小减少而增加。许多绝缘层沉积制程经设计成填充高高宽比的沟槽，但是此类绝缘层沉积制程可能无法制造稠密的高品质二氧化硅绝缘。例如，有些可流动化学气相沉积(FCVD)制程能够填充有高高宽比的沟槽，但是该绝缘材料为含硅及氮薄膜。有些高高宽比制程(HARP)能够沉积氧化硅于有高高宽比的沟槽内，但是氧化硅一般不是高品质的稠密材料。
在历史上，FCVD或HARP材料已以约500℃温度暴露于蒸气退火以使硅/氮键转变成氧化硅键，以及开始增密制程(densificationprocess)。蒸气退火之后，以约1,000℃或更多的退火温度干退火，以及该高退火温度可制造稠密的高品质二氧化硅。不过，有些基板有热预算，而且超过热预算温度的退火制程可能使基板劣化。例如，许多含锗基板有低于1,000℃的热预算，其中，该热预算倾向随着锗在基板中的百分比增加而降低。有些III-V族基板，例如砷化镓或砷化铟镓，具有约600℃或约400℃的热预算，而其他基板或集成电路中的组件存在其他的热预算温度极限。
随着集成电路的大小减少，集成电路中的组件的大小也减少。鳍片形成于许多集成电路的基板中，而该等鳍片的强度随着鳍片的大小减少而降低。当鳍片变小时，增密制程倾向使基板的鳍片弯曲或断裂，特别是当集成电路以高温退火时。二氧化硅与某些鳍片的材料有不同热膨胀系数，因此退火的温度愈高，在进行退火时会有愈多的应力转移到所述鳍片。
因此，期望提供用于制造具有能够填充高高宽比沟槽的绝缘材料的集成电路的方法，在此可以低温增密该绝缘材料。另外，期望提供用于形成具有窄鳍片的集成电路的方法，在此当增密相邻鳍片间的绝缘材料时，所述鳍片不会弯曲或断裂。此外，由以下结合附图和本发明背景的详细说明及随附权利要求书将明白本发明具体实施例的其他合意特征及特性。
发明内容
提供数种集成电路及其制造方法。在一示范具体实施例中，一种制造集成电路的方法包括：形成覆于基板上的绝缘层，该绝缘层在此形成于沟槽内。用水浸渍该绝缘层，以及退火该绝缘层同时照射它。该绝缘层以约800℃或更低的干退火温度退火。
在另一具体实施例中，提供一种制造集成电路的方法。形成覆于基板上以及在沟槽内的绝缘层，该绝缘层在此包括含硅及氮薄膜。该含硅及氮薄膜被转变成二氧化硅，以及用干退火增密同时照射它。增密该绝缘层使该绝缘层的密度增加约0.05克/立方厘米(grampercubiccentimeter)或更多。
在又一具体实施例中，提供一种制造集成电路的方法。在基板中形成多个鳍片，在此在相邻鳍片之间界定沟槽。所述多个鳍片有约10纳米或更小的鳍片宽度，以及所述多个鳍片在垂直线的约1度内。该沟槽有约高度为10或更多和约宽度为1的高宽比。在该沟槽内形成绝缘层，在此该绝缘层填充该沟槽约95体积百分比或更多。增密该绝缘层使得所述多个鳍片在垂直线的约2度内。
附图说明
以下将结合附图来描述本发明的具体实施例，共同类似的元件用相同的元件符号表示，其中：
图1至图5的横截面图根据示范具体实施例图示集成电路的一部份以及其制造方法。
符号说明
10集成电路12基板
14鳍片16沟槽
18沟槽高度20沟槽宽度
22鳍片宽度30绝缘层
32液态水34蒸气退火温度
36干退火温度38辐射源。
具体实施方式
以下详细说明本质上只是示范说明而非旨在限制各个具体实施例及其应用和用途。此外，不希望受限于在“背景技术”或“具体实施方式”中提到的任何理论。
绝缘层形成覆于基板上，而该绝缘层为填充沟槽的“间隙填充”层。在间隙填充应用上，通常使用可流动型绝缘层，使得基本上整个间隙用绝缘层填充。许多可流动型绝缘层在填充间隙方面良好，甚至有高高宽比，但是需要高温退火将绝缘材料转变成高品质稠密的二氧化硅可能会超过基板的热预算，而且热膨胀问题可能会损坏基板上的精密结构，如上述。FCVD绝缘层在填充高高宽比间隙方面良好，但是会形成含硅及氮薄膜。藉由用水浸渍该含硅及氮薄膜及/或在有蒸汽的情形下退火，可将该含硅及氮薄膜转变成氧化硅。所形成的氧化硅可能没有如期望中般稠密，所以可能要用另一个退火增密。该增密退火为去除水以及使薄膜进一步交联的干退火，以及藉由在退火期间照射绝缘层可降低该增密退火的温度以提供额外的能量给增密用。在绝缘层增密后，附加的制造步骤可用来制造该集成电路。
请参考图1。集成电路10包括基板12。用于本文的用语“基板”12涵盖由半导体工业传统用来制作电子装置的半导体材料形成的基板12。半导体材料包括单晶硅材料，例如常用于半导体工业的相对纯或轻度掺有杂质的单晶硅材料，以及多晶硅材料，以及与其他元素(例如锗，碳及其类似者)混合的硅。半导体材料也包括其他材料，例如相对纯或掺有杂质的锗、氧化锌、玻璃及其类似者。其他半导体材料包括III-V族半导体材料，例如砷化镓、氮化硼、磷化硼、锑铝(aluminumantimonide)、砷化铟镓，以及周期表第III及V族中的化合物的各种组合。在一示范具体实施例中，该半导体材料为包含硅及锗的单晶基板。基板12可为块状晶圆(如图示)，或可为在由承载晶圆支撑的绝缘层上的半导体材料薄层。
锗具有约937℃的熔点，硅锗基板12的热预算常常小于约1,000℃。该热预算可经设计成防止锗在基板基质内熔化。该“热预算”为基板12、集成电路10或其他结构在不会造成不可接受的伤害或损坏下可暴露的温度限制，或暴露于某些温度的时间限制。在一些实例中，最好尽可能在热预算所允许的最大温度保持愈久愈好，因此损坏可能在较低的温度开始以及随着温度增加。该热预算可设定在损坏被视为太严重的一点，但加工温度保持在热预算下可降低不合意但是仍可制造出可用产品的损坏。硅锗基板12的热预算可取决于锗在基板12中的浓度。有些示范热预算包括不超过约1,000℃，或不超过约800℃，或不超过约600℃的最大温度。在不同具体实施例中，有些III-V族半导体材料有不超过约600℃，或不超过约500℃，或不超过约400℃的热预算。例如，有些III-V族半导体中的砷在超过热预算时可能放出气体，因此基板12的组合物可能改变。
在一示范具体实施例中，形成多个鳍片14于基板12中，鳍片14在此由熟谙此艺者所习知的方法及技术形成。沟槽16界定于相邻鳍片14之间，在此沟槽16有以双箭头18标示的沟槽高度与以双箭头20标示的沟槽宽度。沟槽16具有沟槽高度18相对于沟槽宽度20的高宽比，在某些具体实施例中，该高宽比可约为5比1或更多比1，在其他具体实施例中约为10比1或更多比1，以及又在其他具体实施例中，约为20比1。一般而言，沟槽高宽比愈大，填充沟槽16愈困难。鳍片14具有用双箭头22标示的鳍片宽度，在某些具体实施例中，鳍片宽度22约有10纳米或更小，或在其他具体实施例中，约有20纳米或更小，或又在其他具体实施例中，约有30纳米或更小。鳍片宽度22愈小，鳍片14愈容易损坏，因为薄鳍片14比材料相同的较厚鳍片14更柔弱。鳍片14也可为实质上垂直的，例如在垂直线的约1度内。垂直鳍片14被并入许多集成电路10中。
在图示于图2及图3的一示范具体实施例中，图3为图2的一放大部份，形成覆于基板12上及在沟槽16内的绝缘层30。绝缘层30可实质填充沟槽16，使得绝缘层30填充沟槽16约95体积百分比或更多，以及绝缘层30也可延伸越过及高于沟槽16。在某些具体实施例中，绝缘层30可厚约200至约1,000纳米，但是其他的厚度也有可能。在某些具体实施例中，沟槽16由基板12形成，如图示，但是在其他具体实施例中，该沟槽可由基板12以外的材料(未图示)形成，例如在制造替换性金属栅极(replacementmetalgate)期间形成的沟槽。
绝缘层30可藉由使用可流动化学气相沉积(FCVD)制程沉积含硅及氮薄膜而形成。不被理论所拘束，但是该FCVD制程可形成呈气相的寡聚物，其中，该寡聚物可流动而藉此流入沟槽16，以及该寡聚物在流进定位后随后可进一步聚合。在一示范具体实施例中，该FCVD为等离子化学气相沉积制程，它可使用包含有含硅及氮前驱物的含低碳或无碳硅前驱物。该硅前驱物可为三硅烷基胺(trisilylamineamine)、二硅烷基胺、单硅烷基胺、硅烷或其他前驱物，而该含氮前驱物可为氨、氮气或其他化合物。在替代具体实施例中，也可使用其他FCVD制程。在替代具体实施例中，高高宽比制程(HARP)可用来形成覆于基板12上及在沟槽16内的绝缘层30。在一示范具体实施例中，该HARP在低于大气压力的化学气相沉积中，使用臭氧及正硅酸乙酯(TEOS)作为前驱物可形成二氧化硅绝缘层30，但是在替代具体实施例中，可使用其他前驱物或制程。制造绝缘层30的其他方法包括旋涂玻璃(spin-onglass；SOG)及旋涂电介质(spin-ondielectrics；SOD)。SOG与SOD被应用作为液体，基板12经旋转而散布SOG或SOD。该SOG可包含硅-氧键，以及硅-氢键。SOG市上有售，例如的T-12B，可购自ElectronicMaterials公司，地址在1349MoffettParkDrive,Sunnyvale,CA94089,USA。SOD可为液体化合物含有硅氮烷化合物以及视需要的溶剂，在此该SOD经涂布成可形成含氮及氢的绝缘材料。有些SOD包含催化剂以协助SOD转变成含有二氧化硅。SOD市上有售，例如100，可购自AZElectronicMaterialsUSACorp公司，地址在70MeisterAve.,Branchburg,NJ08876,USA。
用水浸渍绝缘层30，如图4的示范具体实施例所示。可藉由使绝缘层30暴露于液态水32而用水浸渍绝缘层30，其中，在某些具体实施例中，可使用去离子或蒸馏液态水32。在某些具体实施例中，在暴露于液态水32后，在有蒸气的情形下以约500℃或更低的蒸气退火温度34退火绝缘层30。在其他具体实施例中，蒸气退火温度34约为400℃或更低，或在其他具体实施例中，约为300℃或更低。用水浸渍绝缘层30会使具体实施例中的硅/氮键转变成硅/氧键，其中，绝缘层30为含硅及氮薄膜。在某些具体实施例中，低温蒸气退火(蒸气退火温度34约为500℃或更低，400℃或更低，或300℃或更低)可制造密度约为2.05克/立方厘米或更低的绝缘层30，在其他具体实施例中，约为2.15克/立方厘米。绝缘层30在用水浸渍后主要为二氧化硅。低密度二氧化硅有约2.03克/立方厘米的密度，中密度二氧化硅有约2.13克/立方厘米的密度，以及高密度二氧化硅有约2.24克/立方厘米的密度。在某些具体实施例中，蒸气退火制成有低至中密度的绝缘层30。
参考图示于图5的示范具体实施例，绝缘层30以干退火温度36的干退火增密。该干退火可在实质缺水的氮气氛进行，例如水浓度约为百万分的100或更少，使得残留于绝缘层30中的水在干退火期间去除。在替代具体实施例中，可使用除氮以外的干燥气氛，例如氦或其他气体。干退火温度36随着不同具体实施例而有所不同，其中，干退火温度36经选定成是在基板12或集成电路10在干退火时的热预算内。在不同的具体实施例中，干退火温度36可约为800℃或更低，或约为600℃或更低，或约为500℃或更低，或约为400℃或更低。在许多具体实施例中，干退火温度36约等于或高于上述蒸气退火温度34。在一示范具体实施例中，该干退火使绝缘层30的密度增加约0.05克/立方厘米或更多，或在另一具体实施例，增加约0.07克/立方厘米或更多，或在又一具体实施例中，增加约0.10克/立方厘米或更多。该增密制程可在绝缘层30中制造高密度二氧化硅，使得绝缘层30在不同的具体实施例中有约2.18克/立方厘米或更高、或约2.20克/立方厘米或更高、或约2.24克/立方厘米或更高的密度。
较高的干退火温度36倾向产生绝缘层30有较稠密、较高品质的二氧化硅，如上述。在干退火期间可照射绝缘层30以增加能量给退火制程，有助于绝缘层30的增密而不超过热预算。在某些具体实施例中，绝缘层30的干退火及照射可持续约30秒至约30分钟，但是也可使用不同的时间。在一示范具体实施例中，辐射源38在干退火制程期间可用来使绝缘层30暴露于照射能量。在某些具体实施例中，辐射源38可为紫外线灯，但是在各种具体实施例中，辐射源38也可为红外线灯、可见光灯、微波源(如果够多的水留在绝缘层30中)、或电子束源。退火时间可取决于干退火温度36以及所用的辐射源38的强度及类型。在某些具体实施例中，因为上表面起初接受较多照射能量，所以最初可以比下层快的速率增密绝缘层30的上表面。不过，与较低密度的层相比，照射能量更容易通过已增密的层，因此下层的增密速率在上层已增密时可增加。该增密制程可包含一或更多干退火，在干退火期间，相同或不同的辐射源或无辐射源可使用于不同的步骤。
该干退火的相对低温度在温度较高的干退火制程期间减少热循环强度(thermalcycleintensity)。经减少的热循环强度会减少由基板12与绝缘层30的不同膨胀系数所产生的应力，这会减少沟槽16壁上的应力。在沟槽16形成于相邻鳍片14之间的具体实施例中，经减少的应力会减低鳍片14弯曲或断裂的可能性，使得鳍片14在增密制程后大致在垂直线的约2度内。在沟槽16形成于除在相邻鳍片14之间以外的结构中的具体实施例中，经减少的应力可协助防止由于沟槽16的壁与绝缘层30的膨胀系数有差异而损坏或改变。
如熟谙此艺者所了解的，在某些具体实施例中，绝缘层30可用来形成浅沟槽隔离，但是在鳍片场效电晶体(FinFET)中，绝缘层30也可用来作为在相邻鳍片之间的绝缘层30。在集成电路10的制造中，绝缘层30也可用于其他的“间隙填充”操作。然后，如熟谙此艺者所了解的，许多附加加工步骤可用来增加组件以及研发集成电路10。
尽管以上详细说明已陈述至少一示范具体实施例，然而应了解，仍有有许多变体。也应了解，所述示范具体实施例只是范例而非旨在以任何方式限制本申请案的范畴、适用性或组构。反而，上述详细说明是要让熟谙此艺者有个方便的发展蓝图用来具体实作一或更多具体实施例，应了解，描述于一示范具体实施例的元件的功能及配置可做出各种改变而不脱离如随附权利要求书所述的范畴。

Claims (20)

1.一种制造集成电路的方法，包含：
形成覆于基板上的绝缘层，其中，该绝缘层形成于沟槽内；
以水浸渍该绝缘层；以及
以干退火温度退火该绝缘层，同时照射该绝缘层，其中，该干退火温度约为800℃或更低。
2.根据权利要求1所述的方法，其中，形成该绝缘层包括：
藉由化学气相沉积法沉积覆于该基板上的含硅及氮薄膜。
3.根据权利要求1所述的方法，其中，形成该绝缘层包括：形成覆于该基板上的该绝缘层，其中，该沟槽具有约5/1或更多的高宽比，以及其中，该绝缘层填充该沟槽约95体积百分比或更多。
4.根据权利要求3所述的方法，其中，退火该绝缘层包括：增密该绝缘层至约2.20克/立方厘米或更大，其中，该绝缘层在退火后包含二氧化硅。
5.根据权利要求1所述的方法，其中，浸渍该绝缘层包括：
使该绝缘层暴露于水；以及
在有蒸气的情形下以约500℃或更低的蒸气退火温度，退火该绝缘层。
6.根据权利要求1所述的方法，其中，退火该绝缘层包括：以紫外光照射该绝缘层。
7.根据权利要求1所述的方法，更包括：
形成多个鳍片于该基板中，使得该沟槽在相邻鳍片之间，其中，该多个鳍片具有约10纳米或更小的鳍片宽度，以及其中，该多个鳍片在垂直线的1度内；以及
其中，退火该绝缘层包括：使该多个鳍片保持在垂直线的约2度内。
8.根据权利要求1所述的方法，其中，退火该绝缘层包括：退火该绝缘层，其中，该干退火温度约为600℃或更低。
9.根据权利要求1所述的方法，其中，退火该绝缘层包括：退火该绝缘层，其中，该干退火温度约为500℃或更低。
10.根据权利要求1所述的方法，其中：
退火该绝缘层包括：退火该绝缘层，其中，该干退火温度约为400℃或更低；以及
以水浸渍该绝缘层包括：于约400℃或更低的蒸气退火温度，以水浸渍该绝缘层。
11.一种制造集成电路的方法，包含：
形成覆于基板上的绝缘层，其中，该绝缘层形成于沟槽内，以及其中，该绝缘层包括含硅及氮薄膜；
使该含硅及氮薄膜转变成二氧化硅；以及
以干退火增密该绝缘层，同时照射该绝缘层，其中，增密该绝缘层使该绝缘层的密度增加约0.05克/立方厘米或更多。
12.根据权利要求11所述的方法，其中，增密该绝缘层包括：以紫外光照射该绝缘层。
13.根据权利要求12所述的方法，其中，增密该绝缘层包括：以约800℃或更低的退火温度干退火。
14.根据权利要求12所述的方法，其中，增密该绝缘层包括：以约600℃或更低的干退火温度干退火。
15.根据权利要求12所述的方法，其中，增密该绝缘层包括：以约400℃或更低的退火温度干退火。
16.根据权利要求11所述的方法，其中，使该含硅及氮薄膜转变成该二氧化硅包括：以约500℃或更低的蒸气退火温度蒸气退火。
17.一种制造集成电路的方法，包含：
形成多个鳍片于基板中，藉此在相邻鳍片之间界定沟槽，其中，该鳍片具有约10纳米或更小的鳍片宽度，其中，该鳍片在垂直线的约1度内，以及其中，该沟槽具有约高度为10或更多和宽度为1的高宽比；
形成绝缘层于该沟槽内，其中，该绝缘层填充该沟槽约95体积百分比或更多；
增密该绝缘层，使得该鳍片在垂直线的约2度内。
18.根据权利要求17所述的方法，其中，增密该绝缘层包括：使该绝缘层的密度增加约0.05克/立方厘米或更多。
19.根据权利要求17所述的方法，其中，增密该绝缘层包括：以约600度或更低的干退火温度干退火。
20.根据权利要求17所述的方法，其中，增密该绝缘层包括：产生密度约有2.20克/立方厘米或更多的该绝缘层。
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