CN105070757A - 改善超级结器件的开关特性的结构 - Google Patents

改善超级结器件的开关特性的结构 Download PDF

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CN105070757A
CN105070757A CN201510507319.8A CN201510507319A CN105070757A CN 105070757 A CN105070757 A CN 105070757A CN 201510507319 A CN201510507319 A CN 201510507319A CN 105070757 A CN105070757 A CN 105070757A
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王飞
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种改善超级结器件的开关特性的结构，超级结器件包括单元区和终端区；在单元区形成有超级结器件的单元结构，各单元结构包括MOSFET器件单元，MOSFET器件单元包括形成于超级结顶部的阱区和栅极；终端区的超级结顶部形成有介质层以及覆盖在介质层表面的多晶硅层或金属层，多晶硅层或金属层和栅极相连接，由多晶硅层或金属层和其底部的介质层和超级结组成耦合电容，耦合电容在超级结器件的关断时将终端区的超级结的电压耦合到单元区的栅极从而使单元区的MOSFET器件单元的沟道的关断时间延长且该关断时间足够使浪涌电流泄流通过超级结器件。本发明能使得在器件关断后的电流震荡得到缓解，降低了EMI发生异常的风险。

Description

改善超级结器件的开关特性的结构
技术领域
本发明涉及一种半导体集成电路，特别是涉及一种改善超级结器件的开关特性的结构。
背景技术
目前超级结产品的应用越来越多，超级结(SJ)产品相对现有垂直双扩散MOSFET(VDMOS)有着更低的比导通电阻的优势，但是由于超级结产品的结构特点，超级结产品的开关时间要比VDMOS要小很多，这也导致了在系统上会容易发生超级结的开关特性太快和系统上的其他器件不匹配，导致在开关阶段的电流震荡，EMI，以及系统不稳定等问题，如图1A所示，是现有VDMOS器件体二极管反向恢复过程波形；如图1B所示，是现有超级结MOSFET器件体二极管反向恢复过程波形；波形图中Vgs2表示MOSFET的栅极电压，Isd1表示MOSFET的源漏电流，Vds1表示MOSFET的源漏电压，MOSFET器件在关断后由体区和基底直接的体二极管会存在一个反向恢复的过程，比较图1A和图1B可知，现有超级结MOSFET器件体二极管反向恢复过程出现了电流振荡。
发明内容
本发明所要解决的技术问题是提供一种改善超级结器件的开关特性的结构,能使得在器件关断后的电流震荡得到缓解，降低了EMI发生异常的风险。
为解决上述技术问题，本发明提供的改善超级结器件的开关特性的结构的超级结器件包括单元区即原胞区(cellarea)和终端区，终端区环绕在单元区的周侧，超级结器件的超级结由形成于外延层中的交替排列的P型薄层和N型薄层组成；在所述单元区形成有超级结器件的单元结构，各所述单元结构的顶部包括有MOSFET器件单元，所述MOSFET器件单元包括形成于所述超级结顶部的阱区和栅极，被所述栅极覆盖的阱区的表面用于形成连接所述MOSFET器件单元的源漏区的沟道，沟道的导通和关断由所述栅极的电压确定。
各所述超级结器件的终端区的超级结顶部形成有介质层以及覆盖在所述介质层表面的多晶硅层或金属层，所述多晶硅层或金属层和所述栅极相连接，由所述多晶硅层或金属层和其底部的所述介质层和所述终端区的超级结组成耦合电容，该耦合电容在所述超级结器件的关断时将所述终端区的超级结的电压耦合到所述单元区的栅极从而使所述单元区的MOSFET器件单元的沟道的关断时间延长且该关断时间足够使浪涌电流泄流通过所述超级结器件。
进一步的改进是，所述多晶硅层或金属层和所述栅极的材料直接相连接，或者所述多晶硅层或金属层和所述栅极之间通过接触孔和正面金属层连接。
进一步的改进是，所述多晶硅层或金属层覆盖于整个所述超级结器件的终端区；或者，所述多晶硅层或金属层覆盖于部分所述超级结器件的终端区。
进一步的改进是，所述介质层的厚度要求满足能耐受在所述超级结器件的关断瞬间所述终端区的超级结的电压和所述单元区的栅极的电压差。
进一步的改进是，所述超级结器件为超级结MOEFET。
本发明通过在超级结器件的终端区顶部形成和栅极相连的多晶硅层或金属层，多晶硅层或金属层和底部通过介质层隔离的超级结之间形成耦合电容，该耦合电容能在超级结器件的关断时将终端区的超级结的电压耦合到单元区的栅极从而使单元区的MOSFET器件单元的沟道的关断时间延长从而能使浪涌电流通过超级结器件的沟道泄流，从而能使得在器件关断后的电流震荡得到缓解，降低了EMI发生异常的风险。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1A是现有VDMOS器件体二极管反向恢复过程波形；
图1B是现有超级结MOSFET器件体二极管反向恢复过程波形；
图2是本发明实施例超级结器件的结构示意图。
具体实施方式
如图2所示，是本发明实施例超级结器件的结构示意图，本发明实施例改善超级结器件的开关特性的结构的超级结器件包括单元区和终端区，图2中虚线AA的左侧示意为单元区、右侧示意为终端区。终端区环绕在单元区的周侧，超级结器件的超级结由形成于外延层101中的交替排列的P型薄层103和N型薄层102组成；在所述单元区形成有超级结器件的单元结构，各所述单元结构的顶部包括有MOSFET器件单元，所述MOSFET器件单元包括形成于所述超级结顶部的阱区104和栅极105，被所述栅极105覆盖的阱区104的表面用于形成连接所述MOSFET器件单元的源漏区的沟道，沟道的导通和关断由所述栅极105的电压确定。
各所述超级结器件的终端区的超级结顶部形成有介质层106以及覆盖在所述介质层106表面的多晶硅层或金属层107，所述多晶硅层或金属层107和所述栅极105相连接，由所述多晶硅层或金属层107和其底部的所述介质层106和所述终端区的超级结组成耦合电容，该耦合电容在所述超级结器件的关断时将所述终端区的超级结的电压耦合到所述单元区的栅极105从而使所述单元区的MOSFET器件单元的沟道的关断时间延长且该关断时间足够使浪涌电流泄流通过所述超级结器件。
图2中，所述多晶硅层或金属层107和所述栅极105的材料直接相连接。在其他实施例中，所述多晶硅层或金属层107和所述栅极105之间的连接关系也能为通过接触孔和正面金属层连接。
所述多晶硅层或金属层107覆盖于整个所述超级结器件的终端区；或者，所述多晶硅层或金属层107覆盖于部分所述超级结器件的终端区。
所述介质层106的厚度要求满足能耐受在所述超级结器件的关断瞬间所述终端区的超级结的电压和所述单元区的栅极105的电压差。
所述超级结器件为超级结MOEFET。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (5)

1.一种改善超级结器件的开关特性的结构，其特征在于：超级结器件包括单元区和终端区，终端区环绕在单元区的周侧，超级结器件的超级结由形成于外延层中的交替排列的P型薄层和N型薄层组成；在所述单元区形成有超级结器件的单元结构，各所述单元结构的顶部包括有MOSFET器件单元，所述MOSFET器件单元包括形成于所述超级结顶部的阱区和栅极，被所述栅极覆盖的阱区的表面用于形成连接所述MOSFET器件单元的源漏区的沟道，沟道的导通和关断由所述栅极的电压确定；
各所述超级结器件的终端区的超级结顶部形成有介质层以及覆盖在所述介质层表面的多晶硅层或金属层，所述多晶硅层或金属层和所述栅极相连接，由所述多晶硅层或金属层和其底部的所述介质层和所述终端区的超级结组成耦合电容，该耦合电容在所述超级结器件的关断时将所述终端区的超级结的电压耦合到所述单元区的栅极从而使所述单元区的MOSFET器件单元的沟道的关断时间延长且该关断时间足够使浪涌电流泄流通过所述超级结器件。
2.如权利要求1所述的改善超级结器件的开关特性的结构，其特征在于：所述多晶硅层或金属层和所述栅极的材料直接相连接，或者所述多晶硅层或金属层和所述栅极之间通过接触孔和正面金属层连接。
3.如权利要求1所述的改善超级结器件的开关特性的结构，其特征在于：所述多晶硅层或金属层覆盖于整个所述超级结器件的终端区；或者，所述多晶硅层或金属层覆盖于部分所述超级结器件的终端区。
4.如权利要求1所述的改善超级结器件的开关特性的结构，其特征在于：所述介质层的厚度要求满足能耐受在所述超级结器件的关断瞬间所述终端区的超级结的电压和所述单元区的栅极的电压差。
5.如权利要求1所述的改善超级结器件的开关特性的结构，其特征在于：所述超级结器件为超级结MOEFET。
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CN107293601A (zh) * 2016-04-12 2017-10-24 朱江 一种肖特基半导体装置及其制备方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107293601A (zh) * 2016-04-12 2017-10-24 朱江 一种肖特基半导体装置及其制备方法
CN107293601B (zh) * 2016-04-12 2021-10-22 朱江 一种肖特基半导体装置及其制备方法

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