CN105047637A - 用于扁平无引线封装的通用引线框架 - Google Patents

用于扁平无引线封装的通用引线框架 Download PDF

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Publication number
CN105047637A
CN105047637A CN201510181241.5A CN201510181241A CN105047637A CN 105047637 A CN105047637 A CN 105047637A CN 201510181241 A CN201510181241 A CN 201510181241A CN 105047637 A CN105047637 A CN 105047637A
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hurdle
leadframe panel
solid
lead
master
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CN201510181241.5A
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CN105047637B (zh
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麦智皓
R·R·A·阿利纳
黄钰雁
N·莫斑
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
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  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
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Abstract

本公开涉及用于扁平无引线封装的通用引线框架。一种用于半导体封装的通用引线框架包括实心的引线框架板和多个栏，实心的引线框架板包括导电材料，并且多个栏被刻蚀到引线框架板中并且被以预定引线节距来分布，使得通用引线框架具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧。一种制造通用引线框架的方法包括提供导电材料的实心的引线框架板，以及将多个栏刻蚀到引线框架板中，使得栏以预定引线节距来分布并且通用引线框架具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧。还提供了一种使用通用引线框架制造模制半导体封装的方法。

Description

用于扁平无引线封装的通用引线框架
技术领域
本申请涉及扁平无引线封装，具体地涉及用于扁平无引线封装的引线框架。
背景技术
诸如QFN(方形扁平无引线)和DFN(双边扁平无引线)之类的扁平无引线封装将集成电路物理地和电地连接到诸如印刷电路板(PCB)之类的板。扁平无引线，也称为微引线框架(MLP)和SON(小外形无引线)，是用于在无需通孔的情况下将IC(集成电路)连接到PCB表面的表面安装技术。扁平无引线是提供由平面铜引线框架基板制成的塑料包封封装的近芯片尺度封装技术。封装底部上的外围触点提供至PCB的电连接。
用于扁平无引线封装的引线框架按照惯例基于特定引线数、暴露的焊盘尺寸和本体尺寸被定制。例如，第一引线框架设计用于具有5x5mm的本体尺寸和3x3mm的暴露焊盘尺寸的32引脚数QFN封装，并且不同的引线框架设计用于具有7x7mm的本体尺寸和5x5mm的暴露焊盘尺寸的48引脚数QFN封装。具有太多引线框架设计增加生产中的封装设计和存货成本，并且增加零件号码管理复杂性。
发明内容
根据用于半导体封装的通用引线框架的一个实施例，通用引线框架包括实心的引线框架板和多个栏，实心的引线框架板包括导电材料，并且多个栏被刻蚀到引线框架板中并且被以预定引线节距来分布，使得通用引线框架具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧。
根据一种制造用于半导体封装的通用引线框架的方法的实施例，该方法包括提供包括导电材料的实心的引线框架板，以及将多个栏刻蚀到引线框架板中，使得栏以预定引线节距来分布并且通用引线框架具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧。
根据一种制造模制半导体封装的方法的实施例，该方法包括：提供包括多个栏的引线框架板，多个栏被刻蚀到引线框架板中，使得引线框架板具有与栏相对的实心的第一主侧和与第一主侧相对的图形化的第二主侧；将多个半导体裸片附连到栏的第一组；将半导体裸片的端子连接到与第一组不同的栏的第二组；用模制化合物包封半导体裸片和端子连接；刻蚀引线框架板的实心的第一主侧以将实心引线框架板分割为引线和裸片焊盘，每个裸片焊盘包括第一组中的多个栏并且每个引线包括第二组中的一个或者多个栏；以及切断模制化合物以形成单独的模制半导体封装。
本领域技术人员在阅读以下详细描述并且观看附图之后将认识到附加的特征和优点。
附图说明
附图的元件不一定相对于彼此成比例。同样的附图标记标示对应的相似部分。各个图示的实施例的特征可以被组合，除非它们彼此排斥。实施例被描绘在附图中并且在以下详细描述中详述。
图1，其包括图1A至图1D，图示了通用引线框架的实施例的不同视图。
图2，其包括图2A至图2C，图示了制造通用引线框架的方法的实施例的不同阶段。
图3，其包括图3A至图3H，图示了从通用引线框架制造模制半导体封装的方法的实施例的不同阶段。
具体实施方式
本文所描述的实施例提供一种用于诸如QFN和DFN之类的扁平无引线封装的通用引线框架。通用引线框架设计支持具有相同框架厚度和引线节距的任何封装设计，而无需提供多个引线框架设计以支持整个封装平台。不同的占位面积、本体尺寸和引脚数可以后续通过在封装组装工艺期间个性化通用引线框架来实现。通用引线框架设计可以具有用于更好的电性能(更低的线电阻)的最短的可能线长、通过提供限定厚度类型的单个通用引线框架来最小化引线框架设计工艺以及降低用于具有不同引线数(例如，32、48等)、本体尺寸(例如，5x5mm、7x7mm等)和暴露焊盘尺寸(例如，3x3mm、5x5mm等)的封装平台的存货成本。
图1，其包括图1A至图1D，图示了用于诸如QFN和DFN之类的扁平无引线封装的通用引线框架100的实施例。图1A示出了通用引线框架100的顶视平面图，并且图1B示出了通用引线框架100的侧视图。图1C示出了图1A中标注为“A”的通用引线框架的部分的放大的顶视平面图，并且图1D示出了对应的侧视图。作为示例，通用引线框架100被示出为四格设计，但是可以包括任何数目的格(panel)102(1、2、3、4等)。
通用引线框架100包括实心的引线框架板104，实心的引线框架板104包括导电材料，例如，铜膜、铜钼化合物、诸如铜镍锡合金之类的铜合金、诸如42合金之类的镍铁合金、ASTMF-15合金(由29％镍、17％钴和平衡铁构成)、纯镍等。引线框架板104可以电镀有例如NiPdAu、Ag、Cu等。引线框架板104是实心的，在于引线框架板104不由破裂或者开口中断，即在封装组装工艺之前，引线和裸片焊盘不被雕刻或者刻蚀到引线框架板104中。如此，引线框架板104在不具有引线和裸片焊盘的情况下进入封装组装工艺，引线和裸片焊盘是以后在该工艺中形成的。
通用引线框架100还包括刻蚀到引线框架板104中的多个栏(岛)106。这样，通用引线框架100具有与栏106相对的实心的底侧101和与底侧101相对的图形化的顶侧103。在后来的封装组装期间，半导体裸片被附连到栏106的第一(例如，内部)组108并且半导体裸片的端子被连接到与第一组108不同的栏106的第二(例如，外部)组110。最终封装占位面积在具有针对通用引线框架100的实心底侧101的附加刻蚀工艺的封装组装期间实现。
每个栏106具有如图1C和1D所示的限定的长度(L)、宽度(W)和厚度(Tc)。栏106的顶表面107可以具有如图1C所示的正方形、矩形、圆形、椭圆形或者任何其他期望的形状。栏106可以具有近似相同的长度、宽度和厚度，即在用于形成栏106的刻蚀工艺的公差内。在一个实施例中，栏106具有近似1μm至5μm的厚度。在其他实施例中，栏106的厚度在该范围之外。栏106可以包括一种或者多种材料。例如，栏106可以包括较厚(核心)铜材料和铝/NiPdAu等的较薄外部金属化电镀。栏106可以包括足够用于粘附后来将提供的模制化合物的任何材料系统。每个栏106的厚度对应于在刻蚀工艺期间从实心的引线框架板104的顶侧103的未掩蔽/未保护部分去除的材料的量。实心的引线框架板104的被刻蚀部分具有实心厚度Tb，并且实心的引线框架板104的未刻蚀部分具有厚度Ttotal＝Tb+Tc。
栏106可以被分布在具有预定引线节距(P)(即在封装的邻近引线之间的预定距离)的阵列中。预定引线节距可以满足诸如在JEDEC外形MO-220标准中规定的标准化引线节距。例如，预定引线节距可以是0.65mm、0.5mm或者0.4mm。也可以使用可能满足或者可能不满足标准化引线节距的其他预定引线节距。即，栏106的引线节距可以是标准的引线节距或者定制的引线节距。无论哪种情况，引线框架板104的外周边112都可以没有栏106，并且栏106以均匀隔开的组114来布置。栏106的组114彼此通过引线框架板104的没有栏106的区域116而隔开。在多格通用引线框架的情况下，这样的区域116可以对应于格102之间的空间。
图2，其包括图2A至图2C，图示了制造通用引线框架100的方法的实施例。该方法包括提供具有底侧101和顶侧103的实心的引线框架板100。引线框架板100包括导电材料，例如铜膜、铜钼化合物、诸如铜镍锡合金之类的铜合金、诸如42合金之类的镍铁合金、ASTMF-15合金(由29％镍、17％钴和平衡铁构成)、纯镍等，如图2A所示。引线框架板100可以电镀有例如NiPdAu、Ag、Cu等。栏106可以通过光化学刻蚀被刻蚀到实心的引线框架板100中。例如，引线框架板100的顶表面103可以涂布有光致抗蚀剂。引线框架板100的顶表面103然后可以被清洗，如果需要接着进行层压。然后，例如在紫外光源和精密图案玻璃/膜光掩膜的帮助下，光致抗蚀剂被暴露于期望的栏阵列图案。光掩膜可以通过将客户图纸(原图文件)转换为单条母掩膜或者多条母掩膜而生成。在每种情况下，将保持未刻蚀的引线框架板100的区域涂布有暴露的抗蚀剂200，并且待刻蚀的引线框架板100的区域无暴露的抗蚀剂200，如图2A所示。暴露的抗蚀剂200的图案限定将被刻蚀到引线框架板100的顶表面103中的栏106的长度、宽度和节距。
诸如酸之类的化学刻蚀剂然后被导向引线框架板100的暴露的区域，以将栏106刻蚀到引线框架板100的顶表面103中。栏106的厚度(Tc)依赖于刻蚀工艺的持续时间。在一个实施例中，化学刻蚀剂被导向引线框架板100的暴露的区域足够长的时间段，使得栏106在化学刻蚀工艺完成之后具有近似1μm至5μm的厚度Tc。
然后使用任何标准光致抗蚀剂去除工艺去除暴露的抗蚀剂200，如图2C所示。栏106的厚度对应于在化学刻蚀工艺期间从实心的引线框架板100的顶表面103的未掩蔽/未保护区域去除的材料的量。实心的引线框架板100的蚀刻部分具有实心厚度Tb，并且实心的引线框架板100的未刻蚀部分具有如本文先前所描述的厚度Ttotal＝Tb+Tc。
除了化学刻蚀工艺之外，栏106可以通过实心的引线框架板100的顶表面103的激光或者水喷射刻蚀形成，其中激光/水喷射工艺的能量和持续时间决定栏106的厚度Tc。栏106的最小宽度、长度和节距，在激光/水喷射刻蚀栏106的情况下是激光/水喷射工艺的精度的函数或者在化学刻蚀栏106的情况下是最小光刻特征尺寸的函数。无论哪种情况，栏106可以被刻蚀到引线框架板100中，使得栏106被分布在具有预定引线节距的阵列中并且使得通用引线框架具有与栏106相对的实心的底侧101和图形化的顶侧103。
通用引线框架被进行尺寸设计以由半导体封装设备接收，即用于从引线框架组装半导体封装的任何设备，包括诸如裸片附连设备、接线键合设备和模制设备之类的设备。
图3，其包括图3A至图3H，图示了从通用引线框架制造模制半导体封装的方法的实施例。该方法包括提供包括具有多个栏106的引线框架板104的通用引线框架100，多个栏106被刻蚀到引线框架板104中使得引线框架板104具有与栏106相对的实心的底侧101和图形化的顶侧103，如图3A所示。引线框架100被认为是通用的，在于使用相同的引线框架设计可以支持不同的裸片尺寸、不同的线布局、不同的封装占位面积以及倒装工艺。
图3B示出了在多个半导体裸片304、306被附连到栏106的第一(例如，内部)组之后的制造方法。半导体裸片304、306可以通过诸如焊料、胶或者裸片附连膜之类的任何标准裸片附连材料被附连到栏106的第一组108。附连到第一组108中的栏106的裸片304、306的背侧可以是电活性或者电惰性的。在电活性背侧的情况下，诸如裸片附连膜之类的导热粘合剂可以用于将裸片304、306附连到第一组108中的栏106。裸片附连膜的环氧树脂被固化并且引线框架板104可以例如通过标准等离子体清洗工艺被清洗。
在焊料附连的情况下，在将半导体裸片304、306焊接到栏106的第一组108之前或者之后，栏间间隙300可以由环氧树脂或者其他标准底部填充剂302填充。例如，可以使用倒装工艺将裸片306中的一些或者全部附连到栏106的第一组108，如图3B的右手侧所示。在这种情况下，沉积在倒装裸片306的焊盘上的焊料凸点308被用于将倒装裸片306附连到通用引线框架100的不同栏106。在裸片附连膜的情况下，栏间间隙300可以保持未填充，如图3B的左手侧所示。
在每种情况下，半导体裸片304、306的端子被连接到与第一组106不同的栏106的第二组110。在图3C的右手侧中示出的倒装芯片306的情况下，栏106的第一组108和第二组110被布置在裸片306之下。对于倒装裸片306，所有裸片端子(电和热端子)通过焊料凸点308被焊接到布置在裸片306之下的栏106。在图3C的左手侧中示出的其他(非倒装)裸片304的情况下，栏106的第一组108被布置在裸片304之下，并且栏106的第二组110与裸片304横向上隔开并且未由裸片304覆盖。这些裸片304的端子可以通过如图3C所示的接线键合310、接线带、金属夹等被附连到栏106的第二组110。在每种情况下，引线框架板104的实心底侧101在端子附连工艺期间可以被加热。
在一个实施例中，邻近引线框架板104的实心底侧101的实心加热器块312加热引线框架板104，同时半导体裸片304、306的端子被连接到栏106的第二组110。加热器块312是实心的，即，不由破裂或者开口中断，因为引线框架板104的底侧101也是实心的。如果引线框架板104的底侧101相反被刻蚀或者雕刻成引线和裸片焊盘的图案，则加热器块312可以不是实心块，但是相反必须被仔细地设计以支持这样的构造的引线框架板。实心加热器板312是更简单并且更低成本的方法。
半导体裸片304、306和端子连接然后由模制化合物314包封，如图3D所示。可以使用任何标准的模制工艺。
引线框架板104的实心底侧101可以被减薄，如图3E所示。可以使用任何标准的引线框架减薄工艺。
然后，引线框架板104的实心底侧101可以被刻蚀以将实心引线框架板分割为引线和裸片焊盘。每个裸片焊盘包括第一组108中的多个栏106，并且每个引线包括第二组110中的一个或者多个栏106。图3F示出了在刻蚀的一个实施例期间的组件的部分。根据该实施例，诸如经显影的光致抗蚀剂之类的刻蚀掩膜316被形成在引线框架板104的实心底侧101上，并且诸如酸之类的化学刻蚀剂被涂布到未由刻蚀掩膜316覆盖的引线框架板104的底侧101的区域，如由图3F中的向上的箭头所指示的。图3G示出了在刻蚀的另一实施例期间的组件的部分。根据该实施例，实心的引线框架板104通过实心底侧101的激光或者水喷射刻蚀被分割为引线和裸片焊盘，如由向上箭头所指示的。
在每种情况下，第二组110中的栏106可以限定模制半导体封装的引线占位面积，并且可以以模制半导体封装的引线所需的预定引线节距来分布。如此，被刻蚀到引线框架板的实心底侧中的引线可以具有与第二组110中的栏106相同的尺寸(宽度、长度、节距)，并且每个引线包括第二组110中的栏106之一。在一个实施例中，第二组110中的栏106的预定引线节距满足诸如在JEDEC外形MO-220标准中规定的标准化引线节距。例如，预定引线节距可以是0.65mm、0.5mm或者0.4mm。在另一实施例中，第二组110中的栏106的间隔并不限定模制半导体封装的引线节距。作为替代，引线节距由被刻蚀到引线框架板104的实心底侧101中的引线的间隔限定。即，引线框架板104的实心底侧101的刻蚀限定模制半导体封装的引线占位面积以及模制半导体封装的引线所需的预定引线节距。根据该实施例，每个引线可以包括第二组110中的一个或者多个栏106。通常，模制半导体封装的引线节距可以满足或者可以不满足标准化引线节距。即，模制半导体封装的引线节距可以是标准的引线节距或者定制的引线节距。
然后，切断模制化合物314以形成单独的模制半导体封装318，其中之一在图3H中示出。诸如锯切320之类的任何标准封装单片化工艺可以用于分离单独的封装318。图3H也示出了引线框架板104的刻蚀后的底侧101，其先前被分割为引线322和裸片焊盘324。如前文所描述的，每个裸片焊盘324包括第一组108中的多个栏106，并且每个引线322包括第二组110中的一个或者多个栏106。
为了描述的简单起见，使用诸如“之下”、“下方”、“下”、“之上”、“上”等空间相对术语以解释一个元件相对于第二元件的定位。这些术语旨在包含除了图中描述的那些之外的封装的不同的定向。进一步地，诸如“第一”、“第二”等术语也用于描述各种元件、区域、部分等并且也并不旨在限制。同样的术语贯穿描述指代同样的元件。
如本文所使用的，术语“具有”、“包含”、“包括”、“含有”等是指示所陈述的元件或者特征的存在但并不排除附加的元件或者特征的开放式术语。除非上下文另外明确指出，否则冠词“一”、“一个”和“该”旨在包括单数和复数。
在认识到变化和应用的上述范围的情况下，应当理解的是，本发明不由前述描述限制，也不由附图限制。相反，本发明仅由以下权利要求及其等价方案限制。

Claims (20)

1.一种用于半导体封装的通用引线框架，包括：
实心的引线框架板，包括导电材料；以及
多个栏，被刻蚀到所述引线框架板中，并且被以预定引线节距来分布，使得所述通用引线框架具有与所述栏相对的实心的第一主侧和与所述第一主侧相对的图形化的第二主侧。
2.根据权利要求1所述的通用引线框架，其中所述预定引线节距是0.65mm、0.5mm或者0.4mm之一。
3.根据权利要求1所述的通用引线框架，其中所述引线框架板的外周边无所述栏，并且其中所述栏以均匀隔开的栏的组来布置，栏的所述组彼此通过所述引线框架板的无所述栏的区域而隔开。
4.根据权利要求1所述的通用引线框架，其中所述栏具有近似相同的长度、宽度和厚度。
5.根据权利要求1所述的通用引线框架，其中所述栏具有近似1μm至5μm的厚度。
6.一种制造用于半导体封装的通用引线框架的方法，所述方法包括：
提供包括导电材料的实心的引线框架板；以及
将多个栏刻蚀到所述引线框架板中，使得所述栏以预定引线节距来分布并且所述通用引线框架具有与所述栏相对的实心的第一主侧和与所述第一主侧相对的图形化的第二主侧。
7.根据权利要求6所述的方法，其中所述栏被刻蚀到所述引线框架板中，使得所述栏以0.65mm、0.5mm或者0.4mm的预定引线节距来分布。
8.根据权利要求6所述的方法，其中所述栏被刻蚀到所述引线框架板中，使得所述引线框架板的外周边无所述栏，并且所述栏以均匀隔开的栏的组来布置，栏的所述组彼此通过所述引线框架板的无所述栏的区域而隔开。
9.根据权利要求6所述的方法，其中所述栏被刻蚀到所述引线框架板中，使得所述栏具有近似相同的长度、宽度和厚度。
10.根据权利要求6所述的方法，其中将所述栏刻蚀到所述引线框架板中包括：
刻蚀所述实心的引线框架板足够长的时间段，使得所述栏在所述刻蚀完成之后具有近似1μm至5μm的厚度。
11.一种制造模制半导体封装的方法，所述方法包括：
提供包括多个栏的引线框架板，所述多个栏被刻蚀到所述引线框架板中，使得所述引线框架板具有与所述栏相对的实心的第一主侧和与所述第一主侧相对的图形化的第二主侧；
将多个半导体裸片附连到所述栏的第一组；
将所述半导体裸片的端子连接到所述栏的与所述第一组不同的第二组；
用模制化合物包封所述半导体裸片和端子连接；
刻蚀所述引线框架板的所述实心的第一主侧，以将所述实心的引线框架板分割为引线和裸片焊盘，每个裸片焊盘包括所述第一组中的多个栏，并且每个引线包括所述第二组中的一个或者多个栏；以及
切断所述模制化合物以形成单独的模制半导体封装。
12.根据权利要求11所述的方法，进一步包括在所述半导体裸片被附连到所述栏的所述第一组之前填充所述栏之间的间隙。
13.根据权利要求11所述的方法，其中刻蚀所述引线框架板的所述实心的第一主侧以将所述实心的引线框架板分割为引线和裸片焊盘包括：
在所述引线框架板的所述实心的第一主侧上形成刻蚀掩膜；以及
向所述引线框架板的所述实心的第一主侧的未由所述刻蚀掩膜覆盖的区域施加刻蚀剂。
14.根据权利要求11所述的方法，其中所述实心的引线框架板通过所述实心的第一主侧的激光或者水喷射刻蚀被分割为引线和裸片焊盘。
15.根据权利要求11所述的方法，其中所述半导体裸片通过焊料、胶或者裸片附连膜被附连到所述栏的所述第一组。
16.根据权利要求11所述的方法，进一步包括：
用邻近所述实心的第一主侧的实心加热器块加热所述引线框架板的所述实心的第一主侧，同时将所述半导体裸片的所述端子连接到所述栏的所述第二组。
17.根据权利要求11所述的方法，其中所述第二组中的所述栏限定所述模制半导体封装的引线占位面积并且以所述模制半导体封装的所述引线所需的预定引线节距来分布。
18.根据权利要求17所述的方法，其中所述预定引线节距是0.65mm、0.5mm或者0.4mm。
19.根据权利要求11所述的方法，其中所述引线框架板的所述实心的第一主侧的所述刻蚀限定所述模制半导体封装的引线占位面积和所述模制半导体封装的所述引线所需的预定引线节距。
20.根据权利要求11所述的方法，其中所述栏均匀间隔开并且具有近似相同的长度、宽度和厚度。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1836319A (zh) * 2003-06-25 2006-09-20 先进互连技术有限公司 半导体封装中芯片衬垫布线的引线框
CN101601133A (zh) * 2006-10-27 2009-12-09 宇芯（毛里求斯）控股有限公司 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US8063470B1 (en) * 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
CN102842515A (zh) * 2011-06-23 2012-12-26 飞思卡尔半导体公司 组装半导体器件的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
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JP4533875B2 (ja) * 2006-09-12 2010-09-01 株式会社三井ハイテック 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法
CN100555592C (zh) * 2007-02-08 2009-10-28 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
TWI420630B (zh) * 2010-09-14 2013-12-21 Advanced Semiconductor Eng 半導體封裝結構與半導體封裝製程
CN102629599B (zh) * 2012-04-06 2014-09-03 天水华天科技股份有限公司 四边扁平无引脚封装件及其生产方法
US20150076675A1 (en) * 2013-09-16 2015-03-19 Stmicroelectronics, Inc. Leadframe package with wettable sides and method of manufacturing same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1836319A (zh) * 2003-06-25 2006-09-20 先进互连技术有限公司 半导体封装中芯片衬垫布线的引线框
CN101601133A (zh) * 2006-10-27 2009-12-09 宇芯（毛里求斯）控股有限公司 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US8063470B1 (en) * 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
CN102842515A (zh) * 2011-06-23 2012-12-26 飞思卡尔半导体公司 组装半导体器件的方法

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