CN105022859A - Quantitative analysis method for heavy-ion single-particle multi-bit upset effect of device - Google Patents

Abstract

The present invention discloses a quantitative analysis method for a heavy-ion single-particle multi-bit upset effect of a device. The method comprises: selecting a type of heavy ions, setting an appropriate fluence rate according to a corresponding principle to perform radiation on a cover opening device, recording logic addresses and data of storage units, which perform single-particle upset, of the device by a test system, and stopping radiation when reaching an estimated single-particle upset number or the maximum ion fluence; establishing a mapping relationship from the logic addresses of the device to physical addresses, and according to a physical bit map, carrying out statistics on a number of single-particle upsets, a number of single-particle unit upset events and a number of multi-bit upset events; and by combining ion fluence, calculating parameters such as probabilities of the single-particle unit upset events and the multi-bit upset events, a multi-bit upset mean, a multi-bit upset cross section and the like. According to the quantitative analysis method for the heavy-ion single-particle multi-bit upset effect of the device, technical support and information can be provided for an anti-single-particle-upset reinforcement design of the device, and effectiveness of a reinforcement technology is verified and evaluated.

Description

A kind of quantitative analysis method of heavy ion single event multiple bit upset effect of device

Technical field

The present invention relates to a kind of quantitative analysis method of heavy ion single event multiple bit upset effect of device, belong to space single particle effect ground simulation test technology and reinforcement technique research field.

Background technology

Along with satellite electron system improving constantly large scale integrated circuit performance requirement, employing sub-micro, nanometer-grade IC have become inevitable development trend.The matter of utmost importance that the reduction of device feature process brings is the reduction of critical charge, critical charge is the lowest charge amount needed for device generation single-particle inversion, about become inverse square relation with process, as 90nm process devices, the critical charge of device is less than 2fC in the worst cases.After this means that high energy particle enters device, the ionizing energy deposition that trigger device state turnover needs reduces, and namely the susceptibility of single-particle inversion increases.In addition, the collection process of reduction to electric charge of characteristic dimension also creates profound influence, and the twin-stage enlarge-effect that the electric charge between the responsive nodes of multiple single-particle inversions that the incidence of single heavy ion causes is shared and the avalanche of trap electromotive force causes the parasitic two-stage transistor conducting of consecutive storage unit and produces makes single event multiple bit upset problem become day by day serious.The prediction of ITRS international technology roadmap for semiconductors was to 2016, and under 25nm technique, the single-particle soft error rate of integrated circuit all will come from Multiple-bit upsets.Multiple-bit upsets caused by physically consecutive storage unit upset, owing to causing the sharply increase of device single-particle soft error, the domain reinforcement means of some classics such as DICE dual interlocked storage cell can be caused in face of many nodes charge-trapping mechanism to lose due consolidation effect, and make traditional single particle effect simulation experiment method, theoretical model challenged under nanometer technology.

Single event multiple bit upset (MCU) refers to that single particle incidence causes a kind of Topology Error of physically multiple consecutive storage unit generation single-particle inversion.Further investigation device single event multiple bit upset, need diversity and the topological graph of Obtaining Accurate device single event multiple bit upset, add up the event number of different size single event multiple bit upset and carry out quantitatively characterizing, this is for measurement device single event multiple bit upset susceptibility, instruct device anti-single particle Design of Reinforcement, the validity tool of checking Design of Reinforcement is of great significance.It is current that single event multiple bit upset research ubiquity Multiple-bit upsets is difficult to differentiate statistics, topological graph is difficult to acquisition, influence degree is difficult to quantitative problem.Domestic carry out device single event multiple bit upset research be also in the starting stage, do not carry out the research work of single event multiple bit upset test method in a deep going way, application number 201010624396.9 is called a kind of patent of experimental technique of pulsed laser single event upset cross section, give a kind of method utilizing pulse laser to obtain SEU cross section, application number 200710177960.5 is called the patent of the method obtaining single particle phenomenon cross section and heavy-ion linear energy transfer relationship, give a kind of acquisition SEU cross section, locking cross section, grid are worn cross section and are burnt the method for cross section and heavy ion LET value relation, the description of the acquisition of single event multiple bit upset test figure and disposal route is not all related in two patents.The single event multiple bit upset research work reported in the world focuses mostly at the analysisanddiscusion to test findings, seldom relates to the description of single event multiple bit upset test method.When usually carrying out the test of device single particle effect, it is the single-particle inversion test figure of logic-based address that test macro measures what obtain, therefore whether truly adjacently physically the storage unit that single-particle inversion occurs can not be objectively responded, whether real single event multiple bit upset can be judged to be.Even if obtain the physics bitmap of device on the other hand, establish the mapping of single-particle inversion logical address to physical address, but in effect test, do not control the selection of implantation dose rate, select the fluence rate scope 10 specified in conventional single particle effect test method ²-10 ⁵/ cm ².s the arbitrary fluence rate between, easily introduces and is incident on by different particle " puppet " Multiple-bit upsets caused contiguous physical position, cause single event multiple bit upset statistical error excessive.The sign of single event multiple bit upset is lacked simultaneously and be familiar with clearly, cause the definition of Multiple-bit upsets and calculate reflecting the susceptibility of device to single event multiple bit upset accurately and effectively.Therefore set up a kind of complete single event multiple bit upset test figure to obtain and disposal route becomes the key issue of carrying out the research of device single-particle inversion modelling technique, evaluating device anti-single particle overturn ability, improving the solution of device anti-single particle overturn reinforcement performance urgent need.

Summary of the invention

The object of this invention is to provide a kind of quantitative analysis method measured device being carried out to single event multiple bit upset examination effect under the condition of ground experiment room, make the research work of ground single particle effect Multiple-bit upsets from now on convenient, practical.

The present invention is achieved through the following technical solutions:

A quantitative analysis method for the heavy ion single event multiple bit upset effect of device, its special character is, comprises the following steps:

1] data acquisition

1.1] beam parameters setting

Select ion species, select suitable fluence rate to carry out irradiation according to heavy ion LET value;

1.2] test

The storage unit logical address of registering device generation single-particle inversion and data, stop irradiation when reaching single-particle inversion number or the maximum ion fluence of expectation;

2] data processing

2.1] set up the mapping relations of device logical address to physical address, form physics bitmap;

2.2] according to physics bitmap, add up single-particle inversion number and the single event number in each retaking of a year or grade cycle and whole retaking of a year or grade cycle, single event number comprises unit rollover event number and Multiple-bit upsets event number, and the Multiple-bit upsets topological graph of record corresponding to often kind of Multiple-bit upsets event;

2.3] based on step 2.2] data statistics, in conjunction with heavy ion fluence, single event multiple bit upset is characterized, realizes the quantitative test to device single event multiple bit upset effect.

As needs, in step 1.2] and step 2.1] between also comprise:

1.3] 1.2 are carried out again after adjusting heavy ion incident angle, device pattern filling or operating voltage] test

Step.

As needs, in step 1.3] and step 2.1] between also comprise:

1.4] select new ion species, change heavy ion LET value, after carrying out irradiation according to the suitable fluence rate of heavy ion LET value selection, carry out 1.2 again] step of testing.

As needs, in step 1.4] and step 2.1] between also comprise:

1.5] 1.2 are carried out again after adjusting heavy ion incident angle, device pattern filling or operating voltage] step of testing.

In step 1.1] beam parameters setting time, to the device of single particle effect sensitivity, during irradiation, implantation dose rate should be as far as possible low, thus control to very low by the probability of happening of " puppet " MCU (MCU that two or more ion incidence causes in adjacent position).But the problems such as single-particle inversion number was accumulated slowly, exposure time is long, accelerator Beam breakup unstability, the increase of fluence statistical error that too low fluence rate will cause, therefore actual effect test intermediate ion fluence rate selectes principle is that the number that single-particle inversion occurred in the retaking of a year or grade cycle of guarantee is tried one's best few compared to device memory capacity, is specially:

Integrated level is less than to the memory device of 1Mbit, ensures that the upset number of each retaking of a year or grade period measuring in irradiation is less than 0.01% of chip total volume; Integrated level is greater than to the memory device of 1Mbit, ensure that the upset number of each retaking of a year or grade period measuring in irradiation is not more than 100, the most bad probability that " puppet " Multiple-bit upsets occurs once is like this less than 1 × 10 ^-3.

Accumulative E in the retaking of a year or grade cycle _sGLthe probability λ that " puppet " Multiple-bit upsets occurs once during individual upset can be expressed as:

$\mathrm{\λ}=\frac{E_{\mathrm{SGL}}\×\mathrm{AdjCell}}{N}---(1-1)$

Wherein, E _sGLit is the single-particle inversion number of a retaking of a year or grade periodic recording in irradiation process, N represents memory device integrated level and memory capacity, AdjCell represents the Number of Storage Units that may be referred to as MCU around 1 storage unit upset, there is upset and be just denoted as Multiple-bit upsets in usually physically completely adjacent storage unit, when therefore calculating, AdjCell gets 8.

Consider from data statistics degree of confidence, step 1.2] described in the single-particle inversion number of expectation should be accumulated to more than 100 but overturn number and should not exceed 1% of device memory capacity, maximum ion fluence is no more than 1E7cm ^-2.

Above-mentioned steps 2.1] device logical address to the foundation of the mapping relations of physical address based on the design device information that provides of manufacturer or the method taking reverse design or the method adopting heavy ion microbeam, laser microbeam fixation and recognition.

Above-mentioned steps 2.2] in the statistical method of single event number be " all single-particle inversions that ion causes all regard an event as, and no matter be that unit overturns or Multiple-bit upsets, event is only denoted as once ".

Above-mentioned steps 2.3] in sign is carried out to single event multiple bit upset and quantitatively, characterization parameter comprises U-shaped i.e. SEU cross section, E type and single event cross section, single event multiple bit upset event cross section, single-particle unit rollover event cross section, Multiple-bit upsets average Mean, Multiple-bit upsets probability, has the probability of the single event of i bit flipping, and embodiments method is as follows:

U-shaped i.e. SEU cross section σ _u-SEU, be expressed as:

${\mathrm{\σ}}_{U-\mathrm{SEU}}=\underset{i=1}{\overset{\∞}{\mathrm{\Σ}}}\frac{i\×{\mathrm{Event}}_{i-\mathrm{bit}}}{\mathrm{\Φ}}=\frac{1\×{\mathrm{Event}}_{1-\mathrm{bit}}+2\×{\mathrm{Event}}_{2-\mathrm{bit}}+3\×{\mathrm{Event}}_{3-\mathrm{bit}}+...}{\mathrm{\Φ}}---(1-2)$

E type and single event cross section σ _e-SEU, be expressed as:

${\mathrm{\σ}}_{E-\mathrm{SEU}}=\underset{i=2}{\overset{\∞}{\mathrm{\Σ}}}\frac{{\mathrm{Event}}_{i-\mathrm{bit}}}{\mathrm{\Φ}}=\frac{{\mathrm{Event}}_{1-\mathrm{bit}}+{\mathrm{Event}}_{2-\mathrm{bit}}+{\mathrm{Event}}_{3-\mathrm{bit}}+{\mathrm{Event}}_{4-\mathrm{bit}}+...}{\mathrm{\Φ}}---(1-3)$

Wherein Event i-bit is the single event number with i bit flipping, and Φ is total fluence of incident ion;

Single event multiple bit upset event cross section σ _mCU, be expressed as:

${\mathrm{\σ}}_{\mathrm{MCU}}=\underset{i=2}{\overset{\∞}{\mathrm{\Σ}}}\frac{{\mathrm{Event}}_{i-\mathrm{bit}}}{\mathrm{\Φ}}=\frac{{\mathrm{Event}}_{2-\mathrm{bit}}+{\mathrm{Event}}_{3-\mathrm{bit}}+{\mathrm{Event}}_{4-\mathrm{bit}}+...}{\mathrm{\Φ}}---(1-4)$

Single-particle unit rollover event cross section

${\mathrm{\σ}}_{\mathrm{SBU}}=\frac{{\mathrm{Event}}_{1-\mathrm{bit}}}{\mathrm{\Φ}}---(1-5)$

Multiple-bit upsets average Mean:

$\mathrm{Mean}=\frac{{\mathrm{\σ}}_{U-\mathrm{SEU}}}{{\mathrm{\σ}}_{E-\mathrm{SEU}}}=\frac{\underset{i=2}{\overset{\∞}{\mathrm{\Σ}}}i\×{\mathrm{Event}}_{i-\mathrm{bit}}}{\underset{i=1}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Event}}_{i-\mathrm{bit}}}---(1-6)$

Multiple-bit upsets probability, is expressed as:

$\mathrm{Pr\; obality\; of\; MCU}=\frac{\underset{i=2}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Event}}_{i-\mathrm{bit}}}{\underset{i=1}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Event}}_{i-\mathrm{bit}}}---(1-7)$

In formula, denominator is the summation of all single events, and molecule is the summation with 2 bit flippings and the more Multiple-bit upsets event of Multiple-bit upsets;

There is the single event Event of i bit flipping _i-bitprobability be then expressed as

$\mathrm{Pr\; obality\; of}{\mathrm{Event}}_{i-\mathrm{bit}}=\frac{{\mathrm{Event}}_{i-\mathrm{bit}}}{\underset{i=1}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Event}}_{i-\mathrm{bit}}}---(1-8).$

Step 2.3] after, also comprise the relation curve between one or more in one or more and the heavy ion LET value of drawing in single-particle characterization parameter, ion incident angles, pattern filling, operating voltage.

Compared with prior art, advantage is in the present invention:

1, " whether " puppet " mostly is the occurrence probability of upset; truly adjacent physically can objectively respond the storage unit that single-particle inversion occurs to the mapping relations of physical address by setting up device logical address; thus can determine whether real single event multiple bit upset to eliminate " puppet " Multiple-bit upsets, realizes detecting the evaluation of measured device anti-single particle overturn ability by reducing the control of fluence rate in the quantitative analysis method of heavy ion single event multiple bit upset effect of the present invention.

2, the present invention can provide foundation for setting up scientific and reasonable small size device heavy ion single particle effect simulation experiment method.

3, the present invention can provide technological means and information for device anti-single particle overturn Design of Reinforcement, and the validity of reinforcement technique is evaluated in checking.

4, the present invention is equally applicable to test figure acquisition and the process of proton and neutron single-particle Multiple-bit upsets.

Accompanying drawing explanation

Fig. 1 is the quantitative analysis method of the heavy ion single event multiple bit upset effect of device of the present invention;

Fig. 2 is the decoding figure of device in the embodiment of the present invention;

A certain retaking of a year or grade cycle single-particle inversion Data Physical bitmap display when Fig. 3 is Cl ion irradiation;

Fig. 4 is the single-particle inversion Data Physical bitmap display of Cl ion whole retaking of a year or grade cycle;

The relation curve of the upset of Tu5Shi single-particle unit and Multiple-bit upsets probability of occurrence, Multiple-bit upsets average and LET value.

There is in whole retaking of a year or grade cycle when Fig. 6 illustrates Cl ion irradiation the event number of the single event multiple bit upset of different topology figure.

Concrete enforcement

Below for certain static memory H328X circuit, by reference to the accompanying drawings the specific embodiment of the present invention is elaborated, H328X is a synchronous single-port SRAM circuit, memory capacity 32K × 8 are total to 256Kbit, following example only for illustration of the present invention, but is not used for limiting the scope of the invention.

Fig. 1 is the process flow diagram of the quantitative analysis method of the heavy ion single event multiple bit upset effect of the device of the embodiment of the present invention, and composition graphs 1, is described in detail this method.

(1) before test, sample is uncapped process, carry out functional parameter test, after test passes, sample is inserted on PCB irradiation plate, be fixed on testing position by sample holder and carry out collimation and locate.Connecting test system, feed circuit and PCB irradiation plate, add electrical testing to test specimen, guarantees that sample and test macro normally run.

(2) choose Br ion and start heavy ion irradiation test, the retaking of a year or grade of test macro high speed, the time that system completes a cycle detection is about 4ms, records logical address and data that each retaking of a year or grade cycle, the storage unit of single-particle inversion occurred.The principle that effect test intermediate ion fluence rate is selected ensures that the upset number of each retaking of a year or grade period measuring in irradiation is less than 0.01% of chip total volume and is namely no more than 25, and the most bad probability that " puppet " Multiple-bit upsets occurs like this is less than 1 × 2) ^-3.Because this device is responsive to single particle effect, stop irradiation when exposure time reaches 1 minute, the total fluence of record ion.Then change ionic species, choose the heavy ion of Cl ion, F ion, I ion acquisition Different L ET value successively, repeat above-mentioned steps.

(3) mapping relations of logical address to physical address are set up.H328X SRAM circuit storer physical location arranges according to certain sequence of addresses, sees Fig. 2.Storer totally eight IP unit is controlled by address wire A [14-12], an IP unit has upper and lower two pieces (A [7]), column address is A [3-0], A3 is 0 selection U, and select UX when being 1, row address is A [11-8], A [6-4], wherein A [11-8] selects 1, A [6-4] to be partial circulating in 16 row groups, carries out 8 and select 1 in a row group.Have employed bit interleave technology in laying out pattern, the identical bits cloth of every 8 words is put together.

For H328X, provide arbitrary 15 logical addresses can find the word physical location of 8 sram cells in correspondence group according to address of devices information.Example: the binary representation of logical address 7F58 as:

A ₁₄A ₁₃A ₁₂A ₁₁A ₁₀A ₉A ₈A ₇A ₆A ₅A ₄A ₃A ₂A ₁A ₀

1 1 1 1 1 1 1 0 1 0 1 8 0 0 0

According to the following step, the physical location of 8 bit locations that this logical address can be found corresponding.

A () is by A ₁₄a ₁₃a ₁₂=(111) ₂=7 know that 8 storage unit are positioned at D7 IP unit.

B () is by A ₇=(0) ₂=0 knows that 8 storage unit are positioned at the latter half of D7 IP unit, namely in WL<0>-WL<127Grea tT.GreaT.GT interval.

C () is by A ₁₁a ₁₀a ₉a ₈=(1111) ₂=15 know that 8 storage unit are positioned at 15 row groups, namely in WL<120>-WL<127Gr eatT.GreaT.GT interval.

D () is by A ₆a ₅a ₄=(101) ₂=5 know that 8 storage unit are positioned at 5 row of 15 row groups, i.e. 125 row.

E () is by A ₃=(0) ₂=0 knows that 8 memory cell data being positioned at U row group are chosen

F () is by A ₂a ₁a ₀=(000) ₀=0 belongs to W ₀word, namely 8 identical bi of U row group meta (i=0,1 ... 7) adjacent 8 sram cells point to 0 row.

As the data bit b of logical address 7F58 ₁single-particle inversion occurs, then physical address points to 0 row of U1 row group.

The bitmap mapping software of braiding logic address maps physical address, as shown in Figure 3, interface right half part can select any retaking of a year or grade time at interface, provides logical address and physical address and corresponding flip bit that the storage unit overturn occurs; Left-half is the general picture figure of chip array, is used for mapping the physical location that the storage unit overturn occurs.Software can not only provide each retaking of a year or grade cycle single-particle inversion physics bitmap, carry out accurate judgement and the statistics of Multiple-bit upsets, also can provide and be accumulated to the total single-particle inversion image of device under certain fluence, thus the homogeneity of checking line hot spot and the accuracy of bitmap mapping, see Fig. 4.

(4) based on bitmap software, add up single-particle inversion number and the single event number in each retaking of a year or grade cycle, single event number comprises unit rollover event number and Multiple-bit upsets event number, records the topological graph of the Multiple-bit upsets corresponding to often kind of Multiple-bit upsets event simultaneously.Then add up respectively to often kind of single event number in whole retaking of a year or grade cycle, statistics has single event number and the Eventi-bit of i bit flipping.Only enumerate when giving Cl ion irradiation 1 minute in table 1, each retaking of a year or grade time and total single-particle inversion number, single event number, and the single event number of different upset figure place.The event number of the single event multiple bit upset with different topology figure is given in table 2.

Single-particle inversion number, single event multiple bit upset event number statistical form in whole retaking of a year or grade cycle during table 1 Cl ion irradiation

(5) based on data statistics, in conjunction with the heavy ion fluence that accelerator side provides, according to the definition of the Multiple-bit upsets different parameters given by (1-2)-(1-8), calculate the parameter such as probability, Multiple-bit upsets average, Multiple-bit upsets cross section of different upset figure place single event, result of calculation is in table 2, draw the relation curve of the upset of single-particle unit and Multiple-bit upsets probability of occurrence, Multiple-bit upsets average and LET value, see Fig. 5.

The result of calculation in unit upset and Multiple-bit upsets probability, average, cross section during table 2 different heavy ion LET

Claims (10)

1. a quantitative analysis method for the heavy ion single event multiple bit upset effect of device, is characterized in that, comprise the following steps:

1] data acquisition

1.1] beam parameters setting

Select ion species, select suitable fluence rate to carry out irradiation according to heavy ion LET value;

1.2] test

The storage unit logical address of registering device generation single-particle inversion and data, stop irradiation when reaching single-particle inversion number or the maximum ion fluence of expectation;

2] data processing

2.1] set up the mapping relations of device logical address to physical address, form physics bitmap;

2.2] according to physics bitmap, add up single-particle inversion number and the single event number in each retaking of a year or grade cycle and whole retaking of a year or grade cycle, single event number comprises unit rollover event number and Multiple-bit upsets event number, and the Multiple-bit upsets topological graph of record corresponding to often kind of Multiple-bit upsets event;

2.3] based on step 2.2] data statistics, in conjunction with heavy ion fluence, single event multiple bit upset is characterized, realizes the quantitative test to device single event multiple bit upset effect.

2. the quantitative analysis method of the heavy ion single event multiple bit upset effect of device according to claim 1, is characterized in that:

In step 1.2] and step 2.1] between also comprise:

1.3] 1.2 are carried out again after adjusting heavy ion incident angle, device pattern filling or operating voltage] step of testing.

3. the quantitative analysis method of the heavy ion single event multiple bit upset effect of device according to claim 2, is characterized in that:

In step 1.3] and step 2.1] between also comprise:

1.4] select new ion species, change heavy ion LET value, after carrying out irradiation according to the suitable fluence rate of heavy ion LET value selection, carry out 1.2 again] step of testing.

4. the quantitative analysis method of the heavy ion single event multiple bit upset effect of device according to claim 3, is characterized in that:

In step 1.4] and step 2.1] between also comprise:

1.5] 1.2 are carried out again after adjusting heavy ion incident angle, device pattern filling or operating voltage] step of testing.

5. the quantitative analysis method of the heavy ion single event multiple bit upset effect of the device according to claims 1 or 2 or 3 or 4, is characterized in that:

Described step 1.1] beam parameters setting time, the selection principle of fluence rate is specially:

Integrated level is less than to the memory device of 1Mbit, ensures that the upset number of each retaking of a year or grade period measuring in irradiation is less than 0.01% of chip total volume; Integrated level is greater than to the memory device of 1Mbit, ensures that the upset number of each retaking of a year or grade period measuring is not more than 100 in irradiation, thus the probability that " puppet " Multiple-bit upsets occurs once is controlled to be less than 1 × 10 ^-3.

6. the quantitative analysis method of the heavy ion single event multiple bit upset effect of the device according to claims 5, is characterized in that:

Step 1.2] described in the single-particle inversion number of expectation should be accumulated to more than 100 but overturn number and should not exceed 1% of device memory capacity, maximum ion fluence is no more than 1E7cm ^-2.

7. the quantitative analysis method of the heavy ion single event multiple bit upset effect of the device according to claims 5, is characterized in that:

Step 2.1] device logical address to the foundation of the mapping relations of physical address based on the design device information that provides of manufacturer or the method taking reverse design or the method adopting heavy ion microbeam, laser microbeam fixation and recognition.

8. the quantitative analysis method of the heavy ion single event multiple bit upset effect of the device according to claims 7, is characterized in that:

Step 2.2] in the statistical method of single event number be " all single-particle inversions that ion causes all regard an event as, and no matter be that unit overturns or Multiple-bit upsets, event is only denoted as once ".

9. the quantitative analysis method of the heavy ion single event multiple bit upset effect of the device according to claims 8, is characterized in that:

Step 2.3] in sign is carried out to single event multiple bit upset and quantitatively, characterization parameter comprises U-shaped i.e. SEU cross section, E type and single event cross section, single event multiple bit upset event cross section, single-particle unit rollover event cross section, Multiple-bit upsets average Mean, Multiple-bit upsets probability, has the probability of the single event of i bit flipping, and embodiments method is as follows:

U-shaped i.e. SEU cross section σ _u-SEU, be expressed as:

${\mathrm{\&sigma;}}_{U-\mathrm{SEU}}=\underset{i=1}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\frac{i\&times;{\mathrm{Event}}_{i-\mathrm{bit}}}{\mathrm{\&Phi;}}=\frac{1\&times;{\mathrm{Event}}_{1-\mathrm{bit}}+2\&times;{\mathrm{Event}}_{2-\mathrm{bit}}+3\&times;{\mathrm{Event}}_{3-\mathrm{bit}}+...}{\mathrm{\&Phi;}}---(1-2)$

E type and single event cross section σ _e-SEU, be expressed as:

${\mathrm{\&sigma;}}_{E-\mathrm{SEU}}=\underset{i=1}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\frac{{\mathrm{Event}}_{i-\mathrm{bit}}}{\mathrm{\&Phi;}}=\frac{{\mathrm{Event}}_{1-\mathrm{bit}}+{\mathrm{Event}}_{2-\mathrm{bit}}+{\mathrm{Event}}_{3-\mathrm{bit}}+{\mathrm{Event}}_{4-\mathrm{bit}}+...}{\mathrm{\&Phi;}}---(1-3)$

Wherein Event i-bit is the single event number with i bit flipping, and Φ is total fluence of incident ion;

Single event multiple bit upset event cross section σ _mCU, be expressed as:

${\mathrm{\&sigma;}}_{\mathrm{MCU}}=\underset{i=2}{\overset{\&infin;}{\mathrm{\&Sigma;}}}\frac{{\mathrm{Event}}_{i-\mathrm{bit}}}{\mathrm{\&Phi;}}=\frac{{\mathrm{Event}}_{2-\mathrm{bit}}+{\mathrm{Event}}_{3-\mathrm{bit}}+{\mathrm{Event}}_{4-\mathrm{bit}}+...}{\mathrm{\&Phi;}}---(1-4)$

Single-particle unit rollover event cross section

${\mathrm{\&sigma;}}_{\mathrm{SBU}}=\frac{{\mathrm{Event}}_{1-\mathrm{bit}}}{\mathrm{\&Phi;}}---(1-5)$

Multiple-bit upsets average Mean:

$\mathrm{Mean}=\frac{{\mathrm{\&sigma;}}_{U-\mathrm{SEU}}}{{\mathrm{\&sigma;}}_{E-\mathrm{SEU}}}=\frac{\underset{i=1}{\overset{\&infin;}{\mathrm{\&Sigma;}}}i\&times;{\mathrm{Event}}_{i-\mathrm{bit}}}{\underset{i=1}{\overset{\&infin;}{\mathrm{\&Sigma;}}}{\mathrm{Event}}_{i-\mathrm{bit}}}---(1-6)$

Multiple-bit upsets probability, is expressed as:

$\mathrm{Pr\; obality\; of\; MCU}=\frac{\underset{i=2}{\overset{\&infin;}{\mathrm{\&Sigma;}}}{\mathrm{Event}}_{i-\mathrm{bit}}}{\underset{i=1}{\overset{\&infin;}{\mathrm{\&Sigma;}}}{\mathrm{Event}}_{i-\mathrm{bit}}}---(1-7)$

In formula, denominator is the summation of all single events, and molecule is the summation with 2 bit flippings and the more Multiple-bit upsets event of Multiple-bit upsets;

There is the single event Event of i bit flipping _i-bitprobability be then expressed as

$\mathrm{Pr\; obality\; of}{\mathrm{Event}}_{i-\mathrm{bit}}=\frac{{\mathrm{Event}}_{i-\mathrm{bit}}}{\underset{i=1}{\overset{\&infin;}{\mathrm{\&Sigma;}}}{\mathrm{Event}}_{i-\mathrm{bit}}}---(1-8).$

10. the quantitative analysis method of the heavy ion single event multiple bit upset effect of the device according to claims 9, is characterized in that:

Step 2.3] after, also comprise the relation curve between one or more in one or more and the heavy ion LET value of drawing in single-particle characterization parameter, ion incident angles, pattern filling, operating voltage.