CN113611349A - SRAM (static random Access memory) type FPGA (field programmable Gate array) single event effect test method for 16nm FinFET (field effect transistor) process - Google Patents
SRAM (static random Access memory) type FPGA (field programmable Gate array) single event effect test method for 16nm FinFET (field effect transistor) process Download PDFInfo
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- CN113611349A CN113611349A CN202110925747.8A CN202110925747A CN113611349A CN 113611349 A CN113611349 A CN 113611349A CN 202110925747 A CN202110925747 A CN 202110925747A CN 113611349 A CN113611349 A CN 113611349A
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
The invention discloses a method for testing a single event effect of an SRAM (static random Access memory) type FPGA (field programmable Gate array) by a 16nm FinFET (field effect transistor) process, relates to the technical field of single event effect tests of chips, and solves the technical problem of testing the single event effect in a high-end process, and the method comprises the following steps of: s1, writing a circuit configuration file of a specified module in an SRAM type FPGA by using a Verilog HDL hardware description language; s2, setting a current threshold value and configuring the current threshold value to a power supply control module of a development board of the SRAM type FPGA; s3, irradiating the SRAM type FPGA by an irradiation source with initial irradiation; s4, using Maxim digital Power current detection software to read the current value of the SRAM type FPGA in real time, if the current value exceeds a current threshold, carrying out failure mechanism analysis, and ending the test; s5, reading an rbd configuration information file of the SRAM type FPGA by using Beyond company software, and comparing the configuration information of the rbd configuration information file read before and after irradiation if the rbd configuration information file is read normally; otherwise, recording the occurrence of single event functional interruption of the appointed module; s6, increasing the irradiation amount of the irradiation source and executing the step S4.
Description
Technical Field
The invention relates to the technical field of chip single event effect tests, in particular to a method for testing a single event effect of an SRAM (static random access memory) type FPGA (field programmable gate array) by a 16nm FinFET (field effect transistor) process.
Background
With the iterative upgrade of semiconductor process nodes, advanced SRAM type FPGA chips are favored by space missions due to their characteristics of high performance, low cost, etc. No matter whether the 'resolute number' of foreign NASA carries out a new Mars exploration work, the 'Tianwen number one' successfully enters a Mars parking track for more than 200 days, or the 'ChangE five' completes the 'flying to the moon' task in China recently, the SRAM type FPGA is used as the figure of a spacecraft core unit. However, high-energy particles such as protons, electrons, alpha particles, heavy ions, gamma rays and the like in the space environment can penetrate through a sensitive area of a semiconductor material, and various radiation effects can cause temporary failure, performance degradation and even permanent scrapping of the SRAM type FPGA for spaceflight, so that the spacecraft can not work normally.
At present, single particle effect test research of SRSM type FPGA mainly focuses on radiation failure mechanism research of middle and low end processes (processes above 28 nm) and lacks of a single particle effect test method of high end processes (processes below 16nm), so that the radiation effect mechanism research of the SRAM type FPGA with advanced process nodes (16nm) has important research significance and application value.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art, and aims to provide a SRAM type FPGA single event effect test method suitable for a 16nm FinFET process.
The technical scheme of the invention is as follows: a single event effect test method for SRAM type FPGA of 16nm FinFET process comprises the following steps:
s1, writing a circuit configuration file of a designated module in an SRAM type FPGA by using a Verilog HDL hardware description language, and burning the circuit configuration file into the SRAM type FPGA;
s2, setting a current threshold value and configuring the current threshold value to a power supply control module of a development board of the SRAM type FPGA;
s3, irradiating the SRAM type FPGA by an irradiation source with initial irradiation;
s4, in the single irradiation process, using Maxim Digital Power current detection software to read the current value of the SRAM type FPGA in real time, if the current value exceeds the current threshold value, automatically powering off the Power supply control module, closing the irradiation source, recording the single event latch phenomenon of the SRAM type FPGA under the current irradiation energy, carrying out failure mechanism analysis, and ending the test; otherwise, go to step S5;
s5, reading the rbd configuration information file of the SRAM type FPGA by using Beyond company software, and if the read rbd configuration information file is normal, comparing the configuration information of the rbd configuration information file read before and after irradiation to obtain the single-particle upset section of the specified module with abnormal data storage; otherwise, recording the occurrence of single event functional interruption of the specified module;
s6, continuing to increase the irradiation quantity of the irradiation source and irradiate the SRAM type FPGA, and executing the step S4.
As a further improvement, the designated modules comprise a BRAM module, a CLB module and a CM module.
Furthermore, the BRAM module is configured as a storage module with 100% utilization rate and respectively storing all 1 data and all 0 data, and the FF module in the CLB module is configured as a multi-chain shift register chain circuit with high utilization rate and 0101 data.
Further, data processing before and after irradiation is carried out on the rbd configuration information file, single-particle upset sections of the BRAM module, the FF module and the CM module are counted, and mechanism analysis is carried out on the single-particle upset and multi-bit upset failure phenomena under different irradiation quantities.
Further, the irradiation source is any one of a pulse laser irradiation source, a proton irradiation source, an electron irradiation source, an alpha particle irradiation source, a heavy ion irradiation source and a gamma ray irradiation source.
Advantageous effects
Compared with the prior art, the invention has the advantages that:
the single event effect test is carried out on a 16nm FinFET technology SRAM type FPGA by adopting pulse laser, a circuit configuration file of a designated module in the SRAM type FPGA is compiled by using a Verilog HDL hardware description language, a current value of the SRAM type FPGA is read in real time by using Maxim Digital Power current detection software, an rbd configuration information file of the SRAM type FPGA is read by using Beyond company software, and data processing before and after irradiation is carried out, so that the high sensitivity of a chip to the pulse laser single event effect is effectively verified, the single bit is mainly used for turning under low laser energy (0.8nJ), and the multi-bit turning is mainly used for turning laser energy; the 16nm FPGA generates single particle latch at the pulse laser energy of 1.6nJ, and the method can provide support for the anti-radiation design of the SRAM type FPGA of the advanced process node.
Drawings
FIG. 1 is a block diagram of a testing system of the present invention;
FIG. 2 is a flow chart of an experiment according to the present invention;
FIG. 3 is a comparison of failure data for irradiation read rbd configuration information files in accordance with the present invention.
Detailed Description
The invention will be further described with reference to specific embodiments shown in the drawings.
Referring to fig. 1, as can be seen from the analysis of the structure of the SRAM type FPGA, the single event effect failure phenomenon of the SRAM type FPGA can be identified from three aspects: the single event upset is identified by the read-back of a storage module in the FPGA, the single event latch is identified by the read of the FPGA chip current, and the single event functional interruption is identified by the information communication between the FPGA and an upper computer. In order to realize the functions, the designed SRAM type FPGA single event effect test system consists of three parts: vivado software of a computer end Xilinx, chip current detection software and an SRAM type FPGA development board of a tested device Xilinx. The computer upper computer is provided with Vivado software for compiling a hardware language and carrying out burning configuration and readback on the FPGA; detecting the 16nm FPGA chip current by adopting Maxim Digital Power software of Maxim; the tested SRAM type FPGA is a KCU116 development board, a JTAG interface is used between the tested SRAM type FPGA and Vivado, the tested SRAM type FPGA is connected with current detection software through a USB adapt connector, and the SRAM type FPGA supplies power through a 12V power supply.
Referring to fig. 2-3, a method for testing the single event effect of the SRAM type FPGA of the 16nm FinFET process includes the following steps:
s1, writing a circuit configuration file of a designated module in an SRAM type FPGA by using a Verilog HDL hardware description language, and burning the circuit configuration file into the SRAM type FPGA;
s2, setting a current threshold value and configuring the current threshold value to a power supply control module of a development board of the SRAM type FPGA;
s3, irradiating the SRAM type FPGA by an irradiation source with initial irradiation;
s4, in the single irradiation process, using Maxim Digital Power current detection software to read the current value of the SRAM type FPGA in real time, if the current value exceeds a current threshold value, automatically cutting off the Power supply control module, closing an irradiation source, recording the single event latch phenomenon of the SRAM type FPGA under the current irradiation energy, carrying out failure mechanism analysis, and ending the test; otherwise, go to step S5;
s5, reading an rbd configuration information file of the SRAM type FPGA by using Beyond company software, and if the read rbd configuration information file is normal, comparing the configuration information of the rbd configuration information file read before and after irradiation to obtain a single-particle upset section with abnormal data storage of a specified module; otherwise, recording the occurrence of single event functional interruption of the appointed module;
s6, continuing to increase the irradiation quantity of the irradiation source and irradiate the SRAM type FPGA, and executing the step S4.
The designated modules comprise a BRAM module, a CLB module and a CM module, and the BRAM module, the CLB module and the CM module are the most widely used units in an SRAM type FPGA and the most affected units by irradiation in the SRAM type FPGA, so that high-utilization-rate hardware circuit design is performed on two large storage units, namely the BRAM module and the FF module in the CLB. The BRAM module is configured as a 100% utilization storage module for respectively storing all 1 data and all 0 data, and the FF module in the CLB module is configured as a high-utilization multi-chain shift register chain circuit for storing 0101 data, wherein the high utilization is 75% utilization or above.
The rbd configuration information file contains storage information of the BRAM, the FF and the CM, data processing before and after irradiation is carried out on the rbd configuration information file, single-particle upset sections of the BRAM, the FF and the CM are counted, and mechanism analysis is carried out on unit upset and multi-bit upset failure phenomena under different irradiation quantities.
In this embodiment, the irradiation source is any one of a pulse laser irradiation source, a proton irradiation source, an electron irradiation source, an alpha particle irradiation source, a heavy ion irradiation source, and a gamma ray irradiation source, wherein the pulse laser irradiation source has the advantages of convenient operation, low cost, fast single event effect experiment background, and the like, and is more convenient for single event effect research.
Fig. 3 is a comparison of failure data of the irradiation read rbd configuration information file, where the position of the dashed line box represents the failure data, and table 1 below shows the chip port Current value when latch-up occurs in irradiation according to the present invention, where the Output Current exceeds the Current threshold when the Output Current is 1.47A.
TABLE 1
Because the feature size of the SRAM type FPGA of the advanced process node (the process below 16nm) is greatly reduced, and the charge sharing effect between adjacent transistors is intensified, the single-particle flip section of the SRAM type FPGA of the advanced process node is not enough to represent the data of the FPGA affected by irradiation, and the data needs to be represented by a unit flip section, a multi-bit flip section and a multi-node flip section. This patent adopts the form of control variable to deposit full 1 and full 0 data respectively with the memory cell and disposes, is more convenient for carry out data processing and advanced technology node SRAM type FPGA irradiation mechanism research to the upset cross-section of subdividing.
The software current monitoring scheme provided by the invention has the advantages of cost saving, high adjustability and data reading intuition by using the Maxim Digital Power software to monitor the FPGA to be tested, and is more convenient for field operation of scientific research personnel compared with a black box type current monitoring mode of a hardware debugging board.
The method adopts Beyond company software to Compare the difference of the configuration content before and after irradiation of the rbd configuration information file of the FPGA to be tested, and has the advantage of intuition of data reading.
The single event effect test is carried out on a 16nm FinFET technology SRAM type FPGA by adopting pulse laser, a circuit configuration file of a designated module in the SRAM type FPGA is compiled by using a Verilog HDL hardware description language, a current value of the SRAM type FPGA is read in real time by using Maxim Digital Power current detection software, an rbd configuration information file of the SRAM type FPGA is read by using Beyond company software, and data processing before and after irradiation is carried out, so that the high sensitivity of a chip to the pulse laser single event effect is effectively verified, the single bit is mainly used for turning under low laser energy (0.8nJ), and the multi-bit turning is mainly used for turning laser energy; the 16nm FPGA generates single particle latch at the pulse laser energy of 1.6nJ, and the method can provide support for the anti-radiation design of the SRAM type FPGA of the advanced process node.
The above is only a preferred embodiment of the present invention, and it should be noted that it is obvious to those skilled in the art that several variations and modifications can be made without departing from the structure of the present invention, which will not affect the effect of the implementation of the present invention and the utility of the patent.
Claims (5)
1. A single event effect test method for SRAM type FPGA with 16nm FinFET technology is characterized by comprising the following steps:
s1, writing a circuit configuration file of a designated module in an SRAM type FPGA by using a Verilog HDL hardware description language, and burning the circuit configuration file into the SRAM type FPGA;
s2, setting a current threshold value and configuring the current threshold value to a power supply control module of a development board of the SRAM type FPGA;
s3, irradiating the SRAM type FPGA by an irradiation source with initial irradiation;
s4, in the single irradiation process, using Maxim Digital Power current detection software to read the current value of the SRAM type FPGA in real time, if the current value exceeds the current threshold value, automatically powering off the Power supply control module, closing the irradiation source, recording the single event latch phenomenon of the SRAM type FPGA under the current irradiation energy, carrying out failure mechanism analysis, and ending the test; otherwise, go to step S5;
s5, reading the rbd configuration information file of the SRAM type FPGA by using Beyond company software, and if the read rbd configuration information file is normal, comparing the configuration information of the rbd configuration information file read before and after irradiation to obtain the single-particle upset section of the specified module with abnormal data storage; otherwise, recording the occurrence of single event functional interruption of the specified module;
s6, continuing to increase the irradiation quantity of the irradiation source and irradiate the SRAM type FPGA, and executing the step S4.
2. The method for testing the single event effect of the SRAM type FPGA of the 16nm FinFET process according to claim 1, wherein the designated module comprises a BRAM module, a CLB module and a CM module.
3. The method for testing the single event effect of the SRAM type FPGA of the 16nm FinFET process according to claim 2, wherein the BRAM module is configured as a storage module with 100% utilization rate and respectively storing all 1 data and all 0 data, and the FF module in the CLB module is configured as a multi-chain shift register chain circuit with high utilization rate and storing 0101 data.
4. The method for testing the single event effect of the SRAM type FPGA of the 16nm FinFET process according to claim 3, wherein the rbd configuration information file is subjected to data processing before and after irradiation, the single event upset cross sections of a BRAM module, an FF module and a CM module are counted, and mechanism analysis is performed on the single event upset and multi-bit upset failure phenomena under different irradiation quantities.
5. The SRAM type FPGA single event effect test method of claim 1, wherein the irradiation source is any one of a pulse laser irradiation source, a proton irradiation source, an electron irradiation source, an alpha particle irradiation source, a heavy ion irradiation source and a gamma ray irradiation source.
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| US7859292B1 (en) * | 2009-07-14 | 2010-12-28 | United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Methods and circuitry for reconfigurable SEU/SET tolerance |
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| CN114021505A (en) * | 2022-01-06 | 2022-02-08 | 青岛展诚科技有限公司 | Method and system for generating integrated circuit FinFET complex three-dimensional structure description file |
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