CN105022859B - A kind of quantitative analysis method of the heavy ion single event multiple bit upset effect of device - Google Patents
A kind of quantitative analysis method of the heavy ion single event multiple bit upset effect of device Download PDFInfo
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Abstract
The invention discloses the quantitative analysis method of the heavy ion single event multiple bit upset effect of device, methods described includes：Select ion species, device of uncapping is irradiated according to the suitable fluence rate of corresponding policy setting, the memory cell logical address and data of single-particle inversion occur for test system registering device, stop irradiation when reaching the single-particle inversion number being expected or maximum ion fluence.Device logical address is established to the mapping relations of physical address, according to physics bitmap, statistics single-particle inversion number, the upset of simple grain subunit and Multiple-bit upsets event number.Coupled ion fluence, calculate the parameters such as the upset of simple grain subunit and the Multiple-bit upsets probability of happening, Multiple-bit upsets average, Multiple-bit upsets section.The present invention can overturn Design of Reinforcement for device anti-single particle and provide technical support and information, and verify the validity of evaluation reinforcement technique.
Description
Technical Field
The invention relates to a quantitative analysis method for a heavy-ion single-particle multi-bit upset effect of a device, and belongs to the field of research on a space single-particle effect ground simulation test technology and a reinforcement technology.
Background
With the continuous improvement of the satellite electronic system on the performance requirement of large scale integrated circuits, the adoption of ultra-deep submicron and nanoscale integrated circuits has become an inevitable development trend. The reduction of the feature process size of the device brings about the first problem of the reduction of the critical charge, which is the minimum charge amount required for the single event upset of the device and is approximately in inverse square relation with the process size, such as a 90nm process device, and the critical charge of the device is already less than 2fC in the worst case. This means that after the high energy particles enter the device, the ionization energy deposition required to trigger the device state flip is reduced, i.e. the sensitivity of single event upsets is increased. In addition, the reduction of the characteristic size has a profound influence on the charge collection process, and the single-particle multi-bit upset problem becomes increasingly serious due to the charge sharing among a plurality of single-particle upset sensitive nodes caused by the incidence of single heavy ions and the double-stage amplification effect caused by the conduction of the parasitic double-stage transistor of the adjacent storage unit caused by the collapse of the well potential. The ITRS international semiconductor technology development blueprints predicted that by 2016, the single-event soft error rate of integrated circuits at 25nm technology would all result from multi-bit upsets. Due to the fact that multi-bit upset caused by physically adjacent memory cell upset causes rapid increase of single-particle soft errors of devices, some classical layout reinforcing methods such as DICE double-interlocking memory cells lose due reinforcing effects in the presence of a multi-node charge collection mechanism, and traditional single-particle effect simulation test methods and theoretical models are challenged under a nano process.
Single-event multi-bit-upset (MCU) refers to a topological error in which a single-event upset occurs in physically adjacent memory cells due to a single-event incidence. The method has the advantages that the single-particle multi-bit upset of the device needs to be accurately obtained, the diversity and the topological graph of the single-particle multi-bit upset of the device need to be accurately obtained, the number of events of the single-particle multi-bit upset with different sizes is counted, and quantitative representation is carried out, so that the method has very important significance for measuring the single-particle multi-bit upset sensitivity of the device, guiding the single-particle resistance reinforcement design of the device and verifying the effectiveness of the reinforcement design. At present, the problems that multi-bit upset is difficult to distinguish and count, topological graphs are difficult to obtain, and the influence degree is difficult to quantify commonly exist in single-particle multi-bit upset research. The research on the single-particle multi-bit upset of the device is still in the starting stage at home, the research work of a single-particle multi-bit upset test method is not deeply carried out, the application number is 201010624396.9, the patent of an experimental method for a pulse laser single-particle upset section is provided, a method for acquiring the single-particle upset section by using pulse laser is provided, the application number is 200710177960.5, the patent of a method for acquiring the relationship between the single-particle phenomenon section and the linear energy transfer of heavy ions is provided, and the patent of the method for acquiring the linear energy transfer relationship between the single-particle phenomenon section and the heavy ions is providedA method for obtaining the relation between a single-particle upset section, a blocking section, a gate-through section, a burnout section and a heavy ion LET value is provided, and the two patents do not relate to the description of a single-particle multi-bit upset test data obtaining and processing method. The international reported research work on single-particle multi-bit upset mostly focuses on the analysis and discussion of test results, and rarely relates to the description of a single-particle multi-bit upset test method. When a single event effect test of a device is usually carried out, a test system measures and acquires single event upset test data based on a logic address, so that whether memory cells subjected to single event upset are physically and really adjacent or not can not be objectively reflected, and whether true single event multi-bit upset can be judged or not. On the other hand, even if the physical bitmap of the device is obtained and the mapping from the single event upset logical address to the physical address is established, the selection of the ion fluence rate is not controlled in the effect test, and the fluence rate range 10 specified in the conventional single event effect test method is selected 2 -10 5 /cm 2 And any fluence rate between s is easy to introduce false multi-bit upset caused by different particles being incident on adjacent physical positions, so that the statistical error of the single-particle multi-bit upset is overlarge. Meanwhile, the characterization of single-particle multi-bit upset lacks clear understanding, so that the definition and calculation of the multi-bit upset cannot accurately and effectively reflect the sensitivity of the device to the single-particle multi-bit upset. Therefore, establishing a complete single-particle multi-bit upset test data acquisition and processing method becomes a key problem which is urgently needed to be solved for carrying out the research on the single-particle upset simulation test technology of the device, evaluating the single-particle upset resistance of the device and improving the single-particle upset resistance reinforcement performance of the device.
Disclosure of Invention
The invention aims to provide a quantitative analysis method for single-particle multi-bit upset test effect of a tested device under the condition of a ground laboratory, so that the research work of ground single-particle multi-bit upset is more convenient and practical in future.
The invention is realized by the following technical scheme:
a quantitative analysis method for the multiple bit upset effect of heavy ion single particles of a device is characterized by comprising the following steps:
data acquisition
1.1 ] Beam parameter setting
Selecting heavy ion species, and selecting a proper fluence rate for irradiation according to the LET value of the heavy ions;
1.2 ] testing
Recording the logical address and data of a storage unit of the device subjected to single-particle upset, and stopping irradiation when the predicted single-particle upset number or the maximum ion fluence is reached;
2] data processing
2.1, establishing a mapping relation from a logical address to a physical address of the device to form a physical bitmap;
2.2, counting the number of single-particle upset and the number of single-particle events of each read-back period and all read-back periods according to the physical bitmap, wherein the number of single-particle events comprises the number of unit upset events and the number of multi-bit upset events, and recording a multi-bit upset topological graph corresponding to each multi-bit upset event;
and 2.3, representing single-particle multi-bit upset based on the data statistical information in the step 2.2 and combining the heavy ion fluence to realize quantitative analysis of the single-particle multi-bit upset effect of the device.
If necessary, the method also comprises the following steps between the step 1.2 and the step 2.1):
1.3 ] adjusting the incident angle of heavy ions, filling patterns or working voltage of devices and then carrying out 1.2 ] test
Step (2).
If necessary, the method also comprises the following steps between the step 1.3 and the step 2.1):
1.4. Selecting new heavy ion species, changing the LET value of the heavy ions, selecting proper fluence rate according to the LET value of the heavy ions, irradiating and then carrying out the step of 1.2.
If necessary, the method also comprises the following steps between the step 1.4 and the step 2.1):
and 1.5, adjusting the incident angle of heavy ions, filling patterns of a device or working voltage, and then carrying out 1.2 test.
In step 1.1 ] beam parameter setting, for devices sensitive to single event effect, the ion fluence rate during irradiation should be as low as possible, so as to control the occurrence probability of "false" MCU (MCU caused by two or more ions incident at adjacent positions) to be very low. However, too low fluence will result in too slow accumulation of single event upset number, too long irradiation time, unstable accelerator beam, increased fluence statistical error, and so on, so the ion fluence rate selection principle in the actual effect test is to ensure that the number of single event upsets occurring in a read-back period is as small as possible compared with the device storage capacity, specifically:
for a memory device with integration level less than 1Mbit, the turnover number of each read-back period test in irradiation is ensured to be less than 0.01% of the total capacity of the chip; for the memory device with integration degree larger than 1Mbit, the number of the flips tested in each read-back period in irradiation is ensured to be not more than 100, so that the worst probability of one false multi-bit flip is less than 1 multiplied by 10 -3 。
Accumulating E within one read-back period SGL The probability λ of a "false" multi-bit flip occurring at one flip can be expressed as:
wherein E is SGL The number of single-particle upset is recorded in one read-back period in the irradiation process, N represents the integration level of a storage device, namely the storage capacity, adjCell represents the number of storage units which can be recorded as MCU around 1 storage unit upset, usually, the storage units which are completely physically adjacent are overturned and are recorded as multi-bit upset, and therefore AdjCell takes 8 in calculation.
Considering from the data statistics confidence, the expected single-particle turnover number in the step 1.2 ] should be accumulated to exceed 100, but the turnover number should not exceed 1% of the storage capacity of the device, and the maximum ion fluence should not exceed 1E7cm -2 。
And 2.1) establishing the mapping relation from the logical address to the physical address of the device based on device information provided by a design manufacturer, or adopting a reverse design method or adopting a heavy ion microbeam and laser microbeam positioning and identifying method.
The method for counting the number of single particle events in the step 2.2 comprises the following steps: all single event upsets caused by one ion are regarded as one event, and the event is only recorded once no matter the single event upset or the multiple bit upset.
In the step 2.3, the single-particle multi-bit upset is characterized and quantified, the characterization parameters include a U-type single-particle upset section, an E-type single-particle event section, a single-particle multi-bit upset event section, a single-particle unit upset event section, a multi-bit upset Mean, a multi-bit upset probability and a probability of a single-particle event with i-bit upset, and the specific characterization method is as follows:
u-shaped, i.e. single-particle upset cross-section sigma U-SEU Expressed as:
type E, i.e. single event cross section σ E-SEU Expressed as:
wherein Event i-bit is the number of single Event events with i-bit upset, and phi is the total fluence of incident ions;
single event multi-bit upset event cross section sigma MCU Expressed as:
single event unit upset event cross section
Multi-bit rolling Mean:
multi-bit flip probability, expressed as:
in the formula, a denominator is the sum of all single event events, and a numerator is the sum of multi-bit upset events with 2-bit upset and more-bit upset;
single Event with i-bit upset i-bit Is expressed as
And 2.3, drawing a relation curve between one or more of the single particle characterization parameters and one or more of the heavy ion LET value, the ion incidence angle, the filling pattern and the working voltage.
Compared with the prior art, the invention has the advantages that:
1. the quantitative analysis method for the heavy-ion single-particle multi-bit upset effect reduces the probability that the 'false' is mostly upset by controlling the fluence rate, and can objectively reflect whether the memory cells in which the single-particle upset occurs are actually adjacent physically by establishing the mapping relation between the logical address and the physical address of the device, so that whether the memory cells are actually subjected to the single-particle multi-bit upset or not can be judged to eliminate the 'false' multi-bit upset, and the evaluation and detection of the single-particle upset resistance of the device to be detected are realized.
2. The invention can provide a basis for establishing a scientific and reasonable heavy-ion single-event effect simulation test method for small-size devices.
3. The method can provide technical means and information for the single event upset resistance reinforcement design of the device, and verify and evaluate the effectiveness of the reinforcement technology.
4. The invention is also suitable for acquiring and processing test data of multi-bit upset of proton and neutron single particles.
Drawings
FIG. 1 is a method for quantitative analysis of the multiple-bit flip effect of heavy-ion single particles of the device of the present invention;
FIG. 2 is a decoding diagram of a device in an embodiment of the invention;
FIG. 3 is a physical bitmap display of single-particle upset data in a certain read-back period during Cl ion irradiation;
FIG. 4 is a physical bitmap display of single-particle upset data of all read-back periods of Cl ions;
FIG. 5 is a single event upset and multi-bit upset event probability, multi-bit upset mean, versus LET value curve;
fig. 6 shows the number of events of single-particle multi-bit flips with different topological patterns in all readback periods when Cl ions are irradiated.
Detailed Description
The following description will use a static memory H328X circuit as an example to describe the embodiments of the present invention in detail with reference to the accompanying drawings, where H328X is a synchronous single-port SRAM circuit with a storage capacity of 32K × 8 bits and 256 Kbit.
Fig. 1 is a flowchart of a method for quantitatively analyzing a heavy-ion single-particle multi-bit upset effect of a device according to an embodiment of the present invention, and the method is described in detail with reference to fig. 1.
(1) The method comprises the steps of opening a cover of a sample before testing, testing functional parameters, inserting the sample on a PCB irradiation board after the test is qualified, fixing the sample at a test position through a sample support, and aligning and positioning. And connecting the test system, the power supply circuit and the PCB irradiation board, and carrying out power-on test on the test sample to ensure the normal operation of the sample and the test system.
(2) Selecting Br ions to start a heavy ion irradiation test, testing the high-speed read-back of the system, wherein the time for the system to finish one-time cycle detection is about 4ms, and recording the logic address and data of the memory cell with single-particle upset in each read-back period. The principle of ion fluence rate selection in effect test is to ensure that the turn number tested in each read-back period in irradiation is less than 0.01% of the total capacity of the chip, i.e. not more than 25, so that the worst probability of false multi-bit turn is less than 1X 2) -3 . Because the device is sensitive to the single event effect, the irradiation is stopped when the irradiation time reaches 1 minute, and the total ion fluence is recorded. And then changing the ion species, sequentially selecting Cl ions, F ions and I ions to obtain heavy ions with different LET values, and repeating the steps.
(3) And establishing a mapping relation from the logical address to the physical address. The H328X SRAM circuit memory physical locations are arranged in an address order, see FIG. 2. Eight IP units of the memory are controlled by address lines A14-12, one IP unit has two upper and lower blocks (A7), column address is A3-0, A3 is 0 to select U, when 1, it selects UX, row address is A11-8, A6-4, where A11-8 is 1 selected from 16 row groups, A6-4 is small cycle, and 1 is selected from 8 in one row group. The layout adopts a bit interleaving technology, and the same bits of every 8 words are arranged together.
For H328X, given an arbitrary 15-bit logical address, the physical location of 8 SRAM cells of a word in the corresponding group can be found from the device address information. Example (c): the binary representation of logical address 7F58 is as follows:
the physical location of the 8-bit cell corresponding to this logical address can be found according to the following steps.
(a) From A 14 A 13 A 12 ＝(111) 2 =7 knows that 8 memory cells are located in a D7IP cell.
(b) From A 7 ＝(0) 2 =0 knows that 8 memory cells are located in the lower half of the D7IP cell, i.e. WL<0>-WL<127>, within the interval.
(c) From A 11 A 10 A 9 A 8 ＝(1111) 2 =15 know 8 memory cells are in 15 row group, i.e. WL<120>-WL<127>, within the interval.
(d) From A 6 A 5 A 4 ＝(101) 2 =5 know that 8 memory cells are located in 5 rows of a 15 row group, i.e. 125 rows.
(e) From A 3 ＝(0) 2 =0 knows that the 8 memory cells in the U column group are data selected.
(f) From A 2 A 1 A 0 ＝(000) 0 =0 belonging to W 0 The word, i.e., the adjacent 8 SRAM cells of the same bi (i =0,1, \8230; 7) in the 8U column groups points to the 0 column.
Data bit b as logical address 7F58 1 If a single event upset occurs, the physical address points to column 0 of the U1 column group.
Compiling bitmap mapping software for mapping the logical address to the physical address, wherein the right half part of the interface can select any read-back time as shown in FIG. 3 to give the logical address and the physical address of the memory cell which is turned over and the corresponding turning bit; the left half is a profile of the chip array that maps the physical location of the memory cells where the flip occurs. Software can not only give a single-particle upset physical bitmap in each read-back period to accurately judge and count multi-bit upsets, but also give a total single-particle upset imaging graph of devices accumulated under a certain fluence, so that the uniformity of beam spots and the accuracy of bitmap mapping are verified, and the graph is shown in figure 4.
(4) Counting the single-event upset number and the single-event number of each readback period based on bitmap software, wherein the single-event number comprises the unit upset event number and the multi-bit upset event number, and simultaneously recording the multi-bit upset topological graph corresponding to each multi-bit upset event. And then accumulating the number of each single event in all the read-back periods respectively, and counting the number of the single event with i-bit upset, namely Eventi-bit. In table 1, the number of single event flips, the number of single event events, and the number of single event events with different number of flips per read time and total number of single event flips per 1 minute of Cl ion irradiation are given by way of example only. The number of events for a single-event multi-bit upset with different topologies is given in fig. 6.
TABLE 1 statistics table for single-particle turnover number and single-particle multi-bit turnover event number in all read-back periods during Cl ion irradiation
(5) Based on data statistical information, combining the heavy ion fluence provided by an accelerator side, calculating parameters such as the probability of single event with different upset digits, a multi-digit upset mean value, a multi-digit upset section and the like according to the definitions of different parameters of multi-digit upset given by (1-2) - (1-8), and drawing a relation curve of the single event unit upset and multi-digit upset event probability, the multi-digit upset mean value and an LET value as shown in a table 2.
TABLE 2 calculation results of probability, mean value and section of single-bit inversion and multi-bit inversion at different heavy ion LETs
Claims (10)
1. A quantitative analysis method for the multiple bit upset effect of heavy ion single particles of a device is characterized by comprising the following steps:
data acquisition
1.1 ] Beam parameter setting
Selecting heavy ion species, and selecting a proper fluence rate for irradiation according to the LET value of the heavy ions;
1.2 ] testing
Recording the logic address and data of a storage unit of the device subjected to single particle upset, and stopping irradiation when the predicted single particle upset number or the maximum ion fluence is reached;
data processing
2.1, establishing a mapping relation from a logical address to a physical address of the device to form a physical bitmap;
2.2, counting the number of single-particle upset revolutions and the number of single-particle events of each readback period and all readback periods according to the physical bitmap, wherein the number of single-particle events comprises the number of unit upset events and the number of multi-bit upset events, and recording a multi-bit upset topological graph corresponding to each multi-bit upset event;
and 2.3, representing single-particle multi-bit upset based on the data statistical information in the step 2.2 and combining the heavy ion fluence to realize quantitative analysis of the single-particle multi-bit upset effect of the device.
2. The method for quantitatively analyzing the heavy-ion single-particle multi-bit upset effect of the device according to claim 1, wherein the method comprises the following steps:
between step 1.2 ] and step 2.1 ] further comprising:
and 1.3, adjusting the incident angle of heavy ions, filling patterns or working voltage of the device and then carrying out 1.2 test.
3. The method for quantitatively analyzing the heavy-ion single-particle multi-bit upset effect of the device according to claim 2, wherein the method comprises the following steps:
between step 1.3 ] and step 2.1 ] further comprising:
and 1.4, selecting a new heavy ion type, changing the LET value of the heavy ions, selecting a proper fluence rate according to the LET value of the heavy ions, irradiating, and then carrying out 1.2 test.
4. The method of claim 3 for quantitatively analyzing the effect of multiple-bit flip of heavy-ion single particles, wherein the method comprises the following steps:
between step 1.4 ] and step 2.1 ] further comprising:
and 1.5, adjusting the incident angle of heavy ions, filling patterns of a device or working voltage, and then carrying out 1.2 test.
5. The method for quantitatively analyzing the effect of heavy-ion single-particle multi-bit upset of the device according to claim 1, 2, 3 or 4, wherein the method comprises the following steps:
in the step 1.1 ], when beam parameters are set, the selection principle of the fluence rate is specifically as follows:
for a memory device with integration level less than 1Mbit, the turnover number of each read-back period test in irradiation is ensured to be less than 0.01% of the total capacity of the chip; for the memory device with integration degree larger than 1Mbit, the number of the flips tested in each read-back period in irradiation is ensured to be not more than 100, thereby controlling the probability of occurrence of one pseudo multi-bit flip to be less than 1 multiplied by 10 -3 。
6. The device of claim 5, wherein the method comprises the following steps:
step 1.2) the predicted turnover number of single particles should be accumulated to exceed 100 but the turnover number should not exceed 1% of the storage capacity of the device, and the maximum ion fluence should not exceed 1E7cm -2 。
7. The method of claim 5 for quantitatively analyzing the effect of heavy-ion single-particle multi-bit upset, wherein the method comprises the following steps:
and 2.1, establishing a mapping relation from the logical address to the physical address of the device based on device information provided by a design manufacturer, or adopting a reverse design method or adopting a heavy ion microbeam and laser microbeam positioning and identifying method.
8. The device according to claim 7, wherein the method comprises the following steps:
and 2.2) counting the number of single-particle events, namely, all single-particle upsets caused by one ion are regarded as one event, and the event is only recorded once no matter the single-particle upsets or the multiple-particle upsets are carried out.
9. The device according to claim 8, wherein the method comprises the following steps:
in step 2.3, single-particle multi-bit upset is characterized and quantified, and the characterization parameters comprise a U-type single-particle upset section, an E-type single-particle event section, a single-particle multi-bit upset event section, a single-particle unit upset event section, a multi-bit upset Mean, a multi-bit upset probability and a probability of a single-particle event with i-bit upset, and the specific characterization method comprises the following steps:
u-shaped, i.e. single-particle upset cross-section sigma U-SEU Expressed as:
type E, i.e. single event cross section σ E-SEU Expressed as:
wherein Event i-bit is the number of single Event events with i-bit upset, and phi is the total fluence of incident ions;
single event multi-bit upset event cross section sigma MCU Expressed as:
single event unit upset event cross section
Multi-bit rolling Mean:
multi-bit flip probability, expressed as:
in the formula, denominator is the sum of all single event events, and numerator is the sum of multi-bit upset events with 2-bit upset and more bit upset;
single Event with i-bit upset i-bit Is expressed as
10. The method of claim 9 for quantitatively analyzing the effect of heavy-ion single-particle multi-bit upset, wherein the method comprises the following steps:
and 2.3, drawing a relation curve between one or more of the single particle characterization parameters and one or more of the heavy ion LET value, the ion incidence angle, the filling pattern and the working voltage.
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| CN103869237A (en) * | 2012-12-12 | 2014-06-18 | 中国科学院空间科学与应用研究中心 | Pulse laser number optimizing method and single-particle overturn cross section testing method |
| CN103345943A (en) * | 2013-05-31 | 2013-10-09 | 中国科学院微电子研究所 | Multi-bit upset detection method based on memorizer without word line segmentation |
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