CN1050114A - 高速cmos差动接口电路 - Google Patents

高速cmos差动接口电路 Download PDF

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CN1050114A
CN1050114A CN90106751A CN90106751A CN1050114A CN 1050114 A CN1050114 A CN 1050114A CN 90106751 A CN90106751 A CN 90106751A CN 90106751 A CN90106751 A CN 90106751A CN 1050114 A CN1050114 A CN 1050114A
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differential
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interface
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戴维·约翰·威尔科克斯
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BAE Systems Electronics Ltd
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GEC Marconi Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

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Abstract

高速CMOS差动输入和输出接口电路包含有 偏置装置控制的输入和输出装置。该偏置装置产生 偏置电压。输出接口有一作为输入装置的单端到差 动转换器和作为输出装置的差动输出级。输入接口 有一作为输入装置的放大器和检测器以及作为输出 装置的差动到单端电平转换器。输入和输出接口使 用时钟编码数据，分别在300MHz和200MHz下操 作，两者都可与双极性器件相接。一个组合的输入/ 输出的接口使用时钟编码数据时可在200MHz下操 作或在正常时钟操作下以60MHz操作。

Description

高速CMOS差动接口电路
本发明涉及CMOS器件高速输入和输出接口电路。
标准CMOS输出驱动器的缺点在于：在不遭受过多硅面损失时只能处理高达大约25MHz的频率以及电源“脉动”。
本发明的一个目的是提供一种能进行所要求的高速操作而没有上述缺点的接口电路。
根据本发明，提供一种含有与输出装置互连的输入装置及与输入、输出装置相连并对输入、输出装置产生偏压的偏压装置的高速CMOS差动接口电路。
根据本发明的一个方面，提供一种接口电路，其中，该电路是一个输出接口电路，输入装置含有一个将输入信号转变为差动信号的转换器，而输出装置是一个根据差动信号、产生驱动传输线的差动电流的电流发生器。
根据本发明的另一方面，提供一种接口电路，其中，该电路是一输入接口电路，输入装置含有用于放大检测差动输入信号的放大器和检测器，而输出装置是用于将差动输入信号转变为单信号的差动到单端电平转换器。
参照附图对本发明的实施例加以说明。附图中：
图1a示出输出接口电路的框图，
图1b示出输入接口电路的框图，
图2示出偏压发生器的电路图，
图3示出单端到差动电平转换器的电路图，
图4示出差动输出级的电路图，以及
图5示出输入放大器和差动到单端电平转换器的电路图。
参照图1a，示出输出接口电路的框图。输入到接口的具有CMOS电平的单端信号通过转换器1被转换为差动信号并进行电平偏移和衰减，使得输入到输出级2的该电平是具有4V和5V单端电平的2伏差动信号。该接口的输出是能驱动50欧姆传输线3、具有1V差动摆动的差动电流。偏置电路即基准偏置发生器4产生一个控制电压，它用来设置差动输出电流和产生单端到差动转换器1和输出级2的偏置电流。
参照图1b，示出了输入接口电路的框图。额定输入是具有在4.5V到5V间摆动的单端电平的1V差动信号。该输入接口对这个输入加以检测，由放大器5放大，并在差动到单端电平转换器中将其变换为具有CMOS电平的单端信号。与上述一样的偏置电路4产生一个对差动放大器输入级5设置偏置电流的控制电压。这个控制电压也提供给转换器6。来自转换器6的输入在电路7中加以缓冲。
参照图2，更详细地示出基准偏置发生器。电流镜M5、M6偏置二极管D1和D2。器件M3，M4的源极电压名义上相等意味着二极管的dV通过M2下降。M1和M2的陷阱与各自的源极相连以消除加在产生的基准电流I(N-陷阱CMOS工艺)上的基底偏置的影响。基准电流由下式给出。I＝BOO(P)*
Figure 9010675100041
其中，dVtm是由于器件M1、M2和M3、M4的阈电压失配引起的器件M1、M2的源极电压失配，Z和N分别是器件对M5、M6和M1、M2的拉制宽度和长度的比率W/L。BOO(P)是P沟道MOS、PMOS器件的电流增益因子。级联电流镜8是用来产生用于控制输入输出接口中偏流的偏置电压Vb。还接入了启动电路，器件M7-M12。
参照图3，下面详细描述单端到差动电平转换器。输入数据在驱动用来把输出节点短路到Vdd以产生单端输出高(HIGH)的第一和第二PMOS器件10、10a之前由反相器加以缓冲。单端输出低(LOW)标称值比Vdd低1V并由电流源11偏置的PMOS负载所设定。该电流源值由偏压VB和器件宽度所设定。该器件长度与基准偏置发生器中的器件M13的长度相同。该电路产生4电路中出现的两个输出信号VSIG和 VSIG。
由基准偏置发生器产生的偏置电流正比于BOO(P)、P沟道MOSFET电流增益，因此通过PMOS负载的电压降与一阶的BOO(P)无关。
参照图4，输出级使用一个级联的源极耦合差动对12-15，其中级间偏置电流由因子3标定并在最后一级产生10mA的标称电流。信号VSIG和 VSIG被提供给第一级12。每一级(除了最后一级)标称差动输出电压摆动是峰一峰2V，即，单端输出摆动为4V至5V。最后一级15能驱动50欧姆的负载产生峰一峰1V(500mV单端)的标称差动输出。如上所述，每一差动对的输出电压摆动(除了最后一级的)和P沟道BOO无关。
参照图5，输入接口的第一级的设计基于使用在输出接口输出级的同样原理。进入的差动输入信号I/P、I/P由差动放大器16加以放大，该差动放大器16使用由电流源17偏置的PMOS负载，而来自基准偏置发生器的信号VB控制所述电流源。然后，该信号通过源极跟随器23进行电平偏移，以确保差动放大器的输出能接通随后的差动到CMOS电平转换器中的PMOS输入器件19。接口输入处的两个反相器20对保证CMOS逻辑电平和减少输出上升和下降时间是必须的。
可使用时钟编码数据分别进行300MHz和200MHz操作的高速差动输入和输出接口已予以说明。在输出和输入接口中的速度分别由单端到差动、差动到单端电平转换器所限制。考虑到与输入输入锁存器等有关的延迟，把组合的输入/输出接口的正常时钟操作下限定为60MHz。然而，使用时钟编码数据，组合的输入/输出的接口最大操作频率为200MHz。两种接口均可与双极性器件相接。

Claims (4)

1.一种高速CMOS差动接口电路，它包含有与输出装置互连的输入装置，与输入、输出装置相连并用以产生输入、输出装置的偏置电压的偏压装置。
2.根据权利要求1的接口电路，其特征在于，该电路是一输出接口电路，输入装置含有用以将输入信号转变为差动信号的转换器，而输出装置是根据差动信号产生用于驱动传输线的差动电流的电流发生器。
3.根据权利要求1的接口电路，其特征在于，该电路是一输入接口电路，输入装置含有一个用于放大检测差动输入信号的放大器和检测器，而输出装置是用以将差动输入信号转变为单端信号的差动到单端电平转换器。
4.根据权利要求1的接口电路，其特征在于，偏置装置含有一个与一对二极管相连并对其偏置用以产生基准电流的电流镜以及另外一个用以产生偏置电压的电流镜。
CN90106751A 1989-08-03 1990-08-03 高速cmos差动接口电路 Pending CN1050114A (zh)

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GB8917739.8 1989-08-03
GB8917739A GB2234872B (en) 1989-08-03 1989-08-03 High speed CMOS differential interface circuits

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AU (1) AU626200B2 (zh)
CA (1) CA2022317A1 (zh)
FI (1) FI903853A0 (zh)
GB (1) GB2234872B (zh)
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103149961A (zh) * 2011-12-06 2013-06-12 扬智科技股份有限公司 电流供应器与其方法
CN113421600A (zh) * 2021-05-20 2021-09-21 南京昉芯微电子有限公司 一种面向异质集成的cmos接口电路

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172016A (en) * 1991-06-28 1992-12-15 Digital Equipment Corporation Five-volt tolerant differential receiver
WO1994022220A1 (en) * 1993-03-24 1994-09-29 Apple Computer, Inc. Differential- to single-ended cmos converter
US5418478A (en) * 1993-07-30 1995-05-23 Apple Computer, Inc. CMOS differential twisted-pair driver
DE69434903T2 (de) * 1993-11-29 2007-04-26 Fujitsu Ltd., Kawasaki Elektronisches System zum Abschluss von Busleitungen
US5734366A (en) * 1993-12-09 1998-03-31 Sharp Kabushiki Kaisha Signal amplifier, signal amplifier circuit, signal line drive circuit and image display device
US5570042B1 (en) * 1995-01-03 2000-10-17 Sgs Thomson Micro Electronics Pecl input buffer
US5789941A (en) * 1995-03-29 1998-08-04 Matra Mhs ECL level/CMOS level logic signal interfacing device
US5821809A (en) * 1996-05-23 1998-10-13 International Business Machines Corporation CMOS high-speed differential to single-ended converter circuit
US5767698A (en) * 1996-06-06 1998-06-16 International Business Machines Corporation High speed differential output driver with common reference
US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US5942940A (en) * 1997-07-21 1999-08-24 International Business Machines Corporation Low voltage CMOS differential amplifier
US5959492A (en) * 1997-10-31 1999-09-28 Vlsi Technology, Inc. High speed differential driver circuitry and methods for implementing the same
US6160423A (en) * 1998-03-16 2000-12-12 Jazio, Inc. High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
US6327205B1 (en) 1998-03-16 2001-12-04 Jazio, Inc. Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate
TR200002649T2 (tr) 1998-03-16 2000-11-21 Jazio Inc. VLSI CMOS arayüz devreleri için yüksek hızlı sinyal üretimi.
JP2000031810A (ja) * 1998-07-10 2000-01-28 Fujitsu Ltd ドライバ回路
US7123660B2 (en) * 2001-02-27 2006-10-17 Jazio, Inc. Method and system for deskewing parallel bus channels to increase data transfer rates
KR20130096495A (ko) * 2012-02-22 2013-08-30 삼성전자주식회사 반도체 장치의 버퍼 회로

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58187015A (ja) * 1982-04-26 1983-11-01 Nippon Telegr & Teleph Corp <Ntt> スイツチト・キヤパシタ回路
US4645951A (en) * 1983-08-31 1987-02-24 Hitachi, Ltd. Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals
US4573212A (en) * 1983-11-21 1986-02-25 American Electronic Laboratories, Inc. Integrated receiver antenna device
US4554515A (en) * 1984-07-06 1985-11-19 At&T Laboratories CMOS Operational amplifier
JPH0644705B2 (ja) * 1984-07-20 1994-06-08 株式会社日立製作所 半導体回路
JPS62230221A (ja) * 1986-03-31 1987-10-08 Toshiba Corp バツフア回路
US4779015A (en) * 1987-05-26 1988-10-18 International Business Machines Corporation Low voltage swing CMOS receiver circuit
US4797631A (en) * 1987-11-24 1989-01-10 Texas Instruments Incorporated Folded cascode amplifier with rail-to-rail common-mode range
US4808848A (en) * 1988-03-07 1989-02-28 Motorola, Inc. Comparator circuit
US4945258A (en) * 1988-12-08 1990-07-31 Grumman Aerospace Corporation Monolithic gaAs high speed switch driver

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103149961A (zh) * 2011-12-06 2013-06-12 扬智科技股份有限公司 电流供应器与其方法
CN103149961B (zh) * 2011-12-06 2014-10-22 扬智科技股份有限公司 电流供应器与其方法
CN113421600A (zh) * 2021-05-20 2021-09-21 南京昉芯微电子有限公司 一种面向异质集成的cmos接口电路
CN113421600B (zh) * 2021-05-20 2023-08-15 南京昉芯微电子有限公司 一种面向异质集成的cmos接口电路

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GB2234872B (en) 1994-04-06
GB8917739D0 (en) 1989-09-20
EP0411789A2 (en) 1991-02-06
AU5972390A (en) 1991-02-07
US5105107A (en) 1992-04-14
KR910005571A (ko) 1991-03-30
PT94868A (pt) 1992-06-30
GB2234872A (en) 1991-02-13
CA2022317A1 (en) 1991-02-04
EP0411789A3 (en) 1992-01-02
AU626200B2 (en) 1992-07-23
FI903853A0 (fi) 1990-08-02

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