PT94868A - Circuito de interface diferencial usando a tecnologia dos semicondutores de oxidos metalicos complementares de alta velocidade - Google Patents

Circuito de interface diferencial usando a tecnologia dos semicondutores de oxidos metalicos complementares de alta velocidade Download PDF

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Publication number
PT94868A
PT94868A PT94868A PT9486890A PT94868A PT 94868 A PT94868 A PT 94868A PT 94868 A PT94868 A PT 94868A PT 9486890 A PT9486890 A PT 9486890A PT 94868 A PT94868 A PT 94868A
Authority
PT
Portugal
Prior art keywords
differential
input
output
interface circuit
signals
Prior art date
Application number
PT94868A
Other languages
English (en)
Inventor
David John Wilcox
Original Assignee
Marconi Gec Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Gec Ltd filed Critical Marconi Gec Ltd
Publication of PT94868A publication Critical patent/PT94868A/pt

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Radar, Positioning & Navigation (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Claims (2)

  1. Os interfaces diferenciais de alta velocidade de entrada e de salda que foram descritos são capazes de operarem a 300 MH» e 200 MEjz respectiraaente utilizando dados codificados por relógio* A velocidade á limitada pelos transdutores de nível simples para diferencial, e do diferencial para nível simples nos interfaces de saída e de entrada respectivamente* fendo em conta os atrasos associados oom os “latchee" (trincos) de entrada e saída etc, então uma operação normal sinoroniza-da por reldgio do interface combinado de entrada/saída é limitada a 60 MH** Contudo, utilizando dados codificados por reldgio a máxima frequêaf* cia de operação do interface combinado de entrada/saída é de 200 IHz* Ambas as interfaces são capazes de fazer o interface com dispositivos bípolares. RBIViyOICACdES 1« - Circuito de interface diferencial usando a tecnologia dos semicondutores de óxido metálico complementares (CMOS) de alta velocidade, ca-raeierisado pelo facto de compreender meios de entrada interligados oom meios ds saída e meios ds polarização ligados aos meios de entrada e de eaída e instalados de maneira a gerar tensóes de polarização para os mef ios ds sntrada e de salda*
  2. 2* - Circuito de interface de acordo com a reivindicação 1, caraeteri— zado pelo facto de ser um circuito de interface de saída, os meios de entrada incluírem um transdutor montado de maneira a transformar um sinal de entrada, em sinais diferenciais e os meios de saída serem uru gerador de corrente que fornece uma corrente diferencial para acionar lanhas de transmissão de acordo com os sinais diferenciais· 33 - Circuito de interface de acordo com a reivindicação 1, caracteri-zado pelo facto de ser um circuito de interface de entrada os meios de entrada incluírem um amplificador « um detector instalados de maneira a amplificarem sinais de entrada diferenciais detectados e os meios de saída serem um transdutor diferencial para nível terminado único instalado de maneira a transformar dados de entrada diferenciais num único sinal. L·' 4* » circuito de interface, de acordo oom a reivindicação 1, caracteri-· zado pelo facto de os meios de polarização compreenderem um espelho da corrente, ligado a e instalado de forma a polarizar um par de diodos ô gerar uma corrente de referência e um outro espelho de corrente instalado de maneira a produzir uma tensão de polarização· lisboa, 31 de Julho de I990 0 Agente Oficial da Propriedade Industrial
    Américo da Silva Carvalho Agente Ofioial de Propriedade Industrial Ji. Castilho, 201-3. E.-1000 LISBOA Telefs. 65 13 39 - 65 4613
PT94868A 1989-08-03 1990-07-31 Circuito de interface diferencial usando a tecnologia dos semicondutores de oxidos metalicos complementares de alta velocidade PT94868A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8917739A GB2234872B (en) 1989-08-03 1989-08-03 High speed CMOS differential interface circuits

Publications (1)

Publication Number Publication Date
PT94868A true PT94868A (pt) 1992-06-30

Family

ID=10661085

Family Applications (1)

Application Number Title Priority Date Filing Date
PT94868A PT94868A (pt) 1989-08-03 1990-07-31 Circuito de interface diferencial usando a tecnologia dos semicondutores de oxidos metalicos complementares de alta velocidade

Country Status (10)

Country Link
US (1) US5105107A (pt)
EP (1) EP0411789A3 (pt)
KR (1) KR910005571A (pt)
CN (1) CN1050114A (pt)
AU (1) AU626200B2 (pt)
CA (1) CA2022317A1 (pt)
FI (1) FI903853A0 (pt)
GB (1) GB2234872B (pt)
IE (1) IE902799A1 (pt)
PT (1) PT94868A (pt)

Families Citing this family (20)

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US5172016A (en) * 1991-06-28 1992-12-15 Digital Equipment Corporation Five-volt tolerant differential receiver
WO1994022220A1 (en) * 1993-03-24 1994-09-29 Apple Computer, Inc. Differential- to single-ended cmos converter
US5418478A (en) * 1993-07-30 1995-05-23 Apple Computer, Inc. CMOS differential twisted-pair driver
EP0655839B1 (en) * 1993-11-29 2007-01-03 Fujitsu Limited Electronic system for terminating bus lines
US5734366A (en) * 1993-12-09 1998-03-31 Sharp Kabushiki Kaisha Signal amplifier, signal amplifier circuit, signal line drive circuit and image display device
US5570042B1 (en) * 1995-01-03 2000-10-17 Sgs Thomson Micro Electronics Pecl input buffer
US5789941A (en) * 1995-03-29 1998-08-04 Matra Mhs ECL level/CMOS level logic signal interfacing device
US5821809A (en) * 1996-05-23 1998-10-13 International Business Machines Corporation CMOS high-speed differential to single-ended converter circuit
US5767698A (en) * 1996-06-06 1998-06-16 International Business Machines Corporation High speed differential output driver with common reference
US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US5942940A (en) * 1997-07-21 1999-08-24 International Business Machines Corporation Low voltage CMOS differential amplifier
US5959492A (en) * 1997-10-31 1999-09-28 Vlsi Technology, Inc. High speed differential driver circuitry and methods for implementing the same
EP1064767B8 (en) 1998-03-16 2007-06-27 Jazio Inc. High speed signaling for interfacing vlsi cmos circuits
US6160423A (en) * 1998-03-16 2000-12-12 Jazio, Inc. High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
US6327205B1 (en) 1998-03-16 2001-12-04 Jazio, Inc. Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate
JP2000031810A (ja) * 1998-07-10 2000-01-28 Fujitsu Ltd ドライバ回路
US7123660B2 (en) * 2001-02-27 2006-10-17 Jazio, Inc. Method and system for deskewing parallel bus channels to increase data transfer rates
CN103149961B (zh) * 2011-12-06 2014-10-22 扬智科技股份有限公司 电流供应器与其方法
KR20130096495A (ko) * 2012-02-22 2013-08-30 삼성전자주식회사 반도체 장치의 버퍼 회로
CN113421600B (zh) * 2021-05-20 2023-08-15 南京昉芯微电子有限公司 一种面向异质集成的cmos接口电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58187015A (ja) * 1982-04-26 1983-11-01 Nippon Telegr & Teleph Corp <Ntt> スイツチト・キヤパシタ回路
US4645951A (en) * 1983-08-31 1987-02-24 Hitachi, Ltd. Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals
US4573212A (en) * 1983-11-21 1986-02-25 American Electronic Laboratories, Inc. Integrated receiver antenna device
US4554515A (en) * 1984-07-06 1985-11-19 At&T Laboratories CMOS Operational amplifier
JPH0644705B2 (ja) * 1984-07-20 1994-06-08 株式会社日立製作所 半導体回路
JPS62230221A (ja) * 1986-03-31 1987-10-08 Toshiba Corp バツフア回路
US4779015A (en) * 1987-05-26 1988-10-18 International Business Machines Corporation Low voltage swing CMOS receiver circuit
US4797631A (en) * 1987-11-24 1989-01-10 Texas Instruments Incorporated Folded cascode amplifier with rail-to-rail common-mode range
US4808848A (en) * 1988-03-07 1989-02-28 Motorola, Inc. Comparator circuit
US4945258A (en) * 1988-12-08 1990-07-31 Grumman Aerospace Corporation Monolithic gaAs high speed switch driver

Also Published As

Publication number Publication date
GB2234872A (en) 1991-02-13
EP0411789A2 (en) 1991-02-06
US5105107A (en) 1992-04-14
CN1050114A (zh) 1991-03-20
IE902799A1 (en) 1991-02-27
GB2234872B (en) 1994-04-06
AU626200B2 (en) 1992-07-23
AU5972390A (en) 1991-02-07
KR910005571A (ko) 1991-03-30
CA2022317A1 (en) 1991-02-04
GB8917739D0 (en) 1989-09-20
EP0411789A3 (en) 1992-01-02
FI903853A0 (fi) 1990-08-02

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BB1A Laying open of patent application

Effective date: 19920207

FC3A Refusal

Effective date: 19960830