CN104979298B - A kind of package substrate and its manufacture craft - Google Patents
A kind of package substrate and its manufacture craft Download PDFInfo
- Publication number
- CN104979298B CN104979298B CN201510360625.3A CN201510360625A CN104979298B CN 104979298 B CN104979298 B CN 104979298B CN 201510360625 A CN201510360625 A CN 201510360625A CN 104979298 B CN104979298 B CN 104979298B
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- China
- Prior art keywords
- upper substrate
- infrabasal plate
- hole
- substrate
- photosensitive
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Abstract
A kind of package substrate and its manufacture craft, it is related to package substrate technical field.Solve existing 2D planar structures package substrate and have that package thickness is higher, the package substrate of 3D structures development difficulty be present and cost is larger, the technical deficiency of production cycle length, includes upper substrate and infrabasal plate；Infrabasal plate is placed in upper substrate bottom, presses and connects with upper substrate underrun glue-line；Photosensitive through hole is offered on upper substrate, chip receiving hole corresponding with photosensitive through hole is offered on infrabasal plate, chip receiving hole size is more than photosensitive through hole；Circuit is respectively equipped with upper substrate and infrabasal plate, the circuit of upper substrate is electrically connected with the circuit of infrabasal plate by plated through-hole structure, upper substrate bottom surface is located at photosensitive through hole periphery and infrabasal plate does not press region and is provided with the plated bumps for being used for flip-chip, and plated bumps are connected with upper substrate bottom surface circuit.Upper substrate is pressed with infrabasal plate by glue-line, and chip hole reduces package thickness.Product is highly integrated, volume-diminished；Most of processing procedure uses traditional PCB manufacture craft, and difficulty is low, with short production cycle.
Description
Technical field
The present invention relates to package substrate technical field.
Background technology
Package substrate can provide electrical connection, protection, support, radiating, assembling and other effects for chip, to realize more pins,
Reduce encapsulating products volume, improve the purpose of electrical property and thermal diffusivity, VHD or multi-chip module.But current encapsulation
Substrate is 2D planar structures mostly, and 2D planar structures have that package thickness is higher, and the package substrate of 3D structures mainly uses
Ceramics, development difficulty and cost are larger, production cycle length.
The content of the invention
In summary, it is an object of the invention to solve existing 2D planar structures package substrate, package thickness to be present higher,
There is development difficulty in the package substrate of 3D structures and cost is larger, the technical deficiency of production cycle length, and propose a kind of encapsulation base
Plate and its manufacture craft.
To solve technical problem proposed by the invention, the technical scheme used for：A kind of package substrate, it is characterised in that
The package substrate includes upper substrate and infrabasal plate；Infrabasal plate is placed in upper substrate bottom, with upper substrate underrun glue-line pressure
Close connection；Photosensitive through hole is offered on upper substrate, chip receiving hole corresponding with photosensitive through hole is offered on infrabasal plate, chip is deposited
Discharge hole size is more than photosensitive through hole；Circuit, the circuit of upper substrate and the circuit of infrabasal plate are respectively equipped with upper substrate and infrabasal plate
Electrically connected by plated through-hole structure, upper substrate bottom surface is located at photosensitive through hole periphery and does not press region with infrabasal plate provided with being used for
The plated bumps of flip-chip, plated bumps are connected with upper substrate bottom surface circuit.
The plated bumps are made up of plating copper substrate, plating Ni interlayer and tin plating outer layer.
Infrabasal plate bottom surface circuit is provided with forms solder terminal by plating copper substrate, plating Ni interlayer and tin plating outer layer.
The manufacture craft of the package substrate, it is characterised in that the technique includes having the following steps：
1) substrate of two pieces of BT resin materials, is chosen, one of substrate is made into upper substrate, another piece is made infrabasal plate；
2）, two pieces of substrates are respectively washed rear sputter titanium and copper, form metal film layer in substrate surface；
3）, on two pieces of substrates respectively through upper photoresist, photoresistance exposure, photoresistance development and electro-coppering operate, in two pieces of bases
Corresponding circuit layer is fabricated on plate respectively；
4）, remove upper substrate on photoresist, re-start photoresist, photoresistance exposure, photoresistance development and photoresistance develop
Upper substrate is sequentially placed into copper, nickel afterwards, electroplated in tin electrolytic cell, plating is electroplated out on the lower surface circuit layer of upper substrate
Projection；
5）, after two pieces of substrates complete electroplating operations, remove photoresist and be placed in the gold for etching away and exposing in etching solution
Belong to film layer, circuit layer is formed circuit with the metal film layer retained；
6）, photosensitive through hole is cut out on upper substrate, it is big with photosensitive through hole correspondence position to cut out size on infrabasal plate
In photosensitive through hole, and the chip receiving hole for needing flip-chip can be accommodated；
7）, upper substrate and infrabasal plate pressed by glue-line, photosensitive through hole forms a ledge structure with chip receiving hole
Chip hole；Described plated bumps are located on step surface；
8）, the upper substrate and infrabasal plate of stitching state are drilled, and hole metallization processing is carried out to drilling.
The 4th）Also include in step and remove photoresist on infrabasal plate, re-start photoresist, photoresistance exposure, photoresistance and show
Shadow and infrabasal plate is sequentially placed into copper, nickel after photoresistance development, electroplated in tin electrolytic cell, in the lower surface circuit of infrabasal plate
The operation of solder terminal is electroplated out on layer.
Beneficial effects of the present invention are：Using the substrate of BT resin materials, there is the excellent characteristic of BT materials, upper substrate with
Infrabasal plate is pressed by glue-line, and the chip receiving hole of the photosensitive through hole and infrabasal plate of upper substrate forms the chip of a ledge structure
Hole, chip can be embedded in the chip receiving hole of infrabasal plate, so as to reduce package thickness.Realize new package substrate construction and
Flip-chip（Flip chip）Technique, make product highly integrated, volume-diminished；Most of processing procedure makes work using traditional PCB
Skill, difficulty is low, with short production cycle.
Brief description of the drawings
Fig. 1 is the upper substrate overlooking the structure diagram before pressing；
Fig. 2 is the upper substrate present invention looks up structural representation before pressing；
Fig. 3 is the infrabasal plate overlooking the structure diagram before pressing；
Fig. 4 is the infrabasal plate present invention looks up structural representation before pressing；
Fig. 5 is the finished product overlooking the structure diagram after pressing；
Fig. 6 is the finished product present invention looks up structural representation after pressing；
Fig. 7 is Fig. 5 Section A-A structural representation；
Fig. 8 is package substrate fabrication processing figure of the present invention.
Embodiment
The structure and technique of the present invention are further said below in conjunction with accompanying drawing and currently preferred specific embodiment
It is bright.
Shown in Fig. 7, package substrate of the invention includes upper substrate 1 and infrabasal plate 2；Infrabasal plate 2 is placed in
The bottom of upper substrate 1, press and connect with the underrun glue-line 4 of upper substrate 1, such as substrate 1 and infrabasal plate 2 are closed by PP glue laminateds.
Photosensitive through hole 11 is offered on upper substrate 1, chip receiving hole 21 corresponding with photosensitive through hole 11, chip are offered on infrabasal plate 2
The size of receiving hole 21 is more than photosensitive through hole 11, and photosensitive through hole 11 forms the chip hole of a ledge structure with chip receiving hole 21,
Chip receiving hole 21 can accommodate the chip for needing upside-down mounting；Upper substrate 1 and the two-sided of infrabasal plate 2 are respectively provided with circuit, upper substrate 1
Circuit is electrically connected with the circuit of infrabasal plate 2 by plated through-hole structure 3；The bottom surface of upper substrate 1 is positioned at the photosensitive periphery of through hole 11 with
Substrate 2 does not press region, that is to say ledge structure chip hole appear on the stage terrace be provided with for flip-chip plated bumps 12,
Plated bumps 12 are connected with the bottom surface circuit of upper substrate 1；Plated bumps 12 are by plating copper substrate, plating Ni interlayer and tin plating outer layer group
Into.The bottom surface circuit of infrabasal plate 2 is provided with forms solder terminal 22 by plating copper substrate, plating Ni interlayer and tin plating outer layer, makes
Obtain output board of the infrabasal plate 2 as paster structure.
Shown in Fig. 8, package substrate manufacture craft of the invention includes having the following steps：
1) substrate of two pieces of BT resin materials, is chosen, and carries out baking and copper etching process, by one of substrate work
Substrate 1, another piece is made infrabasal plate 2；BT resins are a kind of current material, using BMI and triazine as main resin component,
And the thermosetting resin that epoxy resin, polyphenylene oxide resin or allyl compound etc. are formed as modified component is added, with BT
The substrate that resin is made up of raw material has high glass-transition temperature（Tg）(255 ~ 330 DEG C), heat resistance (160 ~ 230 DEG C),
The advantages that moisture resistance, low-k (dk) and low lost factor (df)；
2）, two pieces of substrates are respectively washed rear sputter titanium and copper, metal film layer is formed in substrate surface, for follow-up plating
Make circuit layer and do early-stage preparations；
3）, on two pieces of substrates respectively through upper photoresist, photoresistance exposure, photoresistance development and electro-coppering operate, in two pieces of bases
Corresponding circuit layer is fabricated on plate respectively；Namely circuit layer corresponding with circuit is electroplated out on metal film layer, follow-up
By metal film layer it is corresponding with circuit layer outside after etching away regions, circuit layer is then formed as circuit；
4）, remove upper substrate 1 on photoresist, re-start photoresist, photoresistance exposure, photoresistance development and photoresistance develop
Upper substrate is sequentially placed into copper, nickel afterwards, electroplated in tin electrolytic cell, electricity is electroplated out on the lower surface circuit layer of upper substrate 1
Plate projection 12；Photoresist on infrabasal plate 2 is removed, photoresist, photoresistance exposure, photoresistance is re-started and develops and after photoresistance development
Infrabasal plate 2 is sequentially placed into copper, nickel, electroplated in tin electrolytic cell, welding is electroplated out on the lower surface circuit layer of infrabasal plate 2
Terminal 22；
5）, after two pieces of substrates complete electroplating operations, remove photoresist and be placed in the gold for etching away and exposing in etching solution
Belong to film layer, circuit layer is formed circuit with the metal film layer retained；
6）, laser cuts out photosensitive through hole 11 on upper substrate 1, on infrabasal plate 2 with the photosensitive correspondence position thunder of through hole 11
Penetrate and cut out size and be more than photosensitive through hole 11, and the chip receiving hole 21 for needing flip-chip can be accommodated；
7）, upper substrate 1 pressed with infrabasal plate 2 by PP glue-lines 4, photosensitive through hole 11 forms one with chip receiving hole 21
The chip hole of ledge structure；Described plated bumps 12 are located on step surface；
8）, the upper substrate 1 and infrabasal plate 2 of stitching state are drilled using CNC, and hole metallizations are carried out to drilling 3
Processing, makes the circuit on upper substrate 1 be electrically connected with the circuit on infrabasal plate 2.Hole metallization processing can use first glazing
Resist, then leads to the heavy copper of tradition or sputtering process, and drilling, 3 hole walls form metal conducting layer, remove photoresist afterwards, reach plate
Interlayer conducts effect.
Claims (2)
1. a kind of manufacture craft of package substrate, it is characterised in that the technique includes having the following steps：
1) substrate of two pieces of BT resin materials, is chosen, one of substrate is made into upper substrate, another piece is made infrabasal plate；
2）, two pieces of substrates are respectively washed rear sputter titanium and copper, form metal film layer in substrate surface；
3）, on two pieces of substrates respectively through upper photoresist, photoresistance exposure, photoresistance development and electro-coppering operate, on two pieces of substrates
Corresponding circuit layer is fabricated to respectively；
4）, remove upper substrate on photoresist, re-start photoresist, photoresistance exposure, photoresistance development and photoresistance development after will
Upper substrate is sequentially placed into copper, nickel, electroplated in tin electrolytic cell, and it is convex to electroplate out plating on the lower surface circuit layer of upper substrate
Block；
5）, after two pieces of substrates complete electroplating operations, remove photoresist and be placed in the metal foil for etching away and exposing in etching solution
Film layer, circuit layer is set to form circuit with the metal film layer retained；
6）, photosensitive through hole is cut out on upper substrate, size is cut out with photosensitive through hole correspondence position on infrabasal plate and is more than sense
Light through hole, and the chip receiving hole for needing flip-chip can be accommodated；
7）, upper substrate and infrabasal plate pressed by glue-line, photosensitive through hole forms the core of a ledge structure with chip receiving hole
Film perforation；Described plated bumps are located on step surface；
8）, the upper substrate and infrabasal plate of stitching state are drilled, and hole metallization processing is carried out to drilling.
2. technique according to claim 1, it is characterised in that：The 4th）In also include remove infrabasal plate on photoresist,
Re-start photoresist, photoresistance exposure, photoresistance development and infrabasal plate is sequentially placed into copper, nickel, tin electrolysis after photoresistance development
Electroplated in groove, the operation of solder terminal is electroplated out on the lower surface circuit layer of infrabasal plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510360625.3A CN104979298B (en) | 2015-06-26 | 2015-06-26 | A kind of package substrate and its manufacture craft |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510360625.3A CN104979298B (en) | 2015-06-26 | 2015-06-26 | A kind of package substrate and its manufacture craft |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104979298A CN104979298A (en) | 2015-10-14 |
| CN104979298B true CN104979298B (en) | 2017-11-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510360625.3A Expired - Fee Related CN104979298B (en) | 2015-06-26 | 2015-06-26 | A kind of package substrate and its manufacture craft |
Country Status (1)
| Country | Link |
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| CN (1) | CN104979298B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108315786A (en) * | 2018-01-15 | 2018-07-24 | 江西芯创光电有限公司 | Electro-plating method |
| CN114096078B (en) * | 2021-11-25 | 2023-07-25 | 四川九洲电器集团有限责任公司 | Preparation method of printed board protective cover of device not resistant to high temperature, protective cover and application |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295650A (en) * | 2007-04-25 | 2008-10-29 | 矽品精密工业股份有限公司 | Semiconductor device and its manufacturing method |
| CN103165553A (en) * | 2013-02-04 | 2013-06-19 | 日月光半导体制造股份有限公司 | Semiconductor wafer and semiconductor sealing structure |
| CN103260125A (en) * | 2013-04-12 | 2013-08-21 | 日月光半导体制造股份有限公司 | Chip packaging structure and manufacturing method thereof |
| CN204834595U (en) * | 2015-06-26 | 2015-12-02 | 江西芯创光电有限公司 | Package substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100493063B1 (en) * | 2003-07-18 | 2005-06-02 | 삼성전자주식회사 | BGA package with stacked semiconductor chips and manufacturing method thereof |
-
2015
- 2015-06-26 CN CN201510360625.3A patent/CN104979298B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295650A (en) * | 2007-04-25 | 2008-10-29 | 矽品精密工业股份有限公司 | Semiconductor device and its manufacturing method |
| CN103165553A (en) * | 2013-02-04 | 2013-06-19 | 日月光半导体制造股份有限公司 | Semiconductor wafer and semiconductor sealing structure |
| CN103260125A (en) * | 2013-04-12 | 2013-08-21 | 日月光半导体制造股份有限公司 | Chip packaging structure and manufacturing method thereof |
| CN204834595U (en) * | 2015-06-26 | 2015-12-02 | 江西芯创光电有限公司 | Package substrate |
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| Publication number | Publication date |
|---|---|
| CN104979298A (en) | 2015-10-14 |
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