CN106129016A - Two-way integrated embedded type chip reroutes POP encapsulating structure and preparation method thereof - Google Patents
Two-way integrated embedded type chip reroutes POP encapsulating structure and preparation method thereof Download PDFInfo
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- CN106129016A CN106129016A CN201610654334.XA CN201610654334A CN106129016A CN 106129016 A CN106129016 A CN 106129016A CN 201610654334 A CN201610654334 A CN 201610654334A CN 106129016 A CN106129016 A CN 106129016A
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- insulant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
nullThe present invention relates to a kind of two-way integrated embedded type chip and reroute POP encapsulating structure and preparation method thereof，Described structure includes the first packaging body and the second packaging body，First packaging body includes the second line layer (8)，Second line layer (8) front is provided with the first connection copper post (1) and the first components and parts (2)，First connection copper post (1) and the first components and parts (2) outer encapsulating have the first insulant (3)，First insulant (3) front is provided with first line layer (4)，First line layer (4) front is provided with the second connection copper post (5) and the second components and parts (6)，Second connection copper post (5) and the second components and parts (6) outer encapsulating have the second insulant (7)，Second line layer (8) back side is provided with the 3rd connection copper post (9)，It is provided with metal ball (11) in 3rd connection copper post (9).The present invention can multi-layer biaxially oriented imbed, and passive device attachment number is more, is effectively saved substrate space and improves the integrated level of packaging technology.
Description
Technical field
The present invention relates to a kind of two-way integrated embedded type chip and reroute POP encapsulating structure and preparation method thereof, belong to half
Conductor encapsulation technology field.
Background technology
Along with electronic device develops towards multifunction, miniaturization direction, in electronic system, passive device accounting is also come more
Many.Passive device mainly uses surface-pasted mode at present, does not occupy the substantial amounts of space of substrate surface, and surface is welded
Point quantity is many and interconnection length is longer, greatly reduces the electrical property of system, reliability etc..For saving circuit board/substrate table
Space of planes, and the electronic system that offer is more frivolous, performance is more preferable, reliability is higher, change surface attaching type passive device
For can embedded type passive device, be all embedded in together with active component the ultimate three-dimensional packaging technology within substrate be considered solve
The trend of problem.The most traditional three-dimension packaging structure as it is shown in figure 1, its production method be substrate one side imbed passive,
Active component, pressing or coating insulant, guide to the second articulamentum by laser drilling plating blind hole technology by bottom function
Making line layer again, it yet suffers from following shortcoming: conventional base plate is yielding and thickness is thicker, is unfavorable for improving encapsulation integrated
Degree；Blind hole craft precision is the highest and thermal diffusivity, the best, especially for the product of high-frequency high-power in laser drilling plating.
Summary of the invention
The technical problem to be solved is to provide a kind of two-way integrated embedded type chip for above-mentioned prior art
Reroute POP encapsulating structure and preparation method thereof, it can multi-layer biaxially oriented embedment components and parts, effectively saved substrate space and carried
The high integrated level of packaging technology.
The present invention solves the technical scheme that the problems referred to above are used: a kind of two-way integrated embedded type chip reroutes POP
Encapsulating structure, it includes that the first packaging body and the second packaging body, described first packaging body include the second line layer, described second line
Floor front, road is provided with the first connection copper post and the first components and parts, and described first connection copper post and the first components and parts periphery are encapsulated with
First insulant, described first insulant front is provided with first line layer, and described first line layer front is provided with
Two connect copper post and the second components and parts, and described second connection copper post and the second components and parts periphery are encapsulated with the second insulant, institute
Stating the second line layer back side and be provided with the 3rd connection copper post, described second line layer and the 3rd connects copper post periphery and is encapsulated with the 3rd
Capsulation material, the described 3rd ball region of planting connecting copper post is provided with metal ball, and described second packaging body is stacked in the first encapsulation
On second connection copper post of body.
A kind of two-way integrated embedded type chip reroutes the manufacture method of POP encapsulating structure, and described method includes walking as follows
Rapid:
Step one, take a metal support plate
Step 2, metal support plate front plating the first connection copper post
Step 3, mount the first components and parts in metal support plate front
Step 4, metal support plate front cover ground floor insulant
Cover ground floor insulant in metal support plate front, be ground on ground floor insulant surface, until exposing the
Till one connects copper post；
Step 5, ground floor insulant front plating first line layer
Step 6, first line layer front plating the second connection copper post
Step 7, first line layer front mount the second components and parts
Step 8, ground floor insulant front cover second layer insulant
Cover second layer insulant to be ground on second layer insulant surface in ground floor insulant front, until dew
Till going out the second connection copper post；
Step 9, removal metal support plate
Step 10, the ground floor insulant back side are electroplated the second line layer and the 3rd and are connected copper post
Electroplate the second line layer and the 3rd at the ground floor insulant back side successively and connect copper post, thus form outer pin, second
Line layer connects copper post by first and the first components and parts couple together, and completes the rewiring at the first components and parts back side；
Step 11, the second line layer back side attachment the 3rd components and parts；
Step 12, ground floor insulant back side overlays third layer insulant
At ground floor insulant back side overlays third layer insulant, it is ground on third layer insulant surface, until
Till exposing the 3rd connection copper post；
Step 13, plant ball, cutting
The 3rd connect copper post plant ball region implanted metal ball, the semi-finished product having planted metal ball are cut into single product；
Step 14, stacked package body
The the second connection copper post cut single the finished product obtained stacks other packaging body.
Described step 5 ~ step 8 repeats repeatedly.
Described ground floor insulant, second layer insulant and the 3rd insulant pass through injection, hot pressing or spraying
Mode realizes.
Described first components and parts and the second components and parts are active or passive device.
The mounting method of described first components and parts and the second components and parts use surface mount, some glue, whirl coating, plumber's solder or
The mode of upside-down mounting.
Compared with prior art, it is an advantage of the current invention that:
1, improving constantly along with product requirement little, thin, highdensity, lead frame or substrate require little and thin, conventional substrate
Yielding and thickness is thicker, can only one side encapsulation and manufacture difficulty relatively big, and the subsidiary metal support plate support strength of the present invention is big, and
Two-way can carry out embedment encapsulation, substrate manufacture is thin and integrated level is higher, and properties of product are more preferably；
2, to fill out blind hole craft precision the highest for conventional laser drilling, and the present invention use pure electroplating technology make connect metal column up to
To design and manufacture and the product reliability of Fine pitch, especially high-frequency high-power, electrically and heat dispersion more preferably；
3, the present invention reroutes at chip and forms melting of rewiring technology and Stack Technology by connecting metal column on Process ba-sis
Close, effectively shorten chip and element and the conducting distance to outside outfan, it is possible to decrease electrically loss, shortening transmission time,
And improve the space availability ratio of thermal diffusivity and structure, make full use of the advantage that double technique combines and realize high integration and high-performance
Structure；
4, the multi-layer biaxially oriented embedment of the present invention, passive device attachment number is more, has effectively saved substrate space and has improve encapsulation
The integrated level of technique.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the most traditional three-dimension packaging structure.
Fig. 2 is the schematic diagram that a kind of two-way integrated embedded type chip of the present invention reroutes POP encapsulating structure.
Fig. 3 ~ Figure 16 is that a kind of two-way integrated embedded type chip of the present invention reroutes each of the manufacture method of POP encapsulating structure
Process flow chart.
Wherein:
First connects copper post 1
First components and parts 2
First insulant 3
First line layer 4
Second connects copper post 5
Second components and parts 6
Second insulant 7
Second line layer 8
3rd connects copper post 9
3rd insulant 10
Metal ball 11.
Detailed description of the invention
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As in figure 2 it is shown, the two-way integrated embedded type chip of one in the present embodiment reroutes POP encapsulating structure, it includes
First packaging body and the second packaging body, described first packaging body includes that the second line layer 8, described second line layer 8 front are arranged
The first connection copper post 1 and the first components and parts 2, described first connection copper post 1 and the first components and parts 2 periphery are had to be encapsulated with the first insulation
Material 3, described first insulant 3 front is provided with first line layer 4, and described first line layer 4 front is provided with second even
Connecing copper post 5 and the second components and parts 6, described second connection copper post 5 and the second components and parts 6 periphery are encapsulated with the second insulant 7, institute
Stating second line layer 8 back side and be provided with the 3rd connection copper post 9, described second line layer 8 and the 3rd connection copper post 9 periphery are encapsulated with
3rd capsulation material 10, the described 3rd ball region of planting connecting copper post 9 is provided with metal ball 11, and described second packaging body is stacked in
On second connection copper post 5 of the first packaging body.
Its manufacture method is as follows:
Step one, take a metal support plate
See Fig. 3, take the suitable metal support plate of a piece of thickness, at one layer of copper material thin film of metal support plate surface preplating；
Step 2, metal support plate front plating the first connection copper post
See Fig. 4, stick photoresistance film on the metal support plate surface completing preplating copper material thin film, utilize exposure imaging equipment to carry out figure
Shape exposes, develops and remove partial graphical photoresistance film, electroplates the first connection copper post in the front surface region exposing metal support plate, completes
After the photoresistance film on metal support plate surface is removed；
Step 3, mount the first components and parts
Seeing Fig. 5, mount the first components and parts in metal support plate front, described first components and parts can be active or passive device,
Mounting method can use surface mount, some glue, whirl coating, plumber's solder or upside-down mounting etc.；
Step 4, metal support plate front cover ground floor insulant
See Fig. 6, cover ground floor insulant (can be realized by modes such as injection, hot pressing, sprayings) in metal support plate front,
It is ground on ground floor insulant surface, until exposing the first connection copper post；
Step 5, ground floor insulant front plating first line layer
See Fig. 7, carry out metalized in ground floor insulant front, then carry out the development of photoresistance film press mold on surface and expose
Regional area, first line layer in exposed area plating, finally carry out fast-etching in ground floor insulant front, remove
Metal layer beyond first line layer；
Step 6, first line layer front plating the second connection copper post
See Fig. 8, stick photoresistance film on first line layer surface, utilize exposure imaging equipment to carry out graph exposure, develop and go
Except partial graphical photoresistance film, carry out in the front surface region exposed electroplating the second connection copper post, by first line layer surface after completing
Photoresistance film remove；
Step 7, first line layer front mount the second components and parts
Participating in Fig. 9, mount the first components and parts in first line layer front, described first components and parts can be active or passive device
Part, mounting method can use surface mount, some glue, whirl coating, plumber's solder or upside-down mounting etc.；
Step 8, ground floor insulant front cover second layer insulant
Participating in Figure 10, covering second layer insulant in ground floor insulant front (can be by sides such as injection, hot pressing, sprayings
Formula realizes), it is ground on second layer insulant surface, until exposing the second connection copper post；
Step 9, removal metal support plate
See Figure 11, use etch process to remove metal support plate；
Step 10, the ground floor insulant back side are electroplated the second line layer and the 3rd and are connected copper post
See Figure 12, carry out metalized at the ground floor insulant back side, then carry out photoresistance film press mold development dew on surface
Go out regional area, electroplate the second line layer and the 3rd successively in exposed area and connect copper post, thus form outer pin, the second line
Road floor connects copper post by first and the first components and parts couple together, and completes the rewiring at the first components and parts back side, makes first yuan of device
The function of part, at longitudinal extension, finally carries out fast-etching at the ground floor insulant back side, removes beyond the second line layer
Metal layer；
Step 11, attachment the 3rd components and parts
Seeing Figure 13, mount the 3rd components and parts at the second line layer back side, described 3rd components and parts can be active or passive device
Part, mounting method can use surface mount, some glue, whirl coating, plumber's solder or upside-down mounting etc.；
Step 12, ground floor insulant back side overlays third layer insulant
See Figure 14, (can be by sides such as injection, hot pressing, sprayings at ground floor insulant back side overlays third layer insulant
Formula realizes), it is ground on third layer insulant surface, until exposing the 3rd connection copper post；
Step 13, plant ball, cutting
See Figure 15, the 3rd connect copper post plant ball region implanted metal ball, the semi-finished product having planted metal ball are cut into list
Product；
Step 14, stacked package body
See Figure 16, the second connection copper post cut single the finished product obtained stacks other packaging body.
Described step 5 ~ step 8 may be repeated repeatedly, thus realizes the attachment embedment of multilamellar components and parts.
In addition to the implementation, present invention additionally comprises other embodiments, all employing equivalents or equivalence to replace
The technical scheme that mode is formed, all should fall within the scope of the hereto appended claims.
Claims (6)
1. a two-way integrated embedded type chip reroutes POP encapsulating structure, it is characterised in that: it includes the first packaging body and the
Two packaging bodies, described first packaging body includes that the second line layer (8), described second line layer (8) front are provided with the first connection
Copper post (1) and the first components and parts (2), described first connection copper post (1) and the first components and parts (2) periphery are encapsulated with the first insulation material
Material (3), described first insulant (3) front is provided with first line layer (4), and described first line layer (4) front is provided with
Second connects copper post (5) and the second components and parts (6), and described second connection copper post (5) and the second components and parts (6) periphery are encapsulated with the
Two insulant (7), described second line layer (8) back side be provided with the 3rd connection copper post (9), described second line layer (8) and
3rd connects copper post (9) periphery is encapsulated with the 3rd capsulation material (10), and the described 3rd ball region of planting connecting copper post (9) is provided with
Metal ball (11), described second packaging body stacking is arranged in the second connection copper post (5) of the first packaging body.
2. the manufacture method of a two-way integrated embedded type chip rewiring POP encapsulating structure, it is characterised in that described method bag
Include following steps:
Step one, take a metal support plate
Step 2, metal support plate front plating the first connection copper post
Step 3, mount the first components and parts in metal support plate front
Step 4, metal support plate front cover ground floor insulant
Cover ground floor insulant in metal support plate front, be ground on ground floor insulant surface, until exposing the
Till one connects copper post；
Step 5, ground floor insulant front plating first line layer
Step 6, first line layer front plating the second connection copper post
Step 7, first line layer front mount the second components and parts
Step 8, ground floor insulant front cover second layer insulant
Cover second layer insulant to be ground on second layer insulant surface in ground floor insulant front, until dew
Till going out the second connection copper post；
Step 9, removal metal support plate
Step 10, the ground floor insulant back side are electroplated the second line layer and the 3rd and are connected copper post
Electroplate the second line layer and the 3rd at the ground floor insulant back side successively and connect copper post, thus form outer pin, second
Line layer connects copper post by first and the first components and parts couple together, and completes the rewiring at the first components and parts back side；
Step 11, the second line layer back side attachment the 3rd components and parts；
Step 12, ground floor insulant back side overlays third layer insulant
At ground floor insulant back side overlays third layer insulant, it is ground on third layer insulant surface, until
Till exposing the 3rd connection copper post；
Step 13, plant ball, cutting
The 3rd connect copper post plant ball region implanted metal ball, the semi-finished product having planted metal ball are cut into single product；
Step 14, stacked package body
The the second connection copper post cut single the finished product obtained stacks other packaging body.
A kind of two-way integrated embedded type chip the most according to claim 2 reroutes the manufacture method of POP encapsulating structure, its
It is characterised by: described step 5 ~ step 8 repeats repeatedly.
A kind of two-way integrated embedded type chip the most according to claim 2 reroutes the manufacture method of POP encapsulating structure, its
It is characterised by: described ground floor insulant, second layer insulant and the 3rd insulant are by injection, hot pressing or spraying
Mode realize.
A kind of two-way integrated embedded type chip the most according to claim 2 reroutes the manufacture method of POP encapsulating structure, its
It is characterised by: described first components and parts and the second components and parts are active or passive device.
A kind of two-way integrated embedded type chip the most according to claim 2 reroutes the manufacture method of POP encapsulating structure, its
It is characterised by: the mounting method of described first components and parts and the second components and parts uses surface mount, some glue, whirl coating, plumber's solder
Or the mode of upside-down mounting.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610654334.XA CN106129016A (en) | 2016-08-10 | 2016-08-10 | Two-way integrated embedded type chip reroutes POP encapsulating structure and preparation method thereof |
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| CN201610654334.XA CN106129016A (en) | 2016-08-10 | 2016-08-10 | Two-way integrated embedded type chip reroutes POP encapsulating structure and preparation method thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601636A (en) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | Processing method for attached pre-encapsulated metal communication three-dimensional packaging structure |
| CN106876363A (en) * | 2017-03-13 | 2017-06-20 | 江苏长电科技股份有限公司 | The fan-out package structure and its process of 3D connections |
| CN107507821A (en) * | 2017-09-05 | 2017-12-22 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of integrated image sensor chip and logic chip |
| CN108573876A (en) * | 2017-03-08 | 2018-09-25 | 奥特斯奥地利科技与系统技术有限公司 | Hybrid device carrier and its manufacturing method |
| CN109686669A (en) * | 2018-11-22 | 2019-04-26 | 珠海越亚半导体股份有限公司 | A kind of integrated circuit packaging method and encapsulating structure |
| CN109872987A (en) * | 2019-03-08 | 2019-06-11 | 中国科学院微电子研究所 | System encapsulation board structure with radiator structure and preparation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996895A (en) * | 2009-08-12 | 2011-03-30 | 新科金朋有限公司 | Semiconductor device and method for manufacturing the same |
| CN103165505A (en) * | 2011-12-09 | 2013-06-19 | 三星电子株式会社 | Methods of fabricating fan-out wafer level packages and packages formed by the methods |
| CN104051443A (en) * | 2014-06-30 | 2014-09-17 | 江苏长电科技股份有限公司 | Novel high-density stackable packaging structure and manufacturing method thereof |
| US20150303174A1 (en) * | 2014-04-17 | 2015-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same |
| CN205984940U (en) * | 2016-08-10 | 2017-02-22 | 江阴芯智联电子科技有限公司 | Bidirectional integration burys formula chip POP packaging structure that reroutes |
-
2016
- 2016-08-10 CN CN201610654334.XA patent/CN106129016A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996895A (en) * | 2009-08-12 | 2011-03-30 | 新科金朋有限公司 | Semiconductor device and method for manufacturing the same |
| CN103165505A (en) * | 2011-12-09 | 2013-06-19 | 三星电子株式会社 | Methods of fabricating fan-out wafer level packages and packages formed by the methods |
| US20150303174A1 (en) * | 2014-04-17 | 2015-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same |
| CN104051443A (en) * | 2014-06-30 | 2014-09-17 | 江苏长电科技股份有限公司 | Novel high-density stackable packaging structure and manufacturing method thereof |
| CN205984940U (en) * | 2016-08-10 | 2017-02-22 | 江阴芯智联电子科技有限公司 | Bidirectional integration burys formula chip POP packaging structure that reroutes |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10763128B2 (en) | 2016-12-21 | 2020-09-01 | Jiangsu Changjiang Electronics Technology Co, Ltd. | Process of surface-mounting three-dimensional package structure electrically connected by prepackaged metal |
| WO2018113574A1 (en) * | 2016-12-21 | 2018-06-28 | 江苏长电科技股份有限公司 | Process method for mounting pre-encapsulated metal conductive three-dimensional packaging structure |
| CN106601636B (en) * | 2016-12-21 | 2018-11-09 | 江苏长电科技股份有限公司 | A kind of process of the pre-packaged metal conduction three-dimension packaging structure of attachment |
| CN106601636A (en) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | Processing method for attached pre-encapsulated metal communication three-dimensional packaging structure |
| CN108573876A (en) * | 2017-03-08 | 2018-09-25 | 奥特斯奥地利科技与系统技术有限公司 | Hybrid device carrier and its manufacturing method |
| CN106876363A (en) * | 2017-03-13 | 2017-06-20 | 江苏长电科技股份有限公司 | The fan-out package structure and its process of 3D connections |
| CN107507821A (en) * | 2017-09-05 | 2017-12-22 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and method for packing of integrated image sensor chip and logic chip |
| CN109686669A (en) * | 2018-11-22 | 2019-04-26 | 珠海越亚半导体股份有限公司 | A kind of integrated circuit packaging method and encapsulating structure |
| CN109686669B (en) * | 2018-11-22 | 2021-08-10 | 珠海越亚半导体股份有限公司 | Integrated circuit packaging method and packaging structure |
| CN109872987A (en) * | 2019-03-08 | 2019-06-11 | 中国科学院微电子研究所 | System encapsulation board structure with radiator structure and preparation method thereof |
| CN109872987B (en) * | 2019-03-08 | 2022-03-08 | 中国科学院微电子研究所 | System packaging board card structure with heat dissipation structure and manufacturing method thereof |
| CN112864022A (en) * | 2019-11-26 | 2021-05-28 | 天芯互联科技有限公司 | Manufacturing method of packaging structure and packaging structure |
| CN112864022B (en) * | 2019-11-26 | 2024-03-22 | 天芯互联科技有限公司 | Manufacturing method of packaging structure and packaging structure |
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