CN104968081A - Logic protection emitter coupling-type three-filtering hybrid grid drive system - Google Patents
Logic protection emitter coupling-type three-filtering hybrid grid drive system Download PDFInfo
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- CN104968081A CN104968081A CN201510324034.0A CN201510324034A CN104968081A CN 104968081 A CN104968081 A CN 104968081A CN 201510324034 A CN201510324034 A CN 201510324034A CN 104968081 A CN104968081 A CN 104968081A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a logic protection emitter coupling-type three-filtering hybrid grid drive system, and the system mainly consists of a drive chip M, a drive circuit, an in-phase AC signal amplification circuit, a self-locking excitation circuit, a bootstrapping circuit, a power drive amplification circuit, a three-filtering amplification circuit, and a logic protection emitter coupling-type amplification circuit. The system can achieve the good filtering of noise waves in the circuits, greatly improves the precision of a product, greatly enlarges the application range of the product, can automatically excite the related function of the drive chip M according to the external illumination condition, and does not need to add a starting device. Therefore, the system is lower in power consumption. Meanwhile, the starting time of the system is just 1/4 of the starting time of a conventional grid drive circuit, so the starting time of the system is very short.
Description
Technical field
The present invention relates to a kind of LED drive circuit, specifically refer to virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, therefore its needs are driven by special drive circuit.But, the widely used gate driver circuit of current people due to the irrationality of its project organization, defects such as result in current gate driver circuit and have that energy consumption is higher, current noise comparatively large and start-up time is longer.
Summary of the invention
The object of the invention is to the defect that energy consumption is higher, current noise is comparatively large and start-up time is longer overcoming the existence of current gate driver circuit; a kind of reasonable in design is provided; can effectively reduce energy consumption and current noise, obviously shorten the virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system of start-up time.
Object of the present invention is achieved through the following technical solutions:
Virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system; primarily of driving chip M; the drive circuit be connected with driving chip M; the homophase AC signal amplifying circuit be connected with driving chip M; the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, and the boostrap circuit be connected with this self-locking optical excitation circuit forms.Meanwhile, between self-locking optical excitation circuit and driving chip M, be also provided with power drive amplifying circuit, between power drive amplifying circuit and driving chip M, be then serially connected with three filter amplification circuit and virtual protection emitter-base bandgap grading manifold type amplifying circuit.
Described power drive amplifying circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R9 between the output of power amplifier P1 and negative input and electric capacity C8, be serially connected in the resistance R10 between the output of power amplifier P2 and electrode input end and electric capacity C9, base stage is connected with the output of power amplifier P1, the triode Q2 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, base stage is connected with the emitter of triode Q2, the triode Q3 that collector electrode is connected with the negative input of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R13, the triode Q4 that collector electrode is connected with the base stage of triode Q3 after resistance R16, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q3 and the electric capacity C10 of ground connection, the electric capacity C11 be in parallel with resistance R13, one end is connected with the base stage of triode Q4, the resistance R14 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q4, the resistance R15 of the external-4V voltage of the other end, the electric capacity C12 be in parallel with resistance R15, and N pole is connected with the collector electrode of triode Q2, the diode D2 of the extremely external-4V voltage of P forms, the negative input of described power amplifier P1 is also connected with the electrode input end of power amplifier P2, and the electrode input end of power amplifier P1 is all connected with this self-locking optical excitation circuit with the negative input of power amplifier P2.
Described three filter amplification circuit are by triode VT101, triode VT102, triode VT103, triode VT104, triode VT105, triode VT106, triode VT107, operational amplifier P101, operational amplifier P102, operational amplifier P103, operational amplifier P104, one end is as input, the resistance R101 that the other end is connected with the base stage of triode VT107, the electric capacity C101 in parallel with resistance R101, one end is connected with the base stage of triode VT107, the resistance R103 that the other end is connected with the emitter of triode VT107 after resistance R105, one end is connected with the base stage of triode VT107, the resistance R102 that the other end is connected with the collector electrode of triode VT107 after resistance R104, positive pole is connected with the emitter of triode VT107, the electric capacity C104 that negative pole is connected with the tie point of resistance R105 with resistance R103, be serially connected in the resistance R114 between the base stage of triode VT101 and emitter, one end ground connection, the resistance R113 that the other end is connected with the base stage of triode VT102, P pole is connected with the base stage of triode VT103, the diode D101 that N pole is connected with the collector electrode of triode VT107 after electric capacity C103, P pole is connected with the N pole of diode D101 after diode D102, the diode D103 that N pole is connected with the base stage of triode VT106, one end is connected with the base stage of triode VT106, the resistance R111 that the other end is connected with the output of operational amplifier P104, one end ground connection, the resistance R112 that the other end is connected with the emitter of triode VT104, minus earth, the electric capacity C105 that positive pole is connected with the positive pole of electric capacity C104 after resistance R106, one end is connected with the positive pole of electric capacity C105, the resistance R108 that the other end is connected with the negative input end of operational amplifier P101, one end is connected with the positive pole of electric capacity C105, the resistance R107 that the other end is connected with the output of operational amplifier P101, be serially connected in the electric capacity C106 between the negative input end of operational amplifier P101 and output, minus earth, the electric capacity C108 that positive pole is connected with the positive input terminal of operational amplifier P102, negative pole is connected with the output of operational amplifier P101 after resistance R109, the electric capacity C107 that positive pole is connected with the negative input end of operational amplifier P102, one end is connected with the negative pole of electric capacity C107, the resistance R110 that the other end is connected with the positive pole of electric capacity C108, negative pole is connected with the base stage of triode VT107, the electric capacity C102 that positive pole is connected with the emitter of triode VT104 after resistance R115, minus earth, the electric capacity C109 that positive pole is connected with the tie point of resistance R104 with resistance R102 after resistance R116, one end is connected with the positive pole of electric capacity C109, the resistance R118 that the other end is connected with the negative input end of operational amplifier P103, one end is connected with the positive pole of electric capacity C109, the resistance R117 that the other end is connected with the positive input terminal of operational amplifier P103, be serially connected in the electric capacity C110 between the negative input end of operational amplifier P103 and output, minus earth, the electric capacity C111 that positive pole is connected with the negative pole of electric capacity C104 after resistance R119, one end is connected with the positive pole of electric capacity C111, the resistance R121 that the other end is connected with the negative input end of operational amplifier P104, one end is connected with the positive pole of electric capacity C111, the resistance R120 that the other end is connected with the output of operational amplifier P104, and the electric capacity C112 be serially connected between the negative input end of operational amplifier P104 and output forms, wherein, the negative pole of electric capacity C104 is also connected with the collector electrode of triode VT105 with the collector electrode of triode VT106 simultaneously, the emitter of triode VT101, the collector electrode of triode VT103 is all connected with the output of operational amplifier P103 with the collector electrode of triode VT104, the positive input terminal ground connection of operational amplifier P103, the base stage of triode VT101 is connected with the emitter of triode VT102, the collector electrode of triode VT101 is connected with the base stage of triode VT102, the collector electrode of triode VT102 is connected with the base stage of triode VT103, the emitter of triode VT103 is connected with the base stage of triode VT104, the emitter of triode VT104 is connected with the emitter of triode VT105, the base stage of triode VT105 is connected with the emitter of triode VT106, the positive input terminal ground connection of operational amplifier P101, the positive pole of electric capacity C107 is also connected with the output of operational amplifier P102 and the N pole of diode D101 simultaneously, the positive input terminal ground connection of operational amplifier P104, the emitter of described triode VT104 is connected as output and with the TD pin of driving chip M.
Described virtual protection emitter-base bandgap grading manifold type amplifying circuit is primarily of triode Q5, triode Q6, power amplifier P4, power amplifier P5, be serially connected in the resistance R18 between the negative input of power amplifier P4 and output, be serially connected in the polar capacitor C15 between the electrode input end of power amplifier P5 and output, be serially connected in the resistance R17 between the electrode input end of power amplifier P4 and the collector electrode of triode Q5, be serially connected in the resistance R19 between the collector electrode of triode Q5 and the base stage of triode Q6, the electric capacity C14 be in parallel with resistance R19, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C13 that positive pole is connected with the emitter of triode Q5 after resistance R20, be serially connected in the resistance R21 between the base stage of triode Q6 and the positive pole of polar capacitor C13, positive pole is connected with the emitter of triode Q6, negative pole is in turn through electric capacity C16 that voltage stabilizing didoe D3 is connected with the output of power amplifier P4 after resistance R22, P pole is connected with the output of power amplifier P5, the diode D4 that N pole is connected with the tie point of resistance R22 with voltage stabilizing didoe D3 after resistance R23 through resistance R24, and P pole is connected with the negative pole of electric capacity C16, the voltage stabilizing didoe D5 that N pole is connected with the tie point of resistance R24 with diode D4 forms, the base stage of described triode Q5 is connected with the positive pole of polar capacitor C13, and its emitter is connected with the emitter of triode Q6, and its collector electrode is connected with the negative input of power amplifier P4, the collector electrode of triode Q6 is connected with the negative input of power amplifier P5, and the electrode input end of power amplifier P5 is connected with the output of power amplifier P4, the positive pole of described polar capacitor C13 is connected with the output of power amplifier P3, and resistance R23 is then connected with the input of resistance R101 with the tie point of resistance R24.
Described homophase AC signal amplifying circuit is by power amplifier P, the resistance R7 that one end is connected with the VCC pin of driving chip M, the other end is connected with the electrode input end of power amplifier P, the resistance R6 that one end is connected with the negative input of power amplifier P, the other end is connected with self-locking optical excitation circuit, and positive pole is connected with the electrode input end of power amplifier P, the polar capacitor C4 of negative pole external power supply forms, the output of described power amplifier P is connected with the INP pin of driving chip M.
Described self-locking optical excitation circuit is by NOR gate IC1, NOR gate IC2, NOR gate IC3, the photocell CDS that one end is connected with the electrode input end of power amplifier P, the other end is connected with the negative input of power amplifier P2 after potentiometer R5, and the electric capacity C3 be serially connected between the electrode input end of NOR gate IC3 and output forms; The electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected; The output of described NOR gate IC2 then simultaneously the negative input of AND OR NOT gate IC3 be connected with the electrode input end of power amplifier P1, the output of the output of NOR gate IC3 then power amplifier P is connected; The output of the other end of described resistance R6 then AND OR NOT gate IC2 is connected.
Described boostrap circuit is by field effect transistor MOS, one end is connected with the source electrode of field effect transistor MOS, the resistance R4 of other end ground connection, the polar capacitor C1 that negative pole is connected with the grid of field effect transistor MOS, positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, the polar capacitor C2 that positive pole is connected with the positive pole of polar capacitor C1, the negative input of negative pole AND OR NOT gate IC2 is connected, and one end is connected with the positive pole of polar capacitor C2, the resistance R3 of other end ground connection forms; The drain electrode of described field effect transistor MOS is connected with the tie point of resistance R7 with photocell CDS.
Described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C5 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R8 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode in turn after electric capacity C6 and electric capacity C7 ground connection and the transistor Q1 of grounded emitter form; The Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, ground connection after its non-same polarity is then connected with the emitter of transistor Q1; Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
For guaranteeing result of use, driving chip M of the present invention preferentially adopts LTC4440A integrated chip to realize.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) the present invention can excite the correlation function of driving chip M automatically according to outside illumination condition, and without the need to increasing extra starting drive, therefore its power consumption is lower.
(2) be only 1/4 of conventional gate drive circuit start-up time start-up time of the present invention, its start-up time is extremely short.
(3) the present invention adopts boostrap circuit to provide control signal for self-locking optical excitation circuit and driving chip, therefore has very high input impedance, can guarantee the stable performance of whole circuit
(4) the present invention effectively can avoid external electromagnetic interference, can reduce current noise significantly.
(5) be provided with homophase AC signal amplifying circuit in the present invention, therefore can guarantee that the intensity of pulse signal can not decay, thus guarantee stable performance.
(6) be provided with three filter amplification circuit in the present invention, can be good at filtering the clutter in circuit, substantially increase accuracy and the scope of application of product.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Fig. 2 is power drive amplification circuit structure schematic diagram of the present invention.
Fig. 3 is virtual protection emitter-base bandgap grading manifold type amplification circuit structure schematic diagram of the present invention.
Fig. 4 is the circuit diagram of three filter amplification circuit of the present invention.
Description of reference numerals:
10, three filter amplification circuit; 20, virtual protection emitter-base bandgap grading manifold type amplifying circuit; 30, power drive amplifying circuit.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1; the present invention is primarily of driving chip M; the drive circuit be connected with driving chip M; the homophase AC signal amplifying circuit be connected with driving chip M; the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit; the boostrap circuit be connected with this self-locking optical excitation circuit; be serially connected in the power drive amplifying circuit 30 between self-locking optical excitation circuit and driving chip M, and three filter amplification circuit 10 be serially connected between power drive amplifying circuit 30 and driving chip M and virtual protection emitter-base bandgap grading manifold type amplifying circuit 20 form.
For guaranteeing result of use, the high-frequency N-channel MOS FET grid drive chip that this driving chip M preferentially adopts Linear Techn Inc. to produce, namely LTC4440A integrated chip realizes.The feature of this driving chip M is can with the input voltage work up to 80V, and can up to can continuous operation during 100V transient state.
The structure of described power drive amplifying circuit 30 as shown in Figure 2, namely it is primarily of power amplifier P1, power amplifier P2, power amplifier P3, triode Q2, triode Q3, triode Q4, be serially connected in the one-level RC filter circuit between the output of power amplifier P1 and negative input, be serially connected in the secondary RC filter circuit between the output of power amplifier P2 and electrode input end, and resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, electric capacity C10, electric capacity C11, electric capacity C12 and diode D2 form.
Wherein, described one-level RC filtered electrical routing resistance R9 and electric capacity C8 is formed in parallel, namely between resistance R9 and the electric capacity C8 negative input that is all serially connected in power amplifier P1 and output; Described secondary RC filter circuit is then formed in parallel by resistance R10 and electric capacity C9, namely between resistance R10 and the electric capacity C9 electrode input end that is all serially connected in power amplifier P2 and output.Meanwhile, the negative input of power amplifier P1 is also connected with the electrode input end of power amplifier P2.
The base stage of triode Q2 is connected with the output of power amplifier P1, and its collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, and its emitter is then connected with the base stage of triode Q3; The collector electrode of triode Q3 is connected with the negative input of power amplifier P3 after resistance R12, meanwhile, and the collector electrode also external+10V voltage of this triode Q3.
The base stage of triode Q4 is connected with the output of power amplifier P2 after resistance R13, and its collector electrode is then connected with the base stage of triode Q3 after resistance R16.Electric capacity C11 is then in parallel with resistance R13, and for guaranteeing effect, this electric capacity C11 preferentially adopts electrochemical capacitor to realize.During connection, the negative pole of electric capacity C11 is connected with the base stage of triode Q4, and its positive pole is then connected with the output of power amplifier P2.The positive pole of electric capacity C10 is connected with the negative input of power amplifier P3, and its negative pole is then connected with the emitter of triode Q3.Meanwhile, the negative pole of this electric capacity C10 and the equal ground connection of emitter of triode Q3.
One end of resistance R14 is connected with the base stage of triode Q4, the voltage of the external-4V of its other end; And one end of resistance R15 is connected with the emitter of triode Q4, the voltage of its other end then external equally-4V.Electric capacity C12 is then in parallel with resistance R15.Equally, described electric capacity C10 and electric capacity C12 also all adopts electrochemical capacitor to realize.
The N pole of described diode D2 is connected with the collector electrode of triode Q2, and its P pole is at the voltage of external-4V.For guaranteeing the normal operation of power amplifier P1 and power amplifier P2, this electric capacity C8 and electric capacity C9 all preferentially adopts patch capacitor to realize.And the resistance of resistance R9, resistance R10 is 10K Ω, the resistance of resistance R11, resistance R12, resistance R13, resistance R14, resistance R15 and resistance R16 is 20K Ω.
Described homophase AC signal amplifying circuit is by power amplifier P, and resistance R7, resistance R6 and polar capacitor C4 form.During connection, one end of resistance R7 is connected with the VCC pin of driving chip M, and its other end is connected with the electrode input end of power amplifier P; And one end of resistance R6 is connected with the negative input of power amplifier P, its other end is connected with self-locking optical excitation circuit; The positive pole of polar capacitor C4 is connected with the electrode input end of power amplifier P, its negative pole external power supply Vin.
The output of described power amplifier P is connected with the INP pin of driving chip M, and for guaranteeing that power amplifier P can normally work, the magnitude of voltage of this external power supply Vin needs to be 6 ~ 12V.
Self-locking optical excitation circuit is by NOR gate IC1, and NOR gate IC2, NOR gate IC3, photocell CDS, potentiometer R5 and electric capacity C3 form.During connection, one end of photocell CDS is connected with the electrode input end of power amplifier P, and its other end is connected with the negative input of power amplifier P2 after potentiometer R5.This photocell CDS is once sense outside illumination, then its limit self-excitation can produce electric energy, for driving chip M.
Described electric capacity C3 is serially connected between the electrode input end of NOR gate IC3 and output, and namely the positive pole of electric capacity C3 wants the electrode input end of AND OR NOT gate IC3 to be connected, and the output of its negative pole then AND OR NOT gate IC3 is connected.
Meanwhile, the electrode input end of NOR gate IC1 will be connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected.The output of described NOR gate IC2 then needs the negative input of AND OR NOT gate IC3 to be simultaneously connected with the electrode input end of power amplifier P1, and the output of the output of NOR gate IC3 then power amplifier P is connected.
The output of the other end AND OR NOT gate IC2 of resistance R6 is connected, and namely the output of NOR gate IC2 is connected with the negative input of power amplifier P after resistance R6.Meanwhile, the negative input of this NOR gate IC2 will be connected with boostrap circuit.
Described boostrap circuit is made up of field effect transistor MOS, resistance R1, resistance R2, resistance R3, resistance R4 and polar capacitor C1 and polar capacitor C2.During connection, one end of resistance R4 is connected with the source electrode of field effect transistor MOS, other end ground connection; The negative pole of polar capacitor C1 is connected with the grid of field effect transistor MOS, and its positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1; Resistance R2 and polar capacitor C1 is in parallel, and the positive pole of polar capacitor C2 is connected with the positive pole of polar capacitor C1, and the negative input of its negative pole AND OR NOT gate IC2 is connected.
One end of resistance R3 is connected with the positive pole of polar capacitor C2, its other end ground connection.Meanwhile, the drain electrode needs of this field effect transistor MOS are connected with the tie point of resistance R7 with photocell CDS, to guarantee that photocell CDS can provide operating voltage for field effect transistor MOS.
Described drive circuit is then made up of transformer T, diode D1, electric capacity C5, resistance R8, electric capacity C6, electric capacity C7 and transistor Q1.During connection, the P pole of diode D1 is connected with the VCC pin of driving chip M, and its N pole is then connected with the BOOST pin of driving chip M.The positive pole of electric capacity C5 is connected with the BOOST pin of driving chip M, and its negative pole is then connected with the TG pin of driving chip M.For guaranteeing the normal operation of driving chip M, its VCC holds the voltage needing external+12V.
Resistance R8 is divider resistance, and it is serially connected with between the TG pin of driving chip M and TS pin.The base stage of transistor Q1 is then connected with the TG pin of driving chip M, and its collector electrode is ground connection after electric capacity C6 and electric capacity C7 in turn, its grounded emitter.Meanwhile, the collector electrode of this transistor Q1 also needs the direct voltage of external+6V, to guarantee that transistor Q1 has enough bias voltages to drive himself conducting.
Described transformer T exports to outside field effect transistor after being used for that+the 6V of outside direct voltage is carried out transformation process.The Same Name of Ends of the primary coil of this transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, ground connection after its non-same polarity is then connected with the emitter of transistor Q1.Meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
The Same Name of Ends of the secondary coil of transformer T, tap Y1, tap Y2 together with the non-same polarity of secondary coil as output of the present invention.According to the situation of reality, user can only select any one or several port of these four outputs to use.
The structure of described virtual protection emitter-base bandgap grading manifold type amplifying circuit 20 as shown in Figure 3, it is primarily of triode Q5, triode Q6, power amplifier P4, power amplifier P5, be serially connected in the resistance R18 between the negative input of power amplifier P4 and output, be serially connected in the polar capacitor C15 between the electrode input end of power amplifier P5 and output, be serially connected in the resistance R17 between the electrode input end of power amplifier P4 and the collector electrode of triode Q5, be serially connected in the resistance R19 between the collector electrode of triode Q5 and the base stage of triode Q6, the electric capacity C14 be in parallel with resistance R19, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C13 that positive pole is connected with the emitter of triode Q5 after resistance R20, be serially connected in the resistance R21 between the base stage of triode Q6 and the positive pole of polar capacitor C13, positive pole is connected with the emitter of triode Q6, negative pole is in turn through electric capacity C16 that voltage stabilizing didoe D3 is connected with the output of power amplifier P4 after resistance R22, P pole is connected with the output of power amplifier P5, the diode D4 that N pole is connected with the tie point of resistance R22 with voltage stabilizing didoe D3 after resistance R23 through resistance R24, and P pole is connected with the negative pole of electric capacity C16, the voltage stabilizing didoe D5 that N pole is connected with the tie point of resistance R24 with diode D4 forms.
Meanwhile, the base stage of described triode Q5 is connected with the positive pole of polar capacitor C13, and its emitter is connected with the emitter of triode Q6, and its collector electrode is connected with the negative input of power amplifier P4; The collector electrode of triode Q6 is connected with the negative input of power amplifier P5, and the electrode input end of power amplifier P5 is connected with the output of power amplifier P4.
During connection, the positive pole of described polar capacitor C13 will be connected with the output of power amplifier P3, and resistance R23 is then connected with the input of resistance R101 with the tie point of resistance R24.
As shown in Figure 4, described three filter amplification circuit 10 are by triode VT101, triode VT102, triode VT103, triode VT104, triode VT105, triode VT106, triode VT107, operational amplifier P101, operational amplifier P102, operational amplifier P103, operational amplifier P104, resistance R101, resistance R102, resistance R103, resistance R104, resistance R105, resistance R106, resistance R107, resistance R108, resistance R109, resistance R110, resistance R111, resistance R112, resistance R113, resistance R114, resistance R115, resistance R116, resistance R117, resistance R118, resistance R119, resistance R120, resistance R121, electric capacity C101, electric capacity C102, electric capacity C103, electric capacity C104, electric capacity C105, electric capacity C106, electric capacity C107, electric capacity C108, electric capacity C109, electric capacity C110, electric capacity C111, electric capacity C112, diode D101, diode D102, diode D103 forms.
During connection, one end of resistance R101 is as input, the other end is connected with the base stage of triode VT107, electric capacity C101 is in parallel with resistance R101, one end of resistance R103 is connected with the base stage of triode VT107, the other end is connected with the emitter of triode VT107 after resistance R105, one end of resistance R102 is connected with the base stage of triode VT107, the other end is connected with the collector electrode of triode VT107 after resistance R104, the positive pole of electric capacity C104 is connected with the emitter of triode VT107, negative pole is connected with the tie point of resistance R105 with resistance R103, between the base stage that resistance R114 is serially connected in triode VT101 and emitter, one end ground connection of resistance R113, the other end is connected with the base stage of triode VT102, the P pole of diode D101 is connected with the base stage of triode VT103, N pole is connected with the collector electrode of triode VT107 after electric capacity C103, the P pole of diode D103 is connected with the N pole of diode D101 after diode D102, N pole is connected with the base stage of triode VT106, one end of resistance R111 is connected with the base stage of triode VT106, the other end is connected with the output of operational amplifier P104, one end ground connection of resistance R112, the other end is connected with the emitter of triode VT104, the minus earth of electric capacity C105, positive pole is connected with the positive pole of electric capacity C104 after resistance R106, one end of resistance R108 is connected with the positive pole of electric capacity C105, the other end is connected with the negative input end of operational amplifier P101, one end of resistance R107 is connected with the positive pole of electric capacity C105, the other end is connected with the output of operational amplifier P101, between the negative input end being serially connected in operational amplifier P101 of electric capacity C106 and output, the minus earth of electric capacity C108, positive pole is connected with the positive input terminal of operational amplifier P102, the negative pole of electric capacity C107 is connected with the output of operational amplifier P101 after resistance R109, positive pole is connected with the negative input end of operational amplifier P102, one end of resistance R110 is connected with the negative pole of electric capacity C107, the other end is connected with the positive pole of electric capacity C108, the negative pole of electric capacity C102 is connected with the base stage of triode VT107, positive pole is connected with the emitter of triode VT104 after resistance R115, the minus earth of electric capacity C109, positive pole is connected with the tie point of resistance R104 with resistance R102 after resistance R116, one end of resistance R118 is connected with the positive pole of electric capacity C109, the other end is connected with the negative input end of operational amplifier P103, one end of resistance R117 is connected with the positive pole of electric capacity C109, the other end is connected with the positive input terminal of operational amplifier P103, between the negative input end that electric capacity C110 is serially connected in operational amplifier P103 and output, the minus earth of electric capacity C111, positive pole is connected with the negative pole of electric capacity C104 after resistance R119, one end of resistance R121 is connected with the positive pole of electric capacity C111, the other end is connected with the negative input end of operational amplifier P104, one end of resistance R120 is connected with the positive pole of electric capacity C111, the other end is connected with the output of operational amplifier P104, between the negative input end that electric capacity C112 is serially connected in operational amplifier P104 and output, wherein, the negative pole of electric capacity C104 is also connected with the collector electrode of triode VT105 with the collector electrode of triode VT106 simultaneously, the emitter of triode VT101, the collector electrode of triode VT103 is all connected with the output of operational amplifier P103 with the collector electrode of triode VT104, the positive input terminal ground connection of operational amplifier P103, the base stage of triode VT101 is connected with the emitter of triode VT102, the collector electrode of triode VT101 is connected with the base stage of triode VT102, the collector electrode of triode VT102 is connected with the base stage of triode VT103, the emitter of triode VT103 is connected with the base stage of triode VT104, the emitter of triode VT104 is connected with the emitter of triode VT105, the base stage of triode VT105 is connected with the emitter of triode VT106, the positive input terminal ground connection of operational amplifier P101, the positive pole of electric capacity C107 is also connected with the output of operational amplifier P102 and the N pole of diode D101 simultaneously, the positive input terminal ground connection of operational amplifier P104, the emitter of described triode VT104 is connected as output and with the TD pin of driving chip M.
As mentioned above, just the present invention can well be realized.
Claims (6)
1. virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system, primarily of driving chip M, the drive circuit be connected with driving chip M, the homophase AC signal amplifying circuit be connected with driving chip M, the self-locking optical excitation circuit be connected with homophase AC signal amplifying circuit, and the boostrap circuit to be connected with this self-locking optical excitation circuit forms, it is characterized in that, power drive amplifying circuit (30) is also provided with between self-locking optical excitation circuit and driving chip M, three filter amplification circuit (10) and virtual protection emitter-base bandgap grading manifold type amplifying circuit (20) is then serially connected with between power drive amplifying circuit (30) and driving chip M,
Described power drive amplifying circuit (30) is primarily of power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R9 between the output of power amplifier P1 and negative input and electric capacity C8, be serially connected in the resistance R10 between the output of power amplifier P2 and electrode input end and electric capacity C9, base stage is connected with the output of power amplifier P1, the triode Q2 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, base stage is connected with the emitter of triode Q2, the triode Q3 that collector electrode is connected with the negative input of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R13, the triode Q4 that collector electrode is connected with the base stage of triode Q3 after resistance R16, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q3 and the electric capacity C10 of ground connection, the electric capacity C11 be in parallel with resistance R13, one end is connected with the base stage of triode Q4, the resistance R14 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q4, the resistance R15 of the external-4V voltage of the other end, the electric capacity C12 be in parallel with resistance R15, and N pole is connected with the collector electrode of triode Q2, the diode D2 of the extremely external-4V voltage of P forms, the negative input of described power amplifier P1 is also connected with the electrode input end of power amplifier P2, and the electrode input end of power amplifier P1 is all connected with this self-locking optical excitation circuit with the negative input of power amplifier P2,
Described three filter amplification circuit (10) are by triode VT101, triode VT102, triode VT103, triode VT104, triode VT105, triode VT106, triode VT107, operational amplifier P101, operational amplifier P102, operational amplifier P103, operational amplifier P104, one end is as input, the resistance R101 that the other end is connected with the base stage of triode VT107, the electric capacity C101 in parallel with resistance R101, one end is connected with the base stage of triode VT107, the resistance R103 that the other end is connected with the emitter of triode VT107 after resistance R105, one end is connected with the base stage of triode VT107, the resistance R102 that the other end is connected with the collector electrode of triode VT107 after resistance R104, positive pole is connected with the emitter of triode VT107, the electric capacity C104 that negative pole is connected with the tie point of resistance R105 with resistance R103, be serially connected in the resistance R114 between the base stage of triode VT101 and emitter, one end ground connection, the resistance R113 that the other end is connected with the base stage of triode VT102, P pole is connected with the base stage of triode VT103, the diode D101 that N pole is connected with the collector electrode of triode VT107 after electric capacity C103, P pole is connected with the N pole of diode D101 after diode D102, the diode D103 that N pole is connected with the base stage of triode VT106, one end is connected with the base stage of triode VT106, the resistance R111 that the other end is connected with the output of operational amplifier P104, one end ground connection, the resistance R112 that the other end is connected with the emitter of triode VT104, minus earth, the electric capacity C105 that positive pole is connected with the positive pole of electric capacity C104 after resistance R106, one end is connected with the positive pole of electric capacity C105, the resistance R108 that the other end is connected with the negative input end of operational amplifier P101, one end is connected with the positive pole of electric capacity C105, the resistance R107 that the other end is connected with the output of operational amplifier P101, be serially connected in the electric capacity C106 between the negative input end of operational amplifier P101 and output, minus earth, the electric capacity C108 that positive pole is connected with the positive input terminal of operational amplifier P102, negative pole is connected with the output of operational amplifier P101 after resistance R109, the electric capacity C107 that positive pole is connected with the negative input end of operational amplifier P102, one end is connected with the negative pole of electric capacity C107, the resistance R110 that the other end is connected with the positive pole of electric capacity C108, negative pole is connected with the base stage of triode VT107, the electric capacity C102 that positive pole is connected with the emitter of triode VT104 after resistance R115, minus earth, the electric capacity C109 that positive pole is connected with the tie point of resistance R104 with resistance R102 after resistance R116, one end is connected with the positive pole of electric capacity C109, the resistance R118 that the other end is connected with the negative input end of operational amplifier P103, one end is connected with the positive pole of electric capacity C109, the resistance R117 that the other end is connected with the positive input terminal of operational amplifier P103, be serially connected in the electric capacity C110 between the negative input end of operational amplifier P103 and output, minus earth, the electric capacity C111 that positive pole is connected with the negative pole of electric capacity C104 after resistance R119, one end is connected with the positive pole of electric capacity C111, the resistance R121 that the other end is connected with the negative input end of operational amplifier P104, one end is connected with the positive pole of electric capacity C111, the resistance R120 that the other end is connected with the output of operational amplifier P104, and the electric capacity C112 be serially connected between the negative input end of operational amplifier P104 and output forms, wherein, the negative pole of electric capacity C104 is also connected with the collector electrode of triode VT105 with the collector electrode of triode VT106 simultaneously, the emitter of triode VT101, the collector electrode of triode VT103 is all connected with the output of operational amplifier P103 with the collector electrode of triode VT104, the positive input terminal ground connection of operational amplifier P103, the base stage of triode VT101 is connected with the emitter of triode VT102, the collector electrode of triode VT101 is connected with the base stage of triode VT102, the collector electrode of triode VT102 is connected with the base stage of triode VT103, the emitter of triode VT103 is connected with the base stage of triode VT104, the emitter of triode VT104 is connected with the emitter of triode VT105, the base stage of triode VT105 is connected with the emitter of triode VT106, the positive input terminal ground connection of operational amplifier P101, the positive pole of electric capacity C107 is also connected with the output of operational amplifier P102 and the N pole of diode D101 simultaneously, the positive input terminal ground connection of operational amplifier P104, the emitter of described triode VT104 is connected as output and with the TD pin of driving chip M,
Described virtual protection emitter-base bandgap grading manifold type amplifying circuit (20) is primarily of triode Q5, triode Q6, power amplifier P4, power amplifier P5, be serially connected in the resistance R18 between the negative input of power amplifier P4 and output, be serially connected in the polar capacitor C15 between the electrode input end of power amplifier P5 and output, be serially connected in the resistance R17 between the electrode input end of power amplifier P4 and the collector electrode of triode Q5, be serially connected in the resistance R19 between the collector electrode of triode Q5 and the base stage of triode Q6, the electric capacity C14 be in parallel with resistance R19, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C13 that positive pole is connected with the emitter of triode Q5 after resistance R20, be serially connected in the resistance R21 between the base stage of triode Q6 and the positive pole of polar capacitor C13, positive pole is connected with the emitter of triode Q6, negative pole is in turn through electric capacity C16 that voltage stabilizing didoe D3 is connected with the output of power amplifier P4 after resistance R22, P pole is connected with the output of power amplifier P5, the diode D4 that N pole is connected with the tie point of resistance R22 with voltage stabilizing didoe D3 after resistance R23 through resistance R24, and P pole is connected with the negative pole of electric capacity C16, the voltage stabilizing didoe D5 that N pole is connected with the tie point of resistance R24 with diode D4 forms, the base stage of described triode Q5 is connected with the positive pole of polar capacitor C13, and its emitter is connected with the emitter of triode Q6, and its collector electrode is connected with the negative input of power amplifier P4, the collector electrode of triode Q6 is connected with the negative input of power amplifier P5, and the electrode input end of power amplifier P5 is connected with the output of power amplifier P4, the positive pole of described polar capacitor C13 is connected with the output of power amplifier P3, and resistance R23 is then connected with the input of resistance R101 with the tie point of resistance R24.
2. virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system according to claim 1, it is characterized in that, described homophase AC signal amplifying circuit is by power amplifier P, one end is connected with the VCC pin of driving chip M, the resistance R7 that the other end is connected with the electrode input end of power amplifier P, one end is connected with the negative input of power amplifier P, the resistance R6 that the other end is connected with self-locking optical excitation circuit, and positive pole is connected with the electrode input end of power amplifier P, the polar capacitor C4 of negative pole external power supply forms, the output of described power amplifier P is connected with the INP pin of driving chip M.
3. virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system according to claim 2, it is characterized in that, described self-locking optical excitation circuit is by NOR gate IC1, NOR gate IC2, NOR gate IC3, the photocell CDS that one end is connected with the electrode input end of power amplifier P, the other end is connected with the negative input of power amplifier P2 after potentiometer R5, and the electric capacity C3 be serially connected between the electrode input end of NOR gate IC3 and output forms; The electrode input end of described NOR gate IC1 is connected with the tie point of potentiometer R5 with photocell CDS, and the output of its negative input AND OR NOT gate IC2 is connected, and the electrode input end of its output then AND OR NOT gate IC2 is connected; The output of described NOR gate IC2 then simultaneously the negative input of AND OR NOT gate IC3 be connected with the electrode input end of power amplifier P1, the output of the output of NOR gate IC3 then power amplifier P is connected; The output of the other end of described resistance R6 then AND OR NOT gate IC2 is connected.
4. virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system according to claim 3, it is characterized in that, described boostrap circuit is by field effect transistor MOS, one end is connected with the source electrode of field effect transistor MOS, the resistance R4 of other end ground connection, negative pole is connected with the grid of field effect transistor MOS, the polar capacitor C1 that positive pole is connected with the drain electrode of field effect transistor MOS after resistance R1, the resistance R2 be in parallel with polar capacitor C1, positive pole is connected with the positive pole of polar capacitor C1, the polar capacitor C2 that the negative input of negative pole AND OR NOT gate IC2 is connected, and one end is connected with the positive pole of polar capacitor C2, the resistance R3 of other end ground connection forms, the drain electrode of described field effect transistor MOS is connected with the tie point of resistance R7 with photocell CDS.
5. the virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system according to any one of Claims 1 to 4, it is characterized in that, described drive circuit is by transformer T, be serially connected with the diode D1 between the VCC pin of driving chip M and BOOST pin, be serially connected with the electric capacity C5 between the BOOST pin of driving chip M and TG pin, be serially connected with the resistance R8 between the TG pin of driving chip M and TS pin, and base stage is connected with the TG pin of driving chip M, collector electrode is ground connection after electric capacity C6 and electric capacity C7 in turn, and the transistor Q1 of grounded emitter forms, the Same Name of Ends of the primary coil of described transformer T is connected with the tie point of electric capacity C7 with electric capacity C6, ground connection after its non-same polarity is then connected with the emitter of transistor Q1, meanwhile, the emitter of transistor Q1 is also connected with the TS pin of driving chip M, and the secondary coil of described transformer T is provided with tap Y1 and tap Y2.
6. virtual protection emitter-base bandgap grading manifold type three filter and amplification mixed type raster data model system according to claim 5, it is characterized in that, described driving chip M is LTC4440A integrated chip.
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| CN201510324034.0A CN104968081A (en) | 2014-11-28 | 2015-06-12 | Logic protection emitter coupling-type three-filtering hybrid grid drive system |
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| CN201410714382.4A CN104410251A (en) | 2014-11-28 | 2014-11-28 | Hybrid gate drive system based on logic protection emitter-coupled amplifying circuit |
| CN2014107143824 | 2014-11-28 | ||
| CN201510324034.0A CN104968081A (en) | 2014-11-28 | 2015-06-12 | Logic protection emitter coupling-type three-filtering hybrid grid drive system |
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