CN204335031U - A kind of logic control system of the virtual protection amplifying type based on source follower - Google Patents
A kind of logic control system of the virtual protection amplifying type based on source follower Download PDFInfo
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- CN204335031U CN204335031U CN201420727076.XU CN201420727076U CN204335031U CN 204335031 U CN204335031 U CN 204335031U CN 201420727076 U CN201420727076 U CN 201420727076U CN 204335031 U CN204335031 U CN 204335031U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
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- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The utility model discloses a kind of logic control system of the virtual protection amplifying type based on source follower, primarily of field effect transistor MOS, NOR gate circuit, not gate IC1, not gate IC3, not gate IC4, the not gate IC2 that the output of input NAND gate IC1 is connected, the first-level filtering wave circuit that the input of NAND gate IC1 is connected, the input of NAND gate IC3 is connected secondary filter circuit, one end is connected with the grid of field effect transistor MOS, the resistance R3 that the output of other end NAND gate IC1 is connected, one end is connected with the grid of field effect transistor MOS, the compositions such as the resistance R5 that the other end is connected with NOR gate circuit.Overall structure of the present utility model is simple, and it makes and very easy to use.Meanwhile, the utility model adopts logic electronic components to realize its logic control function completely, and therefore its energy consumption is very low, fast operation.
Description
Technical field
The utility model relates to a kind of logic control circuit, specifically refers to a kind of logic control system of the virtual protection amplifying type based on source follower.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, its needs are driven by special drive circuit, have therefore just occurred the protection system for preventing drive system from disturbing from inner or outside unfavorable factor miscellaneous on the market.
Logic control circuit is an important control section in LED protection system, and whether the speed of its speed of service and stable performance directly determine the scope of application and the performance quality of LED protection system.But the structure of these logic control circuits is all comparatively complicated at present, and not only its energy consumption is higher, and its speed of service is comparatively slow, well can not embody the advantage of quick, the low energy consumption of logic control.
Utility model content
The purpose of this utility model is to overcome the logic control circuit complex structure of current LED protection system, energy consumption is higher, the speed of service is slower defect, provides a kind of logic control system of the virtual protection amplifying type based on source follower.
The purpose of this utility model is achieved through the following technical solutions: a kind of logic control system of the virtual protection amplifying type based on source follower, primarily of field effect transistor MOS, NOR gate circuit, not gate IC1, not gate IC3, not gate IC4, the not gate IC2 that the output of input NAND gate IC1 is connected, the first-level filtering wave circuit that the input of NAND gate IC1 is connected, the input of NAND gate IC3 is connected secondary filter circuit, one end is connected with the grid of field effect transistor MOS, the resistance R3 that the output of other end NAND gate IC1 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R5 that the other end is connected with NOR gate circuit, positive pole is connected with the grid of field effect transistor MOS, the electric capacity C3 that the output of its negative pole NAND gate IC3 is connected, and one end is connected with the drain electrode of field effect transistor MOS, the resistance R9 of other end ground connection forms.
Meanwhile, the output of described not gate IC2 is connected with switch power amplifying circuit after diode D3 through resistance R7 in turn, and described not gate IC4 is all connected with this switch power amplifying circuit with the output of NOR gate circuit, and virtual protection amplifying circuit is also serially connected with between the output and switch power amplifying circuit of not gate IC4, described switch power amplifying circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R8 between the output of power amplifier P1 and negative input and electric capacity C8, be serially connected in the resistance R10 between the output of power amplifier P2 and electrode input end and electric capacity C9, base stage is connected with the output of power amplifier P1, the triode Q2 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, base stage is connected with the emitter of triode Q2, the triode Q3 that collector electrode is connected with the negative input of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R13, the triode Q1 that collector electrode is connected with the base stage of triode Q3 after resistance R16, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q3 and the electric capacity C10 of ground connection, the electric capacity C11 be in parallel with resistance R13, one end is connected with the base stage of triode Q1, the resistance R14 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q1, the resistance R15 of the external-4V voltage of the other end, the electric capacity C12 be in parallel with resistance R15, and N pole is connected with the collector electrode of triode Q2, the diode D5 of the extremely external-4V voltage of P forms, the electrode input end of described power amplifier P1 is connected with the N pole of diode D3, and the output of described NOR gate circuit is then connected with the negative input of power amplifier P2.
Described virtual protection amplifying circuit is primarily of power amplifier P4, power amplifier P5, NAND gate IC6, NAND gate IC7, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C13 that positive pole is connected with the negative input of NAND gate IC7 after resistance R20, one end is connected with the negative input of NAND gate IC6, the resistance R17 that the other end is connected with the electrode input end of power amplifier P4, be serially connected in the resistance R18 between the negative input of power amplifier P4 and output, one end is connected with the output of NAND gate IC6, the resistance R19 that the other end is connected with the negative input of power amplifier P5, be serially connected in the polar capacitor C14 between the electrode input end of power amplifier P5 and output, positive pole is connected with the output of NAND gate IC7, negative pole is in turn through electric capacity C15 that voltage stabilizing didoe D6 is connected with the output of power amplifier P4 after resistance R21, P pole is connected with the output of power amplifier P5, N pole is in turn through diode D7 that resistance R23 is connected with the tie point of resistance R21 with voltage stabilizing didoe D6 after resistance R22, and N pole is connected with the negative pole of electric capacity C15, the voltage stabilizing didoe D8 that P pole is connected with the tie point of resistance R23 with diode D7 forms, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P4, the electrode input end of the output NAND gate IC7 of power amplifier P5 is connected, and its electrode input end is then connected with the output of power amplifier P4, the output of the positive pole of described polar capacitor C13 then NAND gate IC4 is connected, and resistance R22 is then connected with the electrode input end of power amplifier P2 with the negative input of power amplifier P1 respectively with the tie point of resistance R23.
The diode D1 that described first-level filtering wave circuit is connected by the input of P pole NAND gate IC1, N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1, and form with the resistance R1 that diode D1 is in parallel; The minus earth of described electric capacity C1.
Described NOR gate circuit is by XOR gate IC5, the diode D4 that N pole is connected with the first input end of XOR gate IC5, P pole is connected with secondary filter circuit, one end is connected with the P pole of diode D4, the resistance R6 of the external+12V voltage of the other end, and positive pole is connected with the P pole of diode D4, the electric capacity C4 of minus earth forms; Second input of described XOR gate IC5 is connected with the electrode input end of power amplifier P1, and the output of XOR gate IC5 is then connected with the negative input of power amplifier P2.
The diode D2 that described secondary filter circuit is connected by the input of N pole NAND gate IC3, P pole is connected with the P pole of diode D4, the resistance R4 be in parallel with diode D2, and the input of positive pole NAND gate IC3 is connected, the electric capacity C2 of minus earth forms.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) overall structure of the present utility model is simple, and it makes and very easy to use.
(2) the utility model adopts logic electronic components to realize its logic control function completely, and therefore its energy consumption is very low, fast operation.
(3) the utility model adopts source follower to be used as control switch, and therefore its performance is more stable, and its dynamic range is better.
(4) the utility model have employed switch power amplifying circuit and is used as power amplifying segments, and therefore performance is more stable, and sensitivity is higher.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Fig. 2 is virtual protection amplification circuit structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, the utility model forms primarily of field effect transistor MOS, not gate IC1, not gate IC3, not gate IC4, first-level filtering wave circuit, secondary filter circuit, NOR gate circuit, resistance R3, resistance R5, resistance R7, resistance R9, electric capacity C3, diode D3, switch power amplifying circuit and virtual protection amplifying circuit.During connection, the output of the input NAND gate IC1 of not gate IC2 is connected, and namely not gate IC1 is connected in series with not gate IC2 phase.Meanwhile, this first-level filtering wave circuit wants the input of NAND gate IC1 to be connected, and the input of secondary filter circuit then NAND gate IC3 is connected.
Wherein, described switch power amplifying circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, triode Q1, triode Q2, triode Q3, be serially connected in the one-level RC filter circuit between the output of power amplifier P1 and negative input, be serially connected in the secondary RC filter circuit between the output of power amplifier P2 and electrode input end, and resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, electric capacity C10, electric capacity C11, electric capacity C12 and diode D5 form.
Described one-level RC filtered electrical routing resistance R8 and electric capacity C8 is formed in parallel, namely between resistance R8 and the electric capacity C8 negative input that is all serially connected in power amplifier P1 and output; Described secondary RC filter circuit is then formed in parallel by resistance R10 and electric capacity C9, namely between resistance R10 and the electric capacity C9 electrode input end that is all serially connected in power amplifier P2 and output.Meanwhile, the negative input of power amplifier P1 is also connected with the electrode input end of power amplifier P2.
The base stage of triode Q2 is connected with the output of power amplifier P1, and its collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, and its emitter is then connected with the base stage of triode Q3; The collector electrode of triode Q3 is connected with the negative input of power amplifier P3 after resistance R12, meanwhile, and the collector electrode also external+10V voltage of this triode Q3.
The base stage of triode Q1 is connected with the output of power amplifier P2 after resistance R13, and its collector electrode is then connected with the base stage of triode Q3 after resistance R16.Electric capacity C11 is then in parallel with resistance R13, and for guaranteeing effect, this electric capacity C11 preferentially adopts electrochemical capacitor to realize.During connection, the negative pole of electric capacity C11 is connected with the base stage of triode Q1, and its positive pole is then connected with the output of power amplifier P2.The positive pole of electric capacity C10 is connected with the negative input of power amplifier P3, and its negative pole is then connected with the emitter of triode Q3.Meanwhile, the negative pole of this electric capacity C10 and the equal ground connection of emitter of triode Q3.
One end of resistance R14 is connected with the base stage of triode Q1, the voltage of the external-4V of its other end; And one end of resistance R15 is connected with the emitter of triode Q1, the voltage of its other end then external equally-4V.Electric capacity C12 is then in parallel with resistance R15.Equally, described electric capacity C10 and electric capacity C12 also all adopts electrochemical capacitor to realize.
The N pole of described diode D5 is connected with the collector electrode of triode Q2, and its P pole is at the voltage of external-4V.Meanwhile, the output of this power amplifier P3 will be connected with the TD pin of driving chip M.
For guaranteeing the normal operation of power amplifier P1 and power amplifier P2, this electric capacity C8 and electric capacity C9 all preferentially adopts patch capacitor to realize.And the resistance of resistance R8, resistance R10 is 10 K Ω, the resistance of resistance R11, resistance R12, resistance R13, resistance R14, resistance R15 and resistance R16 is 20 K Ω.
Described one end of resistance R3 is connected with the grid of field effect transistor MOS, and the output of its other end NAND gate IC1 is connected; One end of resistance R5 is connected with the grid of field effect transistor MOS, and its other end is connected with NOR gate circuit; The positive pole of electric capacity C3 is connected with the grid of field effect transistor MOS, and the output of its negative pole NAND gate IC3 is connected; One end of resistance R9 is connected with the drain electrode of field effect transistor MOS, other end ground connection.Meanwhile, the source electrode of this field effect transistor MOS needs then external+12V voltage, to guarantee that field effect transistor MOS can normally work.The drain electrode of described field effect transistor MOS wants the input of NAND gate IC4 to be connected.
Described first-level filtering wave circuit is made up of diode D1, resistance R1, resistance R2 and electric capacity C1, and wherein, the input of the P pole NAND gate IC1 of diode D1 is connected, and its N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1.Resistance R1 is then in parallel with diode D1, and the minus earth of electric capacity C1.
Described NOR gate circuit is by XOR gate IC5, and diode D4, resistance R6 and electric capacity C4 form, and during connection, the N pole of diode D4 is connected with the first input end of XOR gate IC5, and its P pole is connected with secondary filter circuit; Resistance R6 is divider resistance, and its one end is connected with the P pole of diode D4, the external+12V voltage of its other end; The positive pole of electric capacity C4 is connected with the P pole of diode D4, its minus earth.
Meanwhile, second input of XOR gate IC5 is connected with the electrode input end of power amplifier P1 with the N pole of diode D3 respectively, and the output of XOR gate IC5 then will be connected with the negative input of power amplifier P2.
Described secondary filter circuit is made up of diode D2, resistance R4 and electric capacity C2, and wherein, the input of the N pole NAND gate IC3 of diode D2 is connected, and its P pole is connected with the P pole of diode D4; Resistance R4 and diode D2 is in parallel, and the input of the positive pole NAND gate IC3 of electric capacity C2 is connected, its minus earth.
The structure of described virtual protection amplifying circuit as shown in Figure 2, namely this virtual protection amplifying circuit is primarily of power amplifier P4, power amplifier P5, NAND gate IC6, NAND gate IC7, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C13 that positive pole is connected with the negative input of NAND gate IC7 after resistance R20, one end is connected with the negative input of NAND gate IC6, the resistance R17 that the other end is connected with the electrode input end of power amplifier P4, be serially connected in the resistance R18 between the negative input of power amplifier P4 and output, one end is connected with the output of NAND gate IC6, the resistance R19 that the other end is connected with the negative input of power amplifier P5, be serially connected in the polar capacitor C14 between the electrode input end of power amplifier P5 and output, positive pole is connected with the output of NAND gate IC7, negative pole is in turn through electric capacity C15 that voltage stabilizing didoe D6 is connected with the output of power amplifier P4 after resistance R21, P pole is connected with the output of power amplifier P5, N pole is in turn through diode D7 that resistance R23 is connected with the tie point of resistance R21 with voltage stabilizing didoe D6 after resistance R22, and N pole is connected with the negative pole of electric capacity C15, the voltage stabilizing didoe D8 that P pole is connected with the tie point of resistance R23 with diode D7 forms.
Meanwhile, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P4; The electrode input end of the output NAND gate IC7 of power amplifier P5 is connected, and its electrode input end is then connected with the output of power amplifier P4.
The positive pole of described polar capacitor C13 wants the output of NAND gate IC4 to be connected, and resistance R22 is then connected with the electrode input end of power amplifier P2 with the negative input of power amplifier P1 respectively with the tie point of resistance R23.
As mentioned above, just the utility model can well be realized.
Claims (4)
1. the logic control system based on the virtual protection amplifying type of source follower, primarily of field effect transistor MOS, NOR gate circuit, not gate IC1, not gate IC3, not gate IC4, the not gate IC2 that the output of input NAND gate IC1 is connected, the first-level filtering wave circuit that the input of NAND gate IC1 is connected, the input of NAND gate IC3 is connected secondary filter circuit, one end is connected with the grid of field effect transistor MOS, the resistance R3 that the output of other end NAND gate IC1 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R5 that the other end is connected with NOR gate circuit, positive pole is connected with the grid of field effect transistor MOS, the electric capacity C3 that the output of its negative pole NAND gate IC3 is connected, and one end is connected with the drain electrode of field effect transistor MOS, the resistance R9 of other end ground connection forms, it is characterized in that, the output of described not gate IC2 is connected with switch power amplifying circuit after diode D3 through resistance R7 in turn, described not gate IC4 is all connected with this switch power amplifying circuit with the output of NOR gate circuit, meanwhile, between the output and switch power amplifying circuit of not gate IC4, virtual protection amplifying circuit is also serially connected with, described switch power amplifying circuit is primarily of power amplifier P1, power amplifier P2, power amplifier P3, be serially connected in the resistance R8 between the output of power amplifier P1 and negative input and electric capacity C8, be serially connected in the resistance R10 between the output of power amplifier P2 and electrode input end and electric capacity C9, base stage is connected with the output of power amplifier P1, the triode Q2 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R11, base stage is connected with the emitter of triode Q2, the triode Q3 that collector electrode is connected with the negative input of power amplifier P3 after resistance R12, base stage is connected with the output of power amplifier P2 after resistance R13, the triode Q1 that collector electrode is connected with the base stage of triode Q3 after resistance R16, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q3 and the electric capacity C10 of ground connection, the electric capacity C11 be in parallel with resistance R13, one end is connected with the base stage of triode Q1, the resistance R14 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q1, the resistance R15 of the external-4V voltage of the other end, the electric capacity C12 be in parallel with resistance R15, and N pole is connected with the collector electrode of triode Q2, the diode D5 of the extremely external-4V voltage of P forms, the electrode input end of described power amplifier P1 is connected with the N pole of diode D3, and the output of described NOR gate circuit is then connected with the negative input of power amplifier P2,
Described virtual protection amplifying circuit is primarily of power amplifier P4, power amplifier P5, NAND gate IC6, NAND gate IC7, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C13 that positive pole is connected with the negative input of NAND gate IC7 after resistance R20, one end is connected with the negative input of NAND gate IC6, the resistance R17 that the other end is connected with the electrode input end of power amplifier P4, be serially connected in the resistance R18 between the negative input of power amplifier P4 and output, one end is connected with the output of NAND gate IC6, the resistance R19 that the other end is connected with the negative input of power amplifier P5, be serially connected in the polar capacitor C14 between the electrode input end of power amplifier P5 and output, positive pole is connected with the output of NAND gate IC7, negative pole is in turn through electric capacity C15 that voltage stabilizing didoe D6 is connected with the output of power amplifier P4 after resistance R21, P pole is connected with the output of power amplifier P5, N pole is in turn through diode D7 that resistance R23 is connected with the tie point of resistance R21 with voltage stabilizing didoe D6 after resistance R22, and N pole is connected with the negative pole of electric capacity C15, the voltage stabilizing didoe D8 that P pole is connected with the tie point of resistance R23 with diode D7 forms, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P4, the electrode input end of the output NAND gate IC7 of power amplifier P5 is connected, and its electrode input end is then connected with the output of power amplifier P4, the output of the positive pole of described polar capacitor C13 then NAND gate IC4 is connected, and resistance R22 is then connected with the electrode input end of power amplifier P2 with the negative input of power amplifier P1 respectively with the tie point of resistance R23.
2. the logic control system of a kind of virtual protection amplifying type based on source follower according to claim 1, it is characterized in that, the diode D1 that described first-level filtering wave circuit is connected by the input of P pole NAND gate IC1, N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1, and form with the resistance R1 that diode D1 is in parallel; The minus earth of described electric capacity C1.
3. the logic control system of a kind of virtual protection amplifying type based on source follower according to claim 2, it is characterized in that, described NOR gate circuit is by XOR gate IC5, the diode D4 that N pole is connected with the first input end of XOR gate IC5, P pole is connected with secondary filter circuit, one end is connected with the P pole of diode D4, the resistance R6 of the external+12V voltage of the other end, and positive pole is connected with the P pole of diode D4, the electric capacity C4 of minus earth forms; Second input of described XOR gate IC5 is connected with the electrode input end of power amplifier P1, and the output of XOR gate IC5 is then connected with the negative input of power amplifier P2.
4. the logic control system of a kind of virtual protection amplifying type based on source follower according to claim 3; it is characterized in that; the diode D2 that described secondary filter circuit is connected by the input of N pole NAND gate IC3, P pole is connected with the P pole of diode D4; the resistance R4 be in parallel with diode D2, and the input of positive pole NAND gate IC3 is connected, the electric capacity C2 of minus earth forms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420727076.XU CN204335031U (en) | 2014-11-27 | 2014-11-27 | A kind of logic control system of the virtual protection amplifying type based on source follower |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420727076.XU CN204335031U (en) | 2014-11-27 | 2014-11-27 | A kind of logic control system of the virtual protection amplifying type based on source follower |
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| CN204335031U true CN204335031U (en) | 2015-05-13 |
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| CN201420727076.XU Expired - Fee Related CN204335031U (en) | 2014-11-27 | 2014-11-27 | A kind of logic control system of the virtual protection amplifying type based on source follower |
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| CN (1) | CN204335031U (en) |
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Effective date of registration: 20151224 Address after: 528400 No. 102 and No. 109, Pioneer Building, Torch Development Zone, Guangdong, Zhongshan Patentee after: Zhongshan Xingguangda Electronic Science & Technology Co., Ltd. Address before: 610000, 8 South Street, Chengdu hi tech Zone, Sichuan Patentee before: Chengdu Cuopu Technology Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
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Granted publication date: 20150513 Termination date: 20161127 |