CN204335034U - A kind of Novel LED light protection system logic control system - Google Patents
A kind of Novel LED light protection system logic control system Download PDFInfo
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- CN204335034U CN204335034U CN201420732597.4U CN201420732597U CN204335034U CN 204335034 U CN204335034 U CN 204335034U CN 201420732597 U CN201420732597 U CN 201420732597U CN 204335034 U CN204335034 U CN 204335034U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The utility model discloses a kind of Novel LED light protection system logic control system; primarily of NAND gate IC4; the not gate IC5 that input is connected with the output of NAND gate IC4; the not gate IC3 that output is connected with the negative input of NAND gate IC4; and the first logical links to be connected with the electrode input end of NAND gate IC4 and the second logical links form; it is characterized in that, between the output and the first logical links of not gate IC5, be also serially connected with virtual protection amplifying circuit.Overall structure of the present utility model is simple, and it makes and very easy to use.Meanwhile, the utility model adopts logic electronic components to realize its logic control function completely, and therefore its energy consumption is very low, fast operation.
Description
Technical field
The utility model relates to a kind of LED protection circuit, specifically refers to a kind of Novel LED light protection system logic control system.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, its needs are driven by special drive circuit, have therefore just occurred the protection system for preventing drive system from disturbing from inner or outside unfavorable factor miscellaneous on the market.
Logic control circuit is an important control section in LED protection system, and whether the speed of its speed of service and stable performance directly determine the scope of application and the performance quality of LED protection system.But the structure of these logic control circuits is all comparatively complicated at present, and not only its energy consumption is higher, and its speed of service is comparatively slow, well can not embody the advantage of quick, the low energy consumption of logic control.
Utility model content
The purpose of this utility model is to overcome the logic control circuit complex structure of current LED protection system, energy consumption is higher, the speed of service is slower defect, provides a kind of Novel LED light protection system logic control system.
The purpose of this utility model is achieved through the following technical solutions: a kind of Novel LED light protection system logic control system; primarily of NAND gate IC4; the not gate IC5 that input is connected with the output of NAND gate IC4; the not gate IC3 that output is connected with the negative input of NAND gate IC4, and the first logical links be connected with the electrode input end of NAND gate IC4 and the second logical links form.Meanwhile, between the output and the first logical links of not gate IC5, virtual protection amplifying circuit is also serially connected with, this virtual protection amplifying circuit is primarily of power amplifier P1, power amplifier P2, NAND gate IC6, NAND gate IC7, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C1 that positive pole is connected with the negative input of NAND gate IC7 after resistance R4, one end is connected with the negative input of NAND gate IC6, the resistance R1 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R2 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R3 that the other end is connected with the negative input of power amplifier P2, be serially connected in the polar capacitor C2 between the electrode input end of power amplifier P2 and output, positive pole is connected with the output of NAND gate IC7, negative pole is in turn through electric capacity C3 that voltage stabilizing didoe D7 is connected with the output of power amplifier P1 after resistance R5, P pole is connected with the output of power amplifier P2, N pole is in turn through diode D8 that resistance R7 is connected with the tie point of resistance R5 with voltage stabilizing didoe D7 after resistance R6, and N pole is connected with the negative pole of electric capacity C3, the voltage stabilizing didoe D9 that P pole is connected with the tie point of resistance R7 with diode D8 forms, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P1, the electrode input end of the output NAND gate IC7 of power amplifier P2 is connected, and its electrode input end is then connected with the output of power amplifier P1, the output of the positive pole NAND gate IC5 of described polar capacitor C1 is connected, and resistance R6 is then connected with the first logical links with the tie point of resistance R7.
Further, described first logical links is by not gate IC1, the not gate IC2 that the output of input NAND gate IC1 is connected, output is connected with the electrode input end of NAND gate IC4 in turn after resistance R11, diode D4, the filter delay circuit be connected with the electrode input end of NAND gate IC4, the input of P pole NAND gate IC1 is connected, N pole is in turn through diode D2 that the input of resistance R9 NAND gate IC1 after electric capacity C6 is connected, and form with the resistance R8 that diode D2 is in parallel, the tie point ground connection of described electric capacity C6 and resistance R9; The output of described not gate IC2 is then connected with the tie point of resistance R7 with resistance R6.
The second described logical links is by XOR gate IC6, the diode D5 that P pole is connected with the electrode input end of NAND gate IC4, N pole is connected with the first input end of XOR gate IC6, the diode D3 that the input of N pole NAND gate IC3 is connected, P pole is connected with the first input end of XOR gate IC6 after diode D6, the resistance R10 be in parallel with diode D3, and positive pole is connected with the N pole of diode D3, the electric capacity C7 of minus earth forms; The output of the second input NAND gate IC5 of described XOR gate IC6 is connected.
Described filter delay circuit is by electrochemical capacitor C8, and the resistance R12 be serially connected between the positive pole of electrochemical capacitor C8 and negative pole forms; The N pole of described diode D4 is then connected with the positive pole of this electrochemical capacitor C8.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) overall structure of the present utility model is simple, and it makes and very easy to use.
(2) the utility model adopts logic electronic components to realize its logic control function completely, and therefore its energy consumption is very low, fast operation.
(3) performance of the present utility model is highly stable, goes for different ambient temperatures.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Fig. 2 is virtual protection amplification circuit structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1; logic control circuit described in the utility model is by NAND gate IC4; the not gate IC5 that input is connected with the output of NAND gate IC4; the not gate IC3 that output is connected with the negative input of NAND gate IC4; the first logical links be connected with the electrode input end of NAND gate IC4 and the second logical links, and the virtual protection amplifying circuit be serially connected between the output of not gate IC5 and the first logical links forms.
Wherein, this first logical links is made up of not gate IC1, not gate IC2, resistance R11, diode D4, filter delay circuit, resistance R8, resistance R9, electric capacity C6 and diode D2.During connection, the output of the input NAND gate IC1 of not gate IC2 is connected, and its output is then connected with the electrode input end of NAND gate IC4 after diode D4 through resistance R11 in turn.Meanwhile, filter delay circuit will be connected with the electrode input end of NAND gate IC4.
The input of the P pole NAND gate IC1 of diode D2 is connected, its N pole is connected through the input of resistance R9 NAND gate IC1 after electric capacity C6 in turn, namely needs in turn to form an electric loop with the P pole of diode D2 after resistance R9 and electric capacity C6 from the N pole of diode D2.Resistance R8 is then in parallel with diode D2.Simultaneously; the tie point ground connection of described electric capacity C6 and resistance R9; the output of the output that the N pole of diode D2 needs to be formed an output CT1, not gate IC2 of the present utility model and virtual protection amplifying circuit then together with form the 3rd output CT3 of the present utility model.
Described filter delay circuit is by electrochemical capacitor C8, and the resistance R12 be serially connected between the positive pole of electrochemical capacitor C8 and negative pole forms, during connection, the N pole of diode D4 will be connected with the positive pole of this electrochemical capacitor C8, and namely the electrode input end of NAND gate IC4 will be connected with the positive pole of electrochemical capacitor C8.
The second described logical links is made up of XOR gate IC6, diode D5, diode D6, diode D3, resistance R10 and electric capacity C7.During connection, the P pole of diode D5 is connected with the electrode input end of NAND gate IC4, and its N pole is connected with the first input end of XOR gate IC6.The input of the N pole NAND gate IC3 of diode D3 is connected, and its P pole then forms second output CT2, resistance R10 of the present utility model and is then in parallel with diode D3.
The positive pole of electric capacity C7 is connected with the N pole of diode D3, its minus earth; The N pole of diode D6 is connected with the first input end of XOR gate IC6, and its P pole is then connected with the P pole of diode D3.Meanwhile, the output of the second input NAND gate IC5 of XOR gate IC6 is connected, and the output of XOR gate IC6 then forms the 4th output CT4 of the present utility model.
As shown in Figure 2, this virtual protection amplifying circuit is primarily of power amplifier P1, power amplifier P2, NAND gate IC6, NAND gate IC7, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C1 that positive pole is connected with the negative input of NAND gate IC7 after resistance R4, one end is connected with the negative input of NAND gate IC6, the resistance R1 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R2 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R3 that the other end is connected with the negative input of power amplifier P2, be serially connected in the polar capacitor C2 between the electrode input end of power amplifier P2 and output, positive pole is connected with the output of NAND gate IC7, negative pole is in turn through electric capacity C3 that voltage stabilizing didoe D7 is connected with the output of power amplifier P1 after resistance R5, P pole is connected with the output of power amplifier P2, N pole is in turn through diode D8 that resistance R7 is connected with the tie point of resistance R5 with voltage stabilizing didoe D7 after resistance R6, and N pole is connected with the negative pole of electric capacity C3, the voltage stabilizing didoe D9 that P pole is connected with the tie point of resistance R7 with diode D8 forms.
The electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P1; The electrode input end of the output NAND gate IC7 of power amplifier P2 is connected, and its electrode input end is then connected with the output of power amplifier P1.Meanwhile, the positive pole of described polar capacitor C1 needs the output of NAND gate IC5 to be connected, and resistance R6 then wants the output of NAND gate IC2 to be connected with the tie point of resistance R7.
As mentioned above, just the utility model can well be realized.
Claims (4)
1. a Novel LED light protection system logic control system, primarily of NAND gate IC4, the not gate IC5 that input is connected with the output of NAND gate IC4, the not gate IC3 that output is connected with the negative input of NAND gate IC4, and the first logical links to be connected with the electrode input end of NAND gate IC4 and the second logical links form, it is characterized in that, between the output and the first logical links of not gate IC5, be also serially connected with virtual protection amplifying circuit, this virtual protection amplifying circuit is primarily of power amplifier P1, power amplifier P2, NAND gate IC6, NAND gate IC7, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C1 that positive pole is connected with the negative input of NAND gate IC7 after resistance R4, one end is connected with the negative input of NAND gate IC6, the resistance R1 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R2 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R3 that the other end is connected with the negative input of power amplifier P2, be serially connected in the polar capacitor C2 between the electrode input end of power amplifier P2 and output, positive pole is connected with the output of NAND gate IC7, negative pole is in turn through electric capacity C3 that voltage stabilizing didoe D7 is connected with the output of power amplifier P1 after resistance R5, P pole is connected with the output of power amplifier P2, N pole is in turn through diode D8 that resistance R7 is connected with the tie point of resistance R5 with voltage stabilizing didoe D7 after resistance R6, and N pole is connected with the negative pole of electric capacity C3, the voltage stabilizing didoe D9 that P pole is connected with the tie point of resistance R7 with diode D8 forms, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P1, the electrode input end of the output NAND gate IC7 of power amplifier P2 is connected, and its electrode input end is then connected with the output of power amplifier P1, the output of the positive pole NAND gate IC5 of described polar capacitor C1 is connected, and resistance R6 is then connected with the first logical links with the tie point of resistance R7.
2. a kind of Novel LED light protection system logic control system according to claim 1, it is characterized in that, described first logical links is by not gate IC1, the output of input NAND gate IC1 is connected, output is in turn through resistance R11, the not gate IC2 be connected with the electrode input end of NAND gate IC4 after diode D4, the filter delay circuit be connected with the electrode input end of NAND gate IC4, the input of P pole NAND gate IC1 is connected, N pole is in turn through diode D2 that the input of resistance R9 NAND gate IC1 after electric capacity C6 is connected, and form with the resistance R8 that diode D2 is in parallel, the tie point ground connection of described electric capacity C6 and resistance R9, the output of described not gate IC2 is then connected with the tie point of resistance R7 with resistance R6.
3. a kind of Novel LED light protection system logic control system according to claim 2, it is characterized in that, the second described logical links is by XOR gate IC6, the diode D5 that P pole is connected with the electrode input end of NAND gate IC4, N pole is connected with the first input end of XOR gate IC6, the diode D3 that the input of N pole NAND gate IC3 is connected, P pole is connected with the first input end of XOR gate IC6 after diode D6, the resistance R10 be in parallel with diode D3, and positive pole is connected with the N pole of diode D3, the electric capacity C7 of minus earth forms; The output of the second input NAND gate IC5 of described XOR gate IC6 is connected.
4. a kind of Novel LED light protection system logic control system according to claim 3, is characterized in that, described filter delay circuit is by electrochemical capacitor C8, and the resistance R12 be serially connected between the positive pole of electrochemical capacitor C8 and negative pole forms; The N pole of described diode D4 is then connected with the positive pole of this electrochemical capacitor C8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420732597.4U CN204335034U (en) | 2014-11-27 | 2014-11-27 | A kind of Novel LED light protection system logic control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420732597.4U CN204335034U (en) | 2014-11-27 | 2014-11-27 | A kind of Novel LED light protection system logic control system |
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| Publication Number | Publication Date |
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| CN204335034U true CN204335034U (en) | 2015-05-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420732597.4U Expired - Fee Related CN204335034U (en) | 2014-11-27 | 2014-11-27 | A kind of Novel LED light protection system logic control system |
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| CN (1) | CN204335034U (en) |
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- 2014-11-27 CN CN201420732597.4U patent/CN204335034U/en not_active Expired - Fee Related
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI ZHENSHUN SMARTECH CORP. Free format text: FORMER OWNER: CHENGDU COPOO TECHNOLOGY CO., LTD. Effective date: 20150528 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 610000 CHENGDU, SICHUAN PROVINCE TO: 200070 ZHABEI, SHANGHAI |
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| TR01 | Transfer of patent right |
Effective date of registration: 20150528 Address after: 200070, 206 business building, 671 Hu Tai Road, Shanghai, Zhabei District Patentee after: Shanghai Zhen Shun intelligent Polytron Technologies Inc Address before: 610000, 8 South Street, Chengdu hi tech Zone, Sichuan Patentee before: Chengdu Cuopu Technology Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150513 Termination date: 20191127 |