CN104470112A - Control system based on logic protection emitter-coupled circuit and excitation type logic circuit - Google Patents
Control system based on logic protection emitter-coupled circuit and excitation type logic circuit Download PDFInfo
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- CN104470112A CN104470112A CN201410708102.9A CN201410708102A CN104470112A CN 104470112 A CN104470112 A CN 104470112A CN 201410708102 A CN201410708102 A CN 201410708102A CN 104470112 A CN104470112 A CN 104470112A
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Abstract
The invention discloses a control system based on a logic protection emitter-coupled circuit and an excitation type logic circuit. The control system based on the logic protection emitter-coupled circuit and the excitation type logic circuit is mainly composed of a field-effect transistor MOS, a NOT gate IC1, a NOT gate IC3, a NOT gate IC4, a NOT gate IC2, a filter delay circuit, a primary filter circuit, a secondary filter circuit and the like, wherein the input end of the NOT gate IC2 is connected with the output end of the NOT gate IC1, the filter delay circuit is connected with the output end of the NOT gate IC2, the primary filter circuit is connected with the input end of the NOT gate IC1, and the secondary filter circuit is connected with the input end of the NOT gate IC3. The control system based on the logic protection emitter-coupled circuit and the excitation type logic circuit is characterized in that a laser beam excitation type logic amplifying circuit is connected between a source electrode of the field-effect transistor MOS and the filter delay circuit in series, and a logic protection emitter-coupled amplifying circuit is connected in series between the source electrode of the field-effect transistor MOS and a resistor R3. The control system based on the logic protection emitter-coupled circuit and the excitation type logic circuit is simple in overall structure and quite convenient to manufacture and use; besides, the logic control function of the control system is achieved completely through logic electronic components, and therefore the control system is quite low in power consumption and high in operation speed.
Description
Technical field
The present invention relates to a kind of logic control circuit, specifically refer to the control system of a kind of logic-based protection emitter-coupled circuit and excitation formula logical circuit.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, its needs are driven by special drive circuit, have therefore just occurred the protection system for preventing drive system from disturbing from inner or outside unfavorable factor miscellaneous on the market.
Logic control circuit is an important control section in LED protection system, and whether the speed of its speed of service and stable performance directly determine the scope of application and the performance quality of LED protection system.But the structure of these logic control circuits is all comparatively complicated at present, and not only its energy consumption is higher, and its speed of service is comparatively slow, well can not embody the advantage of quick, the low energy consumption of logic control.
Summary of the invention
The object of the invention is to overcome the logic control circuit complex structure of current LED protection system, energy consumption is higher, the speed of service is slower defect, provide a kind of logic-based to protect the control system of emitter-coupled circuit and excitation formula logical circuit.
Object of the present invention is achieved through the following technical solutions: the control system of a kind of logic-based protection emitter-coupled circuit and excitation formula logical circuit, primarily of field effect transistor MOS, not gate IC1, not gate IC3, not gate IC4, the not gate IC2 that the output of input NAND gate IC1 is connected, the filter delay circuit that the output of NAND gate IC2 is connected, the first-level filtering wave circuit that the input of NAND gate IC1 is connected, the input of NAND gate IC3 is connected secondary filter circuit, the NOR gate circuit that the output of NAND gate IC4 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R3 that the output of other end NAND gate IC1 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R5 that the other end is connected with NOR gate circuit, positive pole is connected with the grid of field effect transistor MOS, the electric capacity C3 that the output of its negative pole NAND gate IC3 is connected, and one end is connected with the drain electrode of field effect transistor MOS, the resistance R9 of other end ground connection forms.
Meanwhile, between the source electrode of scene effect pipe MOS and filter delay circuit, be serially connected with beam excitation formula logic amplifying circuit, the source electrode of scene effect pipe MOS and the circuit of resistance R3 are then serially connected with virtual protection emitter-base bandgap grading manifold type amplifying circuit, this beam excitation formula logic amplifying circuit is primarily of power amplifier P1, NAND gate IC6, NAND gate IC7, NAND gate IC8, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C6, the resistance R10 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R10, the polar capacitor C8 that negative pole is connected with the source electrode of field effect transistor MOS, one end is connected with the negative input of NAND gate IC6, the resistance R11 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R12 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R13 that the other end is connected with the negative input of NAND gate IC8, positive pole is connected with the output of NAND gate IC7, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC8, and one end is connected with the positive pole of polar capacitor C8, the resistance R14 that the other end is connected with the negative input of NAND gate IC7 forms, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC7, and the electrode input end of NAND gate IC8 is connected with the output of power amplifier P1, the electrode input end of described power amplifier P1 is then connected with filter delay circuit, and the output of the negative input of NAND gate IC7 also NAND gate IC4 is connected.
Described virtual protection emitter-base bandgap grading manifold type amplifying circuit is primarily of triode Q1, triode Q2, power amplifier P2, power amplifier P3, be serially connected in the resistance R16 between the negative input of power amplifier P2 and output, be serially connected in the polar capacitor C11 between the electrode input end of power amplifier P3 and output, be serially connected in the resistance R15 between the electrode input end of power amplifier P2 and the collector electrode of triode Q1, be serially connected in the resistance R17 between the collector electrode of triode Q1 and the base stage of triode Q2, the electric capacity C10 be in parallel with resistance R17, negative pole is connected with the electrode input end of power amplifier P2, the polar capacitor C9 that positive pole is connected with the emitter of triode Q1 after resistance R18, be serially connected in the resistance R19 between the base stage of triode Q2 and the positive pole of polar capacitor C9, positive pole is connected with the emitter of triode Q2, negative pole is in turn through electric capacity C12 that voltage stabilizing didoe D7 is connected with the output of power amplifier P2 after resistance R20, P pole is connected with the output of power amplifier P3, the diode D8 that N pole is connected with the tie point of resistance R20 with voltage stabilizing didoe D7 after resistance R21 through resistance R22, and P pole is connected with the negative pole of electric capacity C12, the voltage stabilizing didoe D9 that N pole is connected with the tie point of resistance R22 with diode D8 forms, the base stage of described triode Q1 is connected with the positive pole of polar capacitor C9, and its emitter is connected with the emitter of triode Q2, and its collector electrode is connected with the negative input of power amplifier P2, the collector electrode of triode Q2 is connected with the negative input of power amplifier P3, and the electrode input end of power amplifier P3 is connected with the output of power amplifier P2, the described positive pole of polar capacitor C9 is connected with the grid of field effect transistor MOS, the tie point of resistance R22 and resistance R21 then after resistance R3 the output of NAND gate IC1 be connected.
Described filter delay circuit is made up of resistance R7, diode D3, electrochemical capacitor C5 and resistance R8, between the positive pole that described resistance R8 is serially connected in electrochemical capacitor C5 and negative pole, the output of one end NAND gate IC2 of resistance R7 is connected, its other end is connected with the positive pole of electrochemical capacitor C5 after diode D3; The electrode input end of described power amplifier P1 is then connected with the positive pole of electrochemical capacitor C5.
The diode D1 that described first-level filtering wave circuit is connected by the input of P pole NAND gate IC1, N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1, and form with the resistance R1 that diode D1 is in parallel; The minus earth of described electric capacity C1.
Described NOR gate circuit is by XOR gate IC5, the diode D4 that N pole is connected with the first input end of XOR gate IC5, P pole is connected with secondary filter circuit, one end is connected with the P pole of diode D4, the resistance R6 of the external+12V voltage of the other end, and positive pole is connected with the P pole of diode D4, the electric capacity C4 of minus earth forms; The output of the second input NAND gate IC4 of described XOR gate IC5 is connected, and the output of not gate IC4 is also connected with the output of NAND gate IC8.
The diode D2 that described secondary filter circuit is connected by the input of N pole NAND gate IC3, P pole is connected with the P pole of diode D4, the resistance R4 be in parallel with diode D2, and the input of positive pole NAND gate IC3 is connected, the electric capacity C2 of minus earth forms.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) overall structure of the present invention is simple, and it makes and very easy to use.
(2) the present invention adopts logic electronic components to realize its logic control function completely, and therefore its energy consumption is very low, fast operation.
(3) the present invention adopts source follower to be used as control switch, and therefore its performance is more stable, and its dynamic range is better.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Fig. 2 is virtual protection emitter-base bandgap grading manifold type amplification circuit structure schematic diagram of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, the present invention is primarily of field effect transistor MOS, not gate IC1, not gate IC3, not gate IC4, filter delay circuit, first-level filtering wave circuit, secondary filter circuit, NOR gate circuit, resistance R3, resistance R5, resistance R9, electric capacity C3, beam excitation formula logic amplifying circuit and virtual protection emitter-base bandgap grading manifold type amplifying circuit composition.
During connection, the input of not gate IC2 wants the output of NAND gate IC1 to be connected, and namely not gate IC1 is connected in series with not gate IC2 phase.Described filter delay circuit is made up of resistance R7, diode D3, electrochemical capacitor C5 and resistance R8, wherein, between the positive pole that resistance R8 is serially connected in electrochemical capacitor C5 and negative pole, and the output of one end NAND gate IC2 of resistance R7 is connected, its other end is connected with the positive pole of electrochemical capacitor C5 after diode D3.
Described first-level filtering wave circuit wants the input of NAND gate IC1 to be connected, and the input of secondary filter circuit then NAND gate IC3 is connected, and the output of NOR gate circuit NAND gate IC4 is connected.
One end of resistance R3 is connected with the grid of field effect transistor MOS, and the output of its other end NAND gate IC1 after virtual protection emitter-base bandgap grading manifold type amplifying circuit is connected; One end of resistance R5 is connected with the grid of field effect transistor MOS, and its other end is connected with NOR gate circuit; The positive pole of electric capacity C3 is connected with the grid of field effect transistor MOS, and the output of its negative pole NAND gate IC3 is connected; One end of resistance R9 is connected with the drain electrode of field effect transistor MOS, other end ground connection.
Described first-level filtering wave circuit is made up of diode D1, resistance R1, resistance R2 and electric capacity C1, and wherein, the input of the P pole NAND gate IC1 of diode D1 is connected, and its N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1.Resistance R1 is then in parallel with diode D1, and the minus earth of electric capacity C1.
Described NOR gate circuit is by XOR gate IC5, and diode D4, resistance R6 and electric capacity C4 form, and during connection, the N pole of diode D4 is connected with the first input end of XOR gate IC5, and its P pole is connected with secondary filter circuit; Resistance R6 is divider resistance, and its one end is connected with the P pole of diode D4, the external+12V voltage of its other end; The positive pole of electric capacity C4 is connected with the P pole of diode D4, its minus earth.Meanwhile, second input of XOR gate IC5 wants the output of NAND gate IC4 to be connected.
Described secondary filter circuit is made up of diode D2, resistance R4 and electric capacity C2, and wherein, the input of the N pole NAND gate IC3 of diode D2 is connected, and its P pole is connected with the P pole of diode D4; Resistance R4 and diode D2 is in parallel, and the input of the positive pole NAND gate IC3 of electric capacity C2 is connected, its minus earth.
Described beam excitation formula logic amplifying circuit is then primarily of power amplifier P1, NAND gate IC6, NAND gate IC7, NAND gate IC8, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C6, the resistance R10 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R10, the polar capacitor C8 that negative pole is connected with the source electrode of field effect transistor MOS, one end is connected with the negative input of NAND gate IC6, the resistance R11 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R12 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R13 that the other end is connected with the negative input of NAND gate IC8, positive pole is connected with the output of NAND gate IC7, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC8, and one end is connected with the positive pole of polar capacitor C8, the resistance R14 that the other end is connected with the negative input of NAND gate IC7 forms.
Meanwhile, the electrode input end of NAND gate IC6 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC7, and the electrode input end of NAND gate IC8 is connected with the output of power amplifier P1.
The electrode input end of described power amplifier P1 is connected with the positive pole of electrochemical capacitor C5, and the output of the negative input NAND gate IC4 of NAND gate IC7 is connected, and the negative pole of polar capacitor C8 is then connected with the source electrode of field effect transistor MOS.
The structure of described virtual protection emitter-base bandgap grading manifold type amplifying circuit as shown in Figure 2, it is primarily of triode Q1, triode Q2, power amplifier P2, power amplifier P3, be serially connected in the resistance R16 between the negative input of power amplifier P2 and output, be serially connected in the polar capacitor C11 between the electrode input end of power amplifier P3 and output, be serially connected in the resistance R15 between the electrode input end of power amplifier P2 and the collector electrode of triode Q1, be serially connected in the resistance R17 between the collector electrode of triode Q1 and the base stage of triode Q2, the electric capacity C10 be in parallel with resistance R17, negative pole is connected with the electrode input end of power amplifier P2, the polar capacitor C9 that positive pole is connected with the emitter of triode Q1 after resistance R18, be serially connected in the resistance R19 between the base stage of triode Q2 and the positive pole of polar capacitor C9, positive pole is connected with the emitter of triode Q2, negative pole is in turn through electric capacity C12 that voltage stabilizing didoe D7 is connected with the output of power amplifier P2 after resistance R20, P pole is connected with the output of power amplifier P3, the diode D8 that N pole is connected with the tie point of resistance R20 with voltage stabilizing didoe D7 after resistance R21 through resistance R22, and P pole is connected with the negative pole of electric capacity C12, the voltage stabilizing didoe D9 that N pole is connected with the tie point of resistance R22 with diode D8 forms.
Meanwhile, the base stage of described triode Q1 is connected with the positive pole of polar capacitor C9, and its emitter is connected with the emitter of triode Q2, and its collector electrode is connected with the negative input of power amplifier P2; The collector electrode of triode Q2 is connected with the negative input of power amplifier P3, and the electrode input end of power amplifier P3 is connected with the output of power amplifier P2.
During connection, the described positive pole of polar capacitor C9 is connected with the grid of field effect transistor MOS, the tie point of resistance R22 and resistance R21 then after resistance R3 the output of NAND gate IC1 be connected.
4 outputs are formed altogether, for being connected with other LED circuits of outside in the present invention.Wherein, first output CT1 is drawn by the N pole of diode D1 and is formed, second output is drawn by the P pole of diode D2 and is formed, 3rd output is jointly drawn by the output of not gate IC4 and the output of NAND gate IC8 and is formed, and the 4th output is then drawn by the output of XOR gate IC5 and formed.
As mentioned above, just the present invention can well be realized.
Claims (5)
1. the control system of a logic-based protection emitter-coupled circuit and excitation formula logical circuit, primarily of field effect transistor MOS, not gate IC1, not gate IC3, not gate IC4, the not gate IC2 that the output of input NAND gate IC1 is connected, the filter delay circuit that the output of NAND gate IC2 is connected, the first-level filtering wave circuit that the input of NAND gate IC1 is connected, the input of NAND gate IC3 is connected secondary filter circuit, the NOR gate circuit that the output of NAND gate IC4 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R3 that the output of other end NAND gate IC1 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R5 that the other end is connected with NOR gate circuit, positive pole is connected with the grid of field effect transistor MOS, the electric capacity C3 that the output of its negative pole NAND gate IC3 is connected, and one end is connected with the drain electrode of field effect transistor MOS, the resistance R9 of other end ground connection forms, it is characterized in that, beam excitation formula logic amplifying circuit is serially connected with between the source electrode of scene effect pipe MOS and filter delay circuit, the source electrode of scene effect pipe MOS and the circuit of resistance R3 are then serially connected with virtual protection emitter-base bandgap grading manifold type amplifying circuit, this beam excitation formula logic amplifying circuit is primarily of power amplifier P1, NAND gate IC6, NAND gate IC7, NAND gate IC8, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C6, the resistance R10 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R10, the polar capacitor C8 that negative pole is connected with the source electrode of field effect transistor MOS, one end is connected with the negative input of NAND gate IC6, the resistance R11 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R12 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R13 that the other end is connected with the negative input of NAND gate IC8, positive pole is connected with the output of NAND gate IC7, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC8, and one end is connected with the positive pole of polar capacitor C8, the resistance R14 that the other end is connected with the negative input of NAND gate IC7 forms, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC7, and the electrode input end of NAND gate IC8 is connected with the output of power amplifier P1, the electrode input end of described power amplifier P1 is then connected with filter delay circuit, and the output of the negative input of NAND gate IC7 also NAND gate IC4 is connected,
Described virtual protection emitter-base bandgap grading manifold type amplifying circuit is primarily of triode Q1, triode Q2, power amplifier P2, power amplifier P3, be serially connected in the resistance R16 between the negative input of power amplifier P2 and output, be serially connected in the polar capacitor C11 between the electrode input end of power amplifier P3 and output, be serially connected in the resistance R15 between the electrode input end of power amplifier P2 and the collector electrode of triode Q1, be serially connected in the resistance R17 between the collector electrode of triode Q1 and the base stage of triode Q2, the electric capacity C10 be in parallel with resistance R17, negative pole is connected with the electrode input end of power amplifier P2, the polar capacitor C9 that positive pole is connected with the emitter of triode Q1 after resistance R18, be serially connected in the resistance R19 between the base stage of triode Q2 and the positive pole of polar capacitor C9, positive pole is connected with the emitter of triode Q2, negative pole is in turn through electric capacity C12 that voltage stabilizing didoe D7 is connected with the output of power amplifier P2 after resistance R20, P pole is connected with the output of power amplifier P3, the diode D8 that N pole is connected with the tie point of resistance R20 with voltage stabilizing didoe D7 after resistance R21 through resistance R22, and P pole is connected with the negative pole of electric capacity C12, the voltage stabilizing didoe D9 that N pole is connected with the tie point of resistance R22 with diode D8 forms, the base stage of described triode Q1 is connected with the positive pole of polar capacitor C9, and its emitter is connected with the emitter of triode Q2, and its collector electrode is connected with the negative input of power amplifier P2, the collector electrode of triode Q2 is connected with the negative input of power amplifier P3, and the electrode input end of power amplifier P3 is connected with the output of power amplifier P2, the described positive pole of polar capacitor C9 is connected with the grid of field effect transistor MOS, the tie point of resistance R22 and resistance R21 then after resistance R3 the output of NAND gate IC1 be connected.
2. the control system of a kind of logic-based protection emitter-coupled circuit according to claim 1 and excitation formula logical circuit, it is characterized in that, described filter delay circuit is made up of resistance R7, diode D3, electrochemical capacitor C5 and resistance R8, between the positive pole that described resistance R8 is serially connected in electrochemical capacitor C5 and negative pole, the output of one end NAND gate IC2 of resistance R7 is connected, its other end is connected with the positive pole of electrochemical capacitor C5 after diode D3; The electrode input end of described power amplifier P1 is then connected with the positive pole of electrochemical capacitor C5.
3. the control system of a kind of logic-based protection emitter-coupled circuit according to claim 2 and excitation formula logical circuit, it is characterized in that, the diode D1 that described first-level filtering wave circuit is connected by the input of P pole NAND gate IC1, N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1, and form with the resistance R1 that diode D1 is in parallel; The minus earth of described electric capacity C1.
4. the control system of a kind of logic-based protection emitter-coupled circuit according to claim 3 and excitation formula logical circuit, it is characterized in that, described NOR gate circuit is by XOR gate IC5, the diode D4 that N pole is connected with the first input end of XOR gate IC5, P pole is connected with secondary filter circuit, one end is connected with the P pole of diode D4, the resistance R6 of the external+12V voltage of the other end, and positive pole is connected with the P pole of diode D4, the electric capacity C4 of minus earth forms; The output of the second input NAND gate IC4 of described XOR gate IC5 is connected, and the output of not gate IC4 is also connected with the output of NAND gate IC8.
5. the control system of a kind of logic-based protection emitter-coupled circuit according to claim 4 and excitation formula logical circuit; it is characterized in that; the diode D2 that described secondary filter circuit is connected by the input of N pole NAND gate IC3, P pole is connected with the P pole of diode D4; the resistance R4 be in parallel with diode D2, and the input of positive pole NAND gate IC3 is connected, the electric capacity C2 of minus earth forms.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410708102.9A CN104470112A (en) | 2014-11-28 | 2014-11-28 | Control system based on logic protection emitter-coupled circuit and excitation type logic circuit |
| CN201510324162.5A CN104968086A (en) | 2014-11-28 | 2015-06-12 | Filtering control system based on logic protection emitter coupled excitation type logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410708102.9A CN104470112A (en) | 2014-11-28 | 2014-11-28 | Control system based on logic protection emitter-coupled circuit and excitation type logic circuit |
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| CN104470112A true CN104470112A (en) | 2015-03-25 |
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| CN201410708102.9A Pending CN104470112A (en) | 2014-11-28 | 2014-11-28 | Control system based on logic protection emitter-coupled circuit and excitation type logic circuit |
| CN201510324162.5A Pending CN104968086A (en) | 2014-11-28 | 2015-06-12 | Filtering control system based on logic protection emitter coupled excitation type logic circuit |
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| CN201510324162.5A Pending CN104968086A (en) | 2014-11-28 | 2015-06-12 | Filtering control system based on logic protection emitter coupled excitation type logic circuit |
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| CN (2) | CN104470112A (en) |
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- 2014-11-28 CN CN201410708102.9A patent/CN104470112A/en active Pending
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Application publication date: 20150325 |