CN104837288A - Excitation type logic control system based on gate drive - Google Patents
Excitation type logic control system based on gate drive Download PDFInfo
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Abstract
The invention discloses an excitation type logic control system based on a gate drive; the excitation type logic control system mainly comprises a field effect transistor MOS, a NOT gate IC1, a NOT gate IC3, a NOT gate IC4, a NOT gate IC2, a filter delay circuit, a first level filter circuit connected with an input end of the NOT gate IC1, a second level filter circuit connected with an input end of the NOT gate IC3, a XOR gate circuit connected with an output end of the NOT gate IC4, a resistor R3 with one end connected with a grid electrode of the field effect transistor MOS and the other end connected with an output end of the NOT gate IC1, a resistor R5 with one end connected with the grid electrode of the field effect transistor MOS and the other end connected with XOR gate circuit, and a capacitor C3 with an anode connected with the grid electrode of the field effect transistor MOS and a cathode connected with an output end of the NOT gate IC3. The excitation type logic control system is driven by a gate drive circuit, thus greatly improving reaction speed, and better protecting an LED lamp.
Description
Technical field
The present invention relates to a kind of logic control circuit, specifically refer to a kind of excitation formula logic control system based on gate-drive.
Background technology
At present, because LED has, energy consumption is low, the feature such as long service life and safety and environmental protection, and it has become one of main product of people's life lighting.Because LED is different from traditional incandescent lamp, its needs are driven by special drive circuit, have therefore just occurred the protection system for preventing drive system from disturbing from inner or outside unfavorable factor miscellaneous on the market.
Logic control circuit is an important control section in LED protection system, and whether the speed of its speed of service and stable performance directly determine the scope of application and the performance quality of LED protection system.But the structure of these logic control circuits is all comparatively complicated at present, and reaction speed is comparatively slow, can not well protect LED.
Summary of the invention
The object of the invention is to overcome the logic control circuit complex structure of current LED protection system and the slower defect of reaction speed, a kind of excitation formula logic control system based on gate-drive is provided.
Object of the present invention is achieved through the following technical solutions: a kind of excitation formula logic control system based on gate-drive, it is by field effect transistor MOS, not gate IC1, not gate IC3, not gate IC4, the not gate IC2 that the output of input NAND gate IC1 is connected, the filter delay circuit that the output of NAND gate IC2 is connected, the first-level filtering wave circuit that the input of NAND gate IC1 is connected, the input of NAND gate IC3 is connected secondary filter circuit, the NOR gate circuit that the output of NAND gate IC4 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R3 that the output of other end NAND gate IC1 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R5 that the other end is connected with NOR gate circuit, positive pole is connected with the grid of field effect transistor MOS, the electric capacity C3 that the output of its negative pole NAND gate IC3 is connected, one end is connected with the drain electrode of field effect transistor MOS, the resistance R9 of other end ground connection, be serially connected in the beam excitation formula logic amplifying circuit between the source electrode of field effect transistor MOS and filter delay circuit, and the gate drive circuit be arranged between the grid of field effect transistor MOS and the input of secondary filter circuit forms.
Further, described gate drive circuit is by triode Q1, triode Q2, field effect transistor MOS1, unidirectional thyristor D8, negative pole is connected with the base stage of triode Q2, the electric capacity C9 that positive pole is connected with the emitter of triode Q2 after resistance R16, the resistance R17 be in parallel with electric capacity C9, one end is connected with the collector electrode of triode Q1, the resistance R15 that the other end is then connected with the positive pole of electric capacity C9, be serially connected in the resistance R18 between the collector electrode of triode Q1 and base stage, N pole is connected with the collector electrode of triode Q2, the diode D7 that P pole is then connected with the grid of field effect transistor MOS1 after resistance R19, positive pole is connected with the emitter of triode Q2, the electric capacity C10 that negative pole is then connected with the grid of field effect transistor MOS1 after resistance R20, positive pole is connected with the negative pole of electric capacity C10, the electric capacity C11 that negative pole is then connected with the P pole of unidirectional thyristor D8, and positive pole is connected with the control pole of unidirectional thyristor D8, the electric capacity C12 that negative pole is then connected with the grid of field effect transistor MOS forms, the base stage of described triode Q1 is connected with the collector electrode of triode Q2, its emitter is then connected with the P pole of diode D7, the emitter of triode Q2 is connected with secondary filter circuit, grounded drain, its source electrode of described field effect transistor MOS1 are then connected with the N pole of unidirectional thyristor D8.
Described beam excitation formula logic amplifying circuit is by power amplifier P1, NAND gate IC6, NAND gate IC7, NAND gate IC8, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C6, the resistance R10 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R10, the polar capacitor C8 that negative pole is connected with the source electrode of field effect transistor MOS, one end is connected with the negative input of NAND gate IC6, the resistance R11 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R12 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R13 that the other end is connected with the negative input of NAND gate IC8, positive pole is connected with the output of NAND gate IC7, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC8, and one end is connected with the positive pole of polar capacitor C8, the resistance R14 that the other end is connected with the negative input of NAND gate IC7 forms, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC7, and the electrode input end of NAND gate IC8 is connected with the output of power amplifier P1, the electrode input end of described power amplifier P1 is then connected with filter delay circuit, and the output of the negative input of NAND gate IC7 also NAND gate IC4 is connected.
Described filter delay circuit is made up of resistance R7, diode D3, electrochemical capacitor C5 and resistance R8, between the positive pole that described resistance R8 is serially connected in electrochemical capacitor C5 and negative pole, the output of one end NAND gate IC2 of resistance R7 is connected, its other end is connected with the positive pole of electrochemical capacitor C5 after diode D3; The electrode input end of described power amplifier P1 is then connected with the positive pole of electrochemical capacitor C5.
The diode D1 that described first-level filtering wave circuit is connected by the input of P pole NAND gate IC1, N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1, and form with the resistance R1 that diode D1 is in parallel; The minus earth of described electric capacity C1, the N pole of diode D1 is then as the input of this first-level filtering wave circuit.
Described NOR gate circuit is by XOR gate IC5, the diode D4 that N pole is connected with the first input end of XOR gate IC5, P pole is connected with secondary filter circuit, one end is connected with the P pole of diode D4, the resistance R6 of the external+12V voltage of the other end, and positive pole is connected with the P pole of diode D4, the electric capacity C4 of minus earth forms; The output of the second input NAND gate IC4 of described XOR gate IC5 is connected, and the output of not gate IC4 is also connected with the output of NAND gate IC8.
The diode D2 that described secondary filter circuit is connected by the input of N pole NAND gate IC3, P pole is connected with the P pole of diode D4, the resistance R4 be in parallel with diode D2, and the input of positive pole NAND gate IC3 is connected, the electric capacity C2 of minus earth forms; The P pole of described diode D2 is also connected with the emitter of triode Q2.
The present invention comparatively prior art compares, and has the following advantages and beneficial effect:
(1) overall structure of the present invention is simple, and it makes and very easy to use.
(2) the present invention adopts logic electronic components to realize its logic control function completely, and therefore its energy consumption is very low, fast operation.
(3) the present invention adopts source follower to be used as control switch, and therefore its performance is more stable, and its dynamic range is better.
(4) the present invention adopts gate drive circuit to drive, and can improve reaction speed of the present invention to a great extent, thus can better protect LED.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
As shown in Figure 1, the present invention is primarily of field effect transistor MOS, not gate IC1, not gate IC3, not gate IC4, filter delay circuit, first-level filtering wave circuit, secondary filter circuit, NOR gate circuit, resistance R3, resistance R5, resistance R9, electric capacity C3, and beam excitation formula logic amplifying circuit and gate drive circuit form.
During connection, the input of not gate IC2 wants the output of NAND gate IC1 to be connected, and namely not gate IC1 is connected in series with not gate IC2 phase.Described filter delay circuit is made up of resistance R7, diode D3, electrochemical capacitor C5 and resistance R8, wherein, between the positive pole that resistance R8 is serially connected in electrochemical capacitor C5 and negative pole, and the output of one end NAND gate IC2 of resistance R7 is connected, its other end is connected with the positive pole of electrochemical capacitor C5 after diode D3.
Described first-level filtering wave circuit wants the input of NAND gate IC1 to be connected, and the input of secondary filter circuit then NAND gate IC3 is connected, and the output of NOR gate circuit NAND gate IC4 is connected.
One end of resistance R3 is connected with the grid of field effect transistor MOS, and the output of its other end NAND gate IC1 is connected; One end of resistance R5 is connected with the grid of field effect transistor MOS, and its other end is connected with NOR gate circuit; The positive pole of electric capacity C3 is connected with the grid of field effect transistor MOS, and the output of its negative pole NAND gate IC3 is connected; One end of resistance R9 is connected with the drain electrode of field effect transistor MOS, other end ground connection, and gate drive circuit is then serially connected between the grid of field effect transistor MOS and the input of secondary filter circuit.
Described first-level filtering wave circuit is made up of diode D1, resistance R1, resistance R2 and electric capacity C1, and wherein, the input of the P pole NAND gate IC1 of diode D1 is connected, and its N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1.Resistance R1 is then in parallel with diode D1, and the minus earth of electric capacity C1.
Described NOR gate circuit is by XOR gate IC5, and diode D4, resistance R6 and electric capacity C4 form, and during connection, the N pole of diode D4 is connected with the first input end of XOR gate IC5, and its P pole is connected with secondary filter circuit; Resistance R6 is divider resistance, and its one end is connected with the P pole of diode D4, the external+12V voltage of its other end; The positive pole of electric capacity C4 is connected with the P pole of diode D4, its minus earth.Meanwhile, second input of XOR gate IC5 wants the output of NAND gate IC4 to be connected.
Described secondary filter circuit is made up of diode D2, resistance R4 and electric capacity C2, and wherein, the input of the N pole NAND gate IC3 of diode D2 is connected, and its P pole is connected with the P pole of diode D4; Resistance R4 and diode D2 is in parallel, and the input of the positive pole NAND gate IC3 of electric capacity C2 is connected, its minus earth.Meanwhile, the P pole of diode D2 is also connected with gate drive circuit.
Described beam excitation formula logic amplifying circuit is then primarily of power amplifier P1, NAND gate IC6, NAND gate IC7, NAND gate IC8, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C6, the resistance R10 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R10, the polar capacitor C8 that negative pole is connected with the source electrode of field effect transistor MOS, one end is connected with the negative input of NAND gate IC6, the resistance R11 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R12 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R13 that the other end is connected with the negative input of NAND gate IC8, positive pole is connected with the output of NAND gate IC7, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC8, and one end is connected with the positive pole of polar capacitor C8, the resistance R14 that the other end is connected with the negative input of NAND gate IC7 forms.
Meanwhile, the electrode input end of NAND gate IC6 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC7, and the electrode input end of NAND gate IC8 is connected with the output of power amplifier P1.
The electrode input end of described power amplifier P1 is connected with the positive pole of electrochemical capacitor C5, and the output of the negative input NAND gate IC4 of NAND gate IC7 is connected, and the negative pole of polar capacitor C8 is then connected with the source electrode of field effect transistor MOS.
Gate drive circuit is by triode Q1, and triode Q2, field effect transistor MOS1, unidirectional thyristor D8, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20, electric capacity C9, electric capacity C10, electric capacity C11, electric capacity C12 and diode D7 form.
During connection, the negative pole of electric capacity C9 is connected with the base stage of triode Q2, its positive pole is connected with the emitter of triode Q2 after resistance R16, resistance R17 is then in parallel with electric capacity C9, one end of resistance R15 is connected with the collector electrode of triode Q1, its other end is then connected with the positive pole of electric capacity C9, between the collector electrode that resistance R18 is then serially connected in triode Q1 and base stage, the N pole of diode D7 is connected with the collector electrode of triode Q2, its P pole is then connected with the grid of field effect transistor MOS1 after resistance R19.This triode Q2, triode Q1 and diode D7 form an amplifier, by the effect of this amplifier, make actuating speed of the present invention faster.
Simultaneously, the positive pole of electric capacity C10 is connected with the emitter of triode Q2, its negative pole is then connected with the grid of field effect transistor MOS1 after resistance R20, the positive pole of electric capacity C11 is connected with the negative pole of electric capacity C10, its negative pole is then connected with the P pole of unidirectional thyristor D8, and the positive pole of electric capacity C12 is connected with the control pole of unidirectional thyristor D8, its negative pole is then connected with the grid of field effect transistor MOS.The base stage of described triode Q1 is connected with the collector electrode of triode Q2, its emitter is then connected with the P pole of diode D7.The emitter of triode Q2 is connected with secondary filter circuit.Grounded drain, its source electrode of described field effect transistor MOS1 are then connected with the N pole of unidirectional thyristor D8.
4 outputs are formed altogether, for being connected with other LED circuits of outside in the present invention.Wherein, first output CT1 is drawn by the N pole of diode D1 and is formed, second output is drawn by the positive pole of electric capacity C9 and is formed, 3rd output is jointly drawn by the output of not gate IC4 and the output of NAND gate IC8 and is formed, and the 4th output is then drawn by the output of XOR gate IC5 and formed.
As mentioned above, just the present invention can well be realized.
Claims (6)
1. the excitation formula logic control system based on gate-drive, it is by field effect transistor MOS, not gate IC1, not gate IC3, not gate IC4, the not gate IC2 that the output of input NAND gate IC1 is connected, the filter delay circuit that the output of NAND gate IC2 is connected, the first-level filtering wave circuit that the input of NAND gate IC1 is connected, the input of NAND gate IC3 is connected secondary filter circuit, the NOR gate circuit that the output of NAND gate IC4 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R3 that the output of other end NAND gate IC1 is connected, one end is connected with the grid of field effect transistor MOS, the resistance R5 that the other end is connected with NOR gate circuit, positive pole is connected with the grid of field effect transistor MOS, the electric capacity C3 that the output of its negative pole NAND gate IC3 is connected, one end is connected with the drain electrode of field effect transistor MOS, the resistance R9 of other end ground connection, and the beam excitation formula logic amplifying circuit be serially connected between the source electrode of field effect transistor MOS and filter delay circuit forms, it is characterized in that: between the grid of scene effect pipe MOS and the input of secondary filter circuit, be also provided with gate drive circuit, described gate drive circuit is by triode Q1, triode Q2, field effect transistor MOS1, unidirectional thyristor D8, negative pole is connected with the base stage of triode Q2, the electric capacity C9 that positive pole is connected with the emitter of triode Q2 after resistance R16, the resistance R17 be in parallel with electric capacity C9, one end is connected with the collector electrode of triode Q1, the resistance R15 that the other end is then connected with the positive pole of electric capacity C9, be serially connected in the resistance R18 between the collector electrode of triode Q1 and base stage, N pole is connected with the collector electrode of triode Q2, the diode D7 that P pole is then connected with the grid of field effect transistor MOS1 after resistance R19, positive pole is connected with the emitter of triode Q2, the electric capacity C10 that negative pole is then connected with the grid of field effect transistor MOS1 after resistance R20, positive pole is connected with the negative pole of electric capacity C10, the electric capacity C11 that negative pole is then connected with the P pole of unidirectional thyristor D8, and positive pole is connected with the control pole of unidirectional thyristor D8, the electric capacity C12 that negative pole is then connected with the grid of field effect transistor MOS forms, the base stage of described triode Q1 is connected with the collector electrode of triode Q2, its emitter is then connected with the P pole of diode D7, the emitter of triode Q2 is connected with secondary filter circuit, grounded drain, its source electrode of described field effect transistor MOS1 are then connected with the N pole of unidirectional thyristor D8.
2. a kind of excitation formula logic control system based on gate-drive according to claim 1, it is characterized in that, described beam excitation formula logic amplifying circuit is by power amplifier P1, NAND gate IC6, NAND gate IC7, NAND gate IC8, negative pole is connected with the electrode input end of power amplifier P1, the polar capacitor C6 of positive pole ground connection after optical diode D5, one end is connected with the positive pole of polar capacitor C6, the resistance R10 of other end ground connection after diode D6, positive pole is connected with the tie point of diode D6 with resistance R10, the polar capacitor C8 that negative pole is connected with the source electrode of field effect transistor MOS, one end is connected with the negative input of NAND gate IC6, the resistance R11 that the other end is connected with the electrode input end of power amplifier P1, be serially connected in the resistance R12 between the negative input of power amplifier P1 and output, one end is connected with the output of NAND gate IC6, the resistance R13 that the other end is connected with the negative input of NAND gate IC8, positive pole is connected with the output of NAND gate IC7, the electric capacity C7 that negative pole is connected with the negative input of NAND gate IC8, and one end is connected with the positive pole of polar capacitor C8, the resistance R14 that the other end is connected with the negative input of NAND gate IC7 forms, the electrode input end of described NAND gate IC6 is connected with the negative input of power amplifier P1, and its output is connected with the electrode input end of NAND gate IC7, and the electrode input end of NAND gate IC8 is connected with the output of power amplifier P1, the electrode input end of described power amplifier P1 is then connected with filter delay circuit, and the output of the negative input of NAND gate IC7 also NAND gate IC4 is connected.
3. a kind of excitation formula logic control system based on gate-drive according to claim 2, it is characterized in that, described filter delay circuit is made up of resistance R7, diode D3, electrochemical capacitor C5 and resistance R8, between the positive pole that described resistance R8 is serially connected in electrochemical capacitor C5 and negative pole, the output of one end NAND gate IC2 of resistance R7 is connected, its other end is connected with the positive pole of electrochemical capacitor C5 after diode D3; The electrode input end of described power amplifier P1 is then connected with the positive pole of electrochemical capacitor C5.
4. a kind of excitation formula logic control system based on gate-drive according to claim 3, it is characterized in that, the diode D1 that described first-level filtering wave circuit is connected by the input of P pole NAND gate IC1, N pole is connected through the input of resistance R2 NAND gate IC1 after electric capacity C1, and form with the resistance R1 that diode D1 is in parallel; The minus earth of described electric capacity C1, the N pole of diode D1 is then as the input of this first-level filtering wave circuit.
5. a kind of excitation formula logic control system based on gate-drive according to claim 4, it is characterized in that, described NOR gate circuit is by XOR gate IC5, the diode D4 that N pole is connected with the first input end of XOR gate IC5, P pole is connected with secondary filter circuit, one end is connected with the P pole of diode D4, the resistance R6 of the external+12V voltage of the other end, and positive pole is connected with the P pole of diode D4, the electric capacity C4 of minus earth forms; The output of the second input NAND gate IC4 of described XOR gate IC5 is connected, and the output of not gate IC4 is also connected with the output of NAND gate IC8.
6. a kind of excitation formula logic control system based on gate-drive according to claim 5, it is characterized in that, the diode D2 that described secondary filter circuit is connected by the input of N pole NAND gate IC3, P pole is connected with the P pole of diode D4, the resistance R4 be in parallel with diode D2, and the input of positive pole NAND gate IC3 is connected, the electric capacity C2 of minus earth forms; The P pole of described diode D2 is also connected with the emitter of triode Q2.
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| CN201510307046.2A CN104837288A (en) | 2014-11-25 | 2015-06-06 | Excitation type logic control system based on gate drive |
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| CN201410686089.1A CN104394626A (en) | 2014-11-25 | 2014-11-25 | Excitation logic control system |
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| CN201510307046.2A CN104837288A (en) | 2014-11-25 | 2015-06-06 | Excitation type logic control system based on gate drive |
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| CN204316803U (en) * | 2014-11-25 | 2015-05-06 | 成都创图科技有限公司 | A kind of excitation formula logic control system |
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| CN204316803U (en) * | 2014-11-25 | 2015-05-06 | 成都创图科技有限公司 | A kind of excitation formula logic control system |
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| 高玉奎: "《电工常用电子技术入门》", 31 October 2006 * |
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Application publication date: 20150812 |