CN104934463A - 具有深注入区域的半导体装置及其制造方法 - Google Patents

具有深注入区域的半导体装置及其制造方法 Download PDF

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CN104934463A
CN104934463A CN201410208443.XA CN201410208443A CN104934463A CN 104934463 A CN104934463 A CN 104934463A CN 201410208443 A CN201410208443 A CN 201410208443A CN 104934463 A CN104934463 A CN 104934463A
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conductivity type
high voltage
region
trap
drift region
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CN104934463B (zh
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詹景琳
林正基
连士进
吴锡垣
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Macronix International Co Ltd
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Abstract

本发明公开了一种具有深注入区域的半导体装置及其制造方法，该半导体装置包括：一基板，具有一第一导电型；一高电压阱，具有一第二导电型，并配置在基板中；一源极阱，具有第一导电型，并配置在高电压阱中；一漂移区域，配置在高电压阱中并与源极阱分隔开；以及一深注入区域，具有第一导电型，并配置在源极阱与漂移区域之间的高电压阱中。

Description

具有深注入区域的半导体装置及其制造方法
技术领域
本发明是有关于一种半导体装置及其制造方法，且特别是有关于一种具有深注入区域的半导体装置及其制造方法。
背景技术
一种横向扩散金属-氧化物-半导体(Lateral DiffusedMetal-Oxide-Semiconductor，LDMOS)装置为一种广泛使用在显示设备、便携设备及多数其他应用中的高电压装置。LDMOS装置的设计目标包括一高崩溃电压及一低特定导通电阻。
LDMOS装置的特定导通电阻是受限于此装置的一分级区域(graderegion)的一掺杂浓度。当分级区域的掺杂浓度降低时，特定导通电阻增加。
发明内容
依据本发明的一实施例，一种半导体装置包括：一基板，具有一第一导电型；一高电压阱，具有一第二导电型，并配置在基板中；一源极阱，具有第一导电型，并配置在高电压阱中；一漂移区域，配置在高电压阱中，并与源极阱分隔开；以及一深注入区域，具有第一导电型，并配置在高电压阱中，位于源极阱与漂移区域之间。
依据本发明的另一实施例，一种半导体装置的制造方法包括：提供一个具有一第一导电型的基板；形成一个具有一第二导电型的高电压阱在基板中；形成一个具有第一导电型的源极阱在高电压阱中；形成一漂移区域在高电压阱中，且漂移区域与源极阱分隔开；以及形成一个具有第一导电型的深注入区域在高电压阱中，且在源极阱与漂移区域之间。
附图说明
图1A为依据一实施例的LDMOS装置的俯视图。
图1B为沿着图1A的线B-B′的LDMOS装置的剖面图。
图1C为沿着图1A的线C-C′的LDMOS装置的剖面图。
图2A-图14B概要显示依据一实施例的图1A-图1C的LDMOS装置的制造过程。
图15为显示图1A-图1C的LDMOS装置以及建构为一比较例的已知装置的漏极特征图。
图16为显示图1A-图1C的LDMOS装置以及建构为一比较例的已知装置的漏极特征图。
【符号说明】
B-B′： 线
C-C′： 线
IDS： 漏极-源极电流
VBS： 主体-源极电压
VDS： 漏极-源极电压
VGS： 栅极-源极电压
10： LDMOS装置/LDMOS
100： 基板
105： 高电压N阱(HVNW)
110： 第一P阱
115： 第二P阱
120： 漂移区域
120a： 第一区段
120b： 第二区段
122： P顶端区域
124： N分级区域
125： P型深注入区域
130： FOX层/绝缘层
131： 第一FOX部
132： 第二FOX部
133： 第三FOX部
134：  第四FOX部
140：  栅极氧化层
145：  栅极层
146：  多晶硅层
147：  硅化钨层
150：  间隙壁
155：  第一N+区域
160：  第二N+区域
165：  第一P+区域
170：  第二P+区域
180：  层间介电(ILD)层
190：  接触层
200：  基板
205：  高电压N阱(HVNW)/深阱
210：  第一P阱
215：  第二P阱
222：  P顶端区域
222′：P顶端注入区域
224：  N分级区域
224′：N分级注入区域
225：  P型深注入区域
225′：P型注入区域
230：  场氧化物(FOX)层
231：  第一FOX部
232：  第二FOX部
233：  第三FOX部
234：  第四FOX部
240：  栅极氧化层
245：  栅极层
246：  多晶硅层
247： 硅化钨层
250： 左侧间隙壁
250： 间隙壁
255： 第一N+区域
260： 第二N+区域
265： 第一P+区域
270： 第二P+区域
280： 层间介电(ILD)层
281： 第一开口部
282： 第二开口部
283： 第三开口部
284： 第四开口部
285： 第五开口部
290： 接触层
291： 第一接触部
292： 第二接触部
293： 第三接触部
294： 第四接触部
具体实施方式
现在将详细参考本实施例，其例子被显示于附图中。若有可能的话，图式将使用相同的参考数字以表示相同或类似的部分。
图1A概要显示依据一实施例的LDMOS装置10的俯视图。图1B为沿着图1A的线B-B′的LDMOS装置10的剖面图。图1C为沿着图1A的线C-C′的LDMOS装置10的剖面图。
如图1A-图1C所示，LDMOS装置10包括：一P型基板100；一高电压N阱(high-voltage N-well，HVNW)105，形成于基板100中；一第一P阱110，形成于HVNW105中；一第二P阱115，形成于HVNW105外部并与HVNW105邻接；一漂移区域120，形成于HVNW105中，位于第一P阱110的一侧(例如右侧)上并与第一P阱110分隔开；一P型深注入区域125，形成于HVNW105中，位于第一P阱110及漂移区域120之间；以及一绝缘层130，配置在基板100上。漂移区域120包括多个交互排列的第一区段120a与第二区段120b。每个第一区段120a包括一P顶端区域122及一配置在P顶端区域122上的N分级区域124。每个第二区段120b包括N分级区域124。绝缘层130可以由场氧化物(field oxide，FOX)所构成。以下，绝缘层130被称为FOX层130。FOX层130包括一个与漂移区域120分隔开的第一FOX部131、一覆盖漂移区域120的第二FOX部132、一覆盖在第一P阱110与第二P阱115之间的HVNW105的一部分的第三FOX部133，以及一覆盖一第二P阱115的侧(例如左侧)边缘部分的第四FOX部134。
LDMOS装置10亦包括：一栅极氧化层140，配置在基板100上位于第一P阱110的侧(亦即右侧)边缘部分与一第二FOX部132的侧(例如左侧)边缘部分之间；一栅极层145，配置在栅极氧化层140上；多个间隙壁150，配置在栅极层145的侧壁上；一第一N+区域155，形成于HVNW105中，位于第一FOX部131与第二FOX部132之间；一第二N+区域160，形成于与一栅极层145的侧(例如左侧)边缘部分邻接的第一P阱110中；一第一P+区域165，形成于与第二N+区域160邻接的第一P阱110中；以及一第二P+区域170，形成于第二P阱115中，位于第三FOX部133及第四FOX部134之间。栅极层145包括一多晶硅层146及一形成于多晶硅层146上的硅化钨层147。第一N+区域155构成一LDMOS装置10的漏极区域。第二N+区域160及第一P+区域165构成一LDMOS装置10的源极区域。第二P+区域170构成一LDMOS装置10的主体区域。第一P阱110构成一LDMOS装置10的源极阱。第二P阱115构成一LDMOS装置10的主体阱。
LDMOS装置10更包括一形成于基板100上的层间介电(ILD)层180，以及一形成于ILD层180上的接触层190。接触层190包括多个隔离的接触部，用于经由形成于ILD层180中的不同的开口部，传导地接触形成于基板100中的结构的不同部分。
在依据本实施例的LDMOS装置10中，P型深注入区域125是形成于第一P阱110与漂移区域120之间的区域中，用以帮助一全空乏区的形成。因此，可减少P顶端区域122中的掺杂浓度，或可增加N分级区域124中的掺杂浓度，其具有降低LDMOS装置10的特定导通电阻的效果。
图2A-图14B概要显示依据一实施例的图1A-图1C的LDMOS装置10的制造过程。图2A、图3A、图4A、...、图14A概要显示在LDMOS装置10的制造过程的步骤期间，沿着图1A的线B-B′的LDMOS装置10的局部剖面图。图2B、图3B、图4B、...、图14B概要显示在LDMOS装置10的制造过程的步骤期间，沿着图1A的线C-C′的LDMOS装置10的局部剖面图。
首先，参见图2A及图2B，提供一个具有一第一导电型的基板200，且一个具有一第二导电型的深阱205是形成于基板200中并从一基板200的上表面朝下延伸。在所显示的实施例中，第一导电型为P型，而第二导电型为N型。以下，深阱205被称为一高电压N阱(HVNW)205。基板200可以由一P型主体硅材料、一P型外延层或一P型绝缘层上硅(silicon-on-insulator，SOI)材料所组成。HVNW205可通过下述工艺而形成：一光刻工艺，定义一待形成HVNW205的区域；一离子注入工艺，以大约1011至1013原子/cm2的浓度，注入一N型掺质(例如，磷或砷)在定义的区域中；以及一加热工艺，驱入注入的掺质以达到一预定深度。
参见图3A及图3B，一第一P阱210是形成于HVNW205中，靠近一HVNW205的边缘部分。一第二P阱215是形成于基板200中，在HVNW205的边缘部分外部并与HVNW205的边缘部分邻接。第一P阱210与第二P阱215可通过下述工艺而形成：一光刻工艺，界定待形成第一P阱210与第二P阱215的区域；一离子注入工艺，以大约1012至1014原子/cm2的浓度，注入一P型掺质(例如，硼)在定义的区域中；以及一加热工艺，驱入注入的掺质以达到一预定深度。
参见图4A及图4B，一P顶端注入区域222′是形成于HVNW205中，位于对应于图1A所显示的第一区段120a的区域中。没有P顶端注入区域222′是形成于对应于图1A所显示的第二区段120b的区域中。P顶端注入区域222′可通过下述工艺而形成：一光刻工艺，定义第一区段120a；以及一离子注入工艺，以大约1011至1014原子/cm2的浓度，注入一P型掺质(例如，硼)进入第一区段120a中。
参见图5A及图5B，一N分级注入区域224′是形成于HVNW205中，位于对应于图1A所显示的第一区段120a与第二区段120b两者的区域中。N分级注入区域224′可通过下述工艺而形成：一光刻工艺，定义第一区段120a与第二区段120b；以及一离子注入工艺，以大约1011至1014原子/cm2的浓度，注入一N型掺质(例如，磷或砷)在第一区段120a与第二区段120b中。
参见图6A及图6B，一P型注入区域225′是形成于HVNW205中，靠近一第一P阱210的右侧边缘。P型注入区域225′可通过下述工艺而形成：一光刻工艺，定义一待形成P型注入区域225′的区域；以及一离子注入工艺，以大约1012至1014原子/cm2的浓度，注入一P型掺质(例如，硼)在定义的区域中。用以形成P型注入区域225′的离子注入工艺的注入能量，是大于用以形成P顶端注入区域222′的离子注入工艺的注入能量，以及用以形成N分级注入区域224′的离子注入工艺的注入能量。
参见图7A及图7B，一个以场氧化物(FOX)层230的型式存在的绝缘层，是形成于基板200的上表面上。FOX层230包括：一第一FOX部231，覆盖一HVNW205的右边缘部分；一第二FOX部232，覆盖P顶端注入区域222′及N分级注入区域224′；一第三FOX部233，覆盖一HVNW205的左边缘部分，位于第一P阱210与第二P阱215之间；以及一第四FOX部234，覆盖一第二P阱215的左边缘部分。
FOX层230可通过下述工艺而形成：一沉积工艺，沉积一氮化硅层；一光刻工艺，定义待形成FOX层230的区域；一刻蚀工艺，移除在定义的区域中的氮化硅层；以及一热氧化工艺，形成在定义的区域中的FOX层230。在用以形成FOX层230的热氧化工艺期间，P顶端注入区域222′中的P型掺质、P型注入区域225′中的P型掺质以及N分级注入区域224′中的N型掺质，是被驱至HVNW205中的预定深度，以分别形成P顶端区域222、P型深注入区域225及N分级区域224。P顶端区域222的深度可以大约是0.5μm至3μm。N分级区域224的深度可以大约是0.1μm至1μm。P型深注入区域225的宽度与深度、P型深注入区域225中的掺杂浓度、P型深注入区域225与第一P阱210之间的距离，以及P型深注入区域225与P顶端区域222及N分级区域224之间的距离，为鉴于各种设计考虑而决定的变量，例如P顶端区域222、N分级区域224与HVNW205中的掺杂浓度，以及LDMOS装置10的结构及/或应用。
参见图8A及图8B，一栅极氧化层240是形成于未被FOX层230所覆盖的图7A及图7B的结构的表面部分上。亦即，栅极氧化层240是形成在第一FOX部231与第二FOX部232之间、在第二FOX部232与第三FOX部233之间，以及在第三FOX部233与第四FOX部234之间。栅极氧化层240可通过下述工艺而形成：一牺牲氧化工艺，用以形成一牺牲氧化层；一洁净工艺，用以移除牺牲氧化层；以及一氧化工艺，用以形成栅极氧化层240。
参见图9A及图9B，一栅极层245是形成于栅极氧化层240上，藉以覆盖于一第二FOX部232的左部分及一第一P阱210的右部分上。栅极层245可包括一多晶硅层246及一形成于多晶硅层246上的硅化钨层247。栅极层245的厚度可以大约是0.1μm至0.7μm。栅极层245可通过下述工艺而形成：一沉积工艺，使一多晶硅层及一硅化钨层沉积在整个基板上面；一光刻工艺，定义一待形成栅极层245的区域；以及一刻蚀工艺，移除在定义的区域外部的多晶硅层与硅化钨层。
参见图10A及图10B，多个间隙壁250是形成于栅极层245的两侧上。间隙壁250可以是四乙氧基硅烷(TEOS)氧化膜。间隙壁250可通过下述工艺而形成：一沉积工艺，沉积TEOS氧化膜；一光刻工艺，定义待形成间隙壁250的区域；以及一刻蚀工艺，移除在定义的区域外部的TEOS氧化膜。在形成间隙壁250之后，通过刻蚀移除除了在栅极层245及间隙壁250之下的部分以外的栅极氧化层240。
参见图11A及图11B，一第一N+区域255是形成于HVNW205中，位于第一FOX部231与第二FOX部232之间，而一第二N+区域260是形成于第一P阱210中，而与一栅极层245的左边缘部分邻接，且在一左侧间隙壁250之下。第一N+区域255与第二N+区域260可通过下述工艺而形成：一光刻工艺，定义待形成第一N+区域255与第二N+区域260的区域；以及一离子注入工艺，以大约1015至1016原子/cm2的浓度，注入一N型掺质(例如，磷或砷)在定义的区域中。
参见图12A及图12B，一第一P+区域265是形成于第一P阱210中而与第二N+区域260邻接，而一第二P+区域270是形成于第二P阱215中，位于第三FOX部233与第四FOX部234之间。第一P+区域265与第二P+区域270可通过下述工艺而形成：一光刻工艺，定义待形成第一P+区域265与第二P+区域270的区域；以及一离子注入工艺，以大约1015至1016原子/cm2的浓度，注入一P型掺质(例如，硼)在定义的区域中。
参见图13A及图13B，一层间介电(InterLayer Dielectric，ILD)层280是形成于图12A及图12B的结构的整体表面上。ILD层280包括：一第一开口部281，垂直地与第一N+区域255对准；一第二开口部282，垂直地与栅极层245对准；一第三开口部283，垂直地与第二N+区域260对准；一第四开口部284，垂直地与第一P+区域265对准；以及一第五开口部285，垂直地与第二P+区域270对准。ILD层280可包括未掺杂的硅玻璃(UndopedSilicate glass，USG)及/或硼磷硅玻璃(Borophosphosilicate glass，BPSG)。ILD层280的厚度可以是0.5μm至2μm。ILD层280可通过下述工艺而形成：一沉积工艺，沉积一层的USG及/或BPSG；一光刻工艺，定义待形成ILD层280的区域；以及一刻蚀工艺，移除在定义的区域外部的此层的USG及/或BPSG来形成开口部281至285。
参见图14A及图14B，一接触层290是形成于图13A及图13B的结构上。接触层290包括：一第一接触部291，接触第一N+区域255；一第二接触部292，接触栅极层245；一第三接触部293，接触第二N+区域260及第一P+区域265两者；以及一第四接触部294，接触第二P+区域270。接触层290可以由任何导电金属(例如铝、铜，或铝铜合金)所构成。接触层290可通过下述工艺而形成：一沉积工艺，沉积一金属层；一光刻工艺，定义待形成接触层290的区域；以及一刻蚀工艺，移除在定义的区域外部的金属层。
图15为显示具有如图1A-图1C所示的P型深注入区域125的LDMOS装置10以及构建为一比较例的已知装置的漏极特征图。已知装置并不包括P型深注入区域125。在图15中，一漏极-源极电压VDS从0改变至800V，而一栅极-源极电压VGS及一主体-源极电压VBS是维持于0V。如图15所显示的，LDMOS装置10与已知装置两者的截止-崩溃(off-breakdown)电压系超过700V。因此，LDMOS装置10具有大约与已知装置相同的截止-崩溃电压。
图16为显示LDMOS装置10与已知装置的漏极特征图。在图16中，VDS从0改变至2V，而VGS是维持于20V。如图16所显示的，对于VDS的相同数值而言，LDMOS10的一漏极-源极电流IDS是高于已知装置的。因此，LDMOS10具有一比已知装置更低的特定导通电阻，同时具有与已知装置相同的截止-崩溃电压。
虽然上述实施例系针对图1A及图1B所显示的N型LDMOS装置10及图2A-图13B所显示的其制造方法，但熟习本项技艺者现在将明白所揭露的概念，是同等适合于一P型LDMOS装置。熟习本项技艺者亦将明白所揭露的概念，是适合于其他半导体装置及其制造方法，例如绝缘栅双载子晶体管(IGBT)装置及二极管。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视随附的权利要求范围所界定的为准。

Claims (18)

1.一种半导体装置，包括：
一基板，具有一第一导电型；
一高电压阱，具有一第二导电型，并配置在该基板中；
一源极阱，具有该第一导电型，并配置在该高电压阱中；
一漂移区域，配置在该高电压阱中，并与该源极阱分隔开；以及
一深注入区域，具有该第一导电型，并配置在该高电压阱中，位于该源极阱与该漂移区域之间。
2.根据权利要求1所述的半导体装置，其中该漂移区域包括多个交互排列的第一区段与第二区段，
每个第一区段包括一个具有该第一导电型的顶端区域，以及一个具有该第二导电型并形成于该顶端区域的顶端上的分级区域，且
每个第二区段只包括该分级区域。
3.根据权利要求1所述的半导体装置，其中该第一导电型为P型，而该第二导电型为N型。
4.根据权利要求1所述的半导体装置，其中该第一导电型为N型及该第二导电型为P型。
5.根据权利要求1所述的半导体装置，其中该源极阱是被配置靠近该高电压阱的一边缘部分，且该装置更包括一个具有该第一导电型的主体阱，该主体阱配置在该高电压阱外部，并与该高电压阱的该边缘部分邻接。
6.根据权利要求5所述的半导体装置，更包括一个配置在该基板上的绝缘层，该绝缘层包括：
一第一绝缘部分，与该漂移区域分隔开；
一第二绝缘部分，覆盖该漂移区域；
一第三绝缘部分，覆盖该高电压阱的该边缘部分；以及
一第四绝缘部分，覆盖该主体阱的一边缘部分。
7.根据权利要求6所述的半导体装置，更包括：
一栅极氧化层，配置在该基板上，位于该源极阱及该第二绝缘部分之间；以及
一栅极层，配置在该栅极氧化层上。
8.根据权利要求7所述的半导体装置，更包括：
一源极区域，配置在该源极阱中；
一漏极区域，配置在该高电压阱中，并与该漂移区域分隔开；以及
一主体区域，配置在该主体阱中。
9.根据权利要求8所述的半导体装置，更包括：
一层间介电层，配置在该基板上；以及
一接触层，配置在该层间介电层上。
10.一种半导体装置的制造方法，该方法包括：
提供一个具有一第一导电型的基板；
形成一个具有一第二导电型的高电压阱在该基板中；
形成一个具有该第一导电型的源极阱在该高电压阱中；
形成一漂移区域在该高电压阱中，且该漂移区域与该源极阱分隔开；以及
形成一个具有该第一导电型的深注入区域在该高电压阱中，以及在该源极阱与该漂移区域之间。
11.根据权利要求10所述的方法，其中该第一导电型为P型，而该第二导电型为N型。
12.根据权利要求10所述的方法，其中该第一导电型为N型及该第二导电型为P型。
13.根据权利要求10所述的方法，其中该漂移区域包括多个交互排列的第一区段与第二区段，
在该高电压阱中的该漂移区域的该形成步骤包括：
只在这些第一区段中形成一个具有该第一导电型的顶端区域；及
在这些第一区段及这些第二区段的两者中形成一个具有该第二导电型的分级区域，该分级区域是形成于各该第一区段中的该顶端区域的顶端上。
14.根据权利要求10所述的方法，其中该源极阱是形成靠近该高电压阱的一边缘部分，且该方法更包括：形成一个具有该第一导电型的主体阱，位于该高电压阱的该边缘部分外部，并与该高电压阱的该边缘部分邻接。
15.根据权利要求14所述的方法，更包括形成一个配置在该基板上的绝缘层，包括：
形成一与该漂移区域分隔开的第一绝缘部分；
形成一覆盖该漂移区域的第二绝缘部分；
形成一覆盖该高电压阱的该边缘部分的第三绝缘部分；以及
形成一覆盖该主体阱的一边缘部分的第四绝缘部分。
16.根据权利要求15所述的方法，更包括：
形成一栅极氧化层在该基板上，位于该源极阱与该第二绝缘部分之间；及
形成一栅极层在该栅极氧化层上。
17.根据权利要求16所述的方法，更包括：
形成一源极区域在该源极阱中；
形成一漏极区域在该高电压阱中，且该漏极区域与该漂移区域分隔开；以及
形成一配置在该主体阱中的主体区域。
18.根据权利要求17所述的方法，更包括：
形成一层间介电层在该基板上；以及
形成一接触层在该层间介电层上。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9520492B2 (en) * 2015-02-18 2016-12-13 Macronix International Co., Ltd. Semiconductor device having buried layer
US9761656B2 (en) * 2015-04-10 2017-09-12 Macronix International Co., Ltd. Semiconductor device having buried region and method of fabricating same
US9520471B1 (en) * 2015-11-17 2016-12-13 Macronix International Co., Ltd. Semiconductor device having gradient implant region and manufacturing method thereof
US9461046B1 (en) 2015-12-18 2016-10-04 Texas Instruments Incorporated LDMOS device with graded body doping
US10297661B2 (en) * 2017-06-30 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage resistor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258215A1 (en) * 2007-04-23 2008-10-23 Olof Tornblad LDMOS Device
JP2009088288A (ja) * 2007-09-28 2009-04-23 Fujifilm Corp 電荷転送素子および固体撮像素子並びに撮像装置
CN102097469A (zh) * 2009-12-10 2011-06-15 世界先进积体电路股份有限公司 半导体结构及其制造方法
US20110140201A1 (en) * 2009-12-16 2011-06-16 Cheng-Chi Lin Lateral power mosfet structure and method of manufacture
CN102136493A (zh) * 2010-01-21 2011-07-27 上海华虹Nec电子有限公司 高压隔离型ldnmos器件及其制造方法
US20120267715A1 (en) * 2011-04-20 2012-10-25 Chou Wei-Chun High voltage semiconductor device and method for fabricating the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7180132B2 (en) * 2004-09-16 2007-02-20 Fairchild Semiconductor Corporation Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region
KR20100064263A (ko) * 2008-12-04 2010-06-14 주식회사 동부하이텍 반도체 소자 및 이의 제조 방법
US20120104492A1 (en) * 2010-10-29 2012-05-03 Macronix International Co., Ltd. Low on-resistance resurf mos transistor
TWI440183B (zh) 2011-03-24 2014-06-01 Macronix Int Co Ltd 超高電壓ｎ型金屬氧化物半導體元件及其製造方法
US8610209B2 (en) * 2011-03-24 2013-12-17 Macronix International Co., Ltd. Ultra-high voltage N-type-metal-oxide-semiconductor (UHV NMOS) device and methods of manufacturing the same
TWI436483B (zh) 2011-03-29 2014-05-01 Macronix Int Co Ltd 半導體裝置
US8482059B2 (en) * 2011-05-05 2013-07-09 Macronix International Co., Ltd. Semiconductor structure and manufacturing method for the same
US20120292740A1 (en) * 2011-05-19 2012-11-22 Macronix International Co., Ltd. High voltage resistance semiconductor device and method of manufacturing a high voltage resistance semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258215A1 (en) * 2007-04-23 2008-10-23 Olof Tornblad LDMOS Device
JP2009088288A (ja) * 2007-09-28 2009-04-23 Fujifilm Corp 電荷転送素子および固体撮像素子並びに撮像装置
CN102097469A (zh) * 2009-12-10 2011-06-15 世界先进积体电路股份有限公司 半导体结构及其制造方法
US20110140201A1 (en) * 2009-12-16 2011-06-16 Cheng-Chi Lin Lateral power mosfet structure and method of manufacture
CN102136493A (zh) * 2010-01-21 2011-07-27 上海华虹Nec电子有限公司 高压隔离型ldnmos器件及其制造方法
US20120267715A1 (en) * 2011-04-20 2012-10-25 Chou Wei-Chun High voltage semiconductor device and method for fabricating the same

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