CN107819035B - 改善的功率mos - Google Patents

改善的功率mos Download PDF

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CN107819035B
CN107819035B CN201710830399.XA CN201710830399A CN107819035B CN 107819035 B CN107819035 B CN 107819035B CN 201710830399 A CN201710830399 A CN 201710830399A CN 107819035 B CN107819035 B CN 107819035B
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史蒂文·托马斯·皮克
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Abstract

一种改善的功率MOS。公开了一种制造器件的工艺。该工艺包括：在衬底上形成第一导电类型的外延层；在外延层中形成第二导电类型的第一垂直部分；通过靠近第一垂直部分垂直刻蚀来创建第一垂直沟槽；用第一类型氧化物填充第一垂直沟槽；在第一垂直沟槽中形成第二垂直沟槽。第二垂直沟槽由第一垂直沟槽中的第一类型氧化物来限定。该工艺还包括：在第二垂直沟槽的内壁上形成第二类型氧化物；用多晶硅填充第二垂直沟槽。在外延层的垂直靠近第一垂直沟槽的第二垂直部分中，通过注入第一导电类型的离子来创建本体区，并且通过在本体区的顶层中注入离子来创建源极区。

Description

改善的功率MOS
技术领域
本公开涉及半导体器件领域，更具体地，涉及改善的功率MOS。
背景技术
沟槽栅技术通常用于改善半导体器件尤其是高电压器件中的击穿电压特性。在沟槽栅技术中，栅极垂直埋在源极中，通常由隔离盖分离。沟槽栅技术的其他优点包括降低至少在一些应用中可能不期望的结栅场效应晶体管(JFET)效应。然而，当期望低电压配置时，由于需要降低嵌入式栅极的宽度，因此沟槽栅技术提供一些缺点。降低表面场(RESURF)技术是用于设计横向高压、低导通电阻器件的最广泛使用的方法之一。该技术允许将双极型晶体管和MOS晶体管与范围从20V至1200V的高电压器件集成在一起。
沟槽MOS(具有沟槽栅的金属氧化物半导体)半导体器件通常用于功率应用。沟槽MOS器件通常包括其上具有外延生长的、掺杂硅的层的半导体衬底，其中形成包含栅电极和栅极电介质的沟槽。该器件的源极区位于邻近沟槽的上部。该器件还包括漏极区，其通过本体区与源极区分离，沟槽延伸穿过所述本体区。
发明内容
提供该发明内容来以简化形式介绍一些概念，下面在具体实施方式中进一步描述这些概念。本发明内容不旨在确定所要求保护主题的主要特征或必要特征，也不旨在用于限制所要求保护的主题的范围。
在一个实施例中，公开了制造器件的工艺。该工艺包括：在衬底上形成第一导电类型的外延层；在外延层中形成第二导电类型的第一垂直部分；通过靠近第一垂直部分垂直刻蚀来创建第一垂直沟槽；用第一类型氧化物填充第一垂直沟槽；在第一垂直沟槽中形成第二垂直沟槽。第二垂直沟槽由第一垂直沟槽中的第一类型氧化物来限定。该工艺还包括：在第二垂直沟槽的内壁上形成第二类型氧化物；用多晶硅填充第二垂直沟槽。在外延层的垂直靠近第一垂直沟槽的第二垂直部分中，通过注入第二导电类型的离子来创建本体区，并且通过在本体区的顶层中注入离子来创建源极区。
在一些实施例中，制造所述器件的工艺还包括：在第一垂直部分、第一垂直沟槽和第二垂直部分之上形成第一类型氧化物的层。第一类型氧化物是原硅酸四乙酯(TEOS电介质)。第二类型氧化物是二氧化硅。第一导电类型是n型。第二导电类型是p型。
在另一实施例中，公开了一种器件。该器件包括具有第一导电类型的外延层的衬底。该器件还包括：在外延层中实现的两个对称且相同的单元，其中，这两个对称单元中的每个单元包括深沟槽、第二导电类型的降低表面场(RESURF)板、本体区、源极区、漏极区和在深沟槽中实现的栅电极。组合这两个对称且相同的单元，使得该组合共享漏极区和RESURF板。
在一些实施例中，深沟槽用氧化物来填充，并且本体区具有第二导电类型。在深沟槽中实现栅电极，并且栅电极用多晶硅来填充并且由栅极氧化物来限定。源极区形成在本体区之上，使得源极区完全覆盖本体区，并且两个对称且相同的单元中的每个单元包括实质覆盖栅电极和源极区的电介质层。
附图说明
为了能够详细地理解本发明的上述特征的方式，可以通过参考实施例来获得上述简要总结的本发明的更具体的描述，其中一些实施例在附图中示出。然而，要注意，附图仅示出了本发明的典型实施例，因此不应被视为限制其范围，因为本发明可以有其他同等有效的实施例。一旦结合附图阅读本说明书，所要求保护的主题的优点对于本领域技术人员而言将变得明显，在附图中，相同的附图标记用于表示相同的元件，并且在附图中：
图1绘出根据本公开的一个或更多个实施例的器件的横截面图的示意图，该横截面图示出沟槽中的栅极、本体区和RESURF板；
图2至图10绘出根据本公开的一个或更多个实施例的在各种逐步制造阶段中的装置的截面的示意图；以及
图11绘出根据本公开的一个或更多个实施例的包括两个图1至图10中描述的半单元的完整晶体管。
注意，这些图未按比例绘制。已经省略了图形转换之间的中间步骤，以免混淆本公开。这些中间步骤是本领域技术人员已知的。
具体实施方式
在说明书中省略了或没有详细描述许多众所周知的制造步骤、组件和连接器，以免混淆本公开。
图1绘出使用本文件中稍后描述的工艺制造的器件100的横截面图的示意图。该器件100包括栅电极112、RESURF板114、源极区102、本体区104、栅极电介质106以及用电介质108填充的沟槽110。
制造这种器件的一种方法是在浅沟槽中制造栅电极，然后通过以高能量注入p型RESURF区域来创建RESURF板，以使RESURF板更深(以实现高击穿电压(BVdss))。然而，随着能量增加，注入的掺杂体(species)会渗透注入掩模，所述注入掩模被放在适当位置来保护除了通过其创建RESURF板的区域以外的区域。注入物的这种渗透和横向蔓延导致较高的、不期望的Rdson。
该器件100还可以使用四端RESURF技术来制造。然而，这种工艺很复杂，并且需要特殊的工厂变化。此外，针对不同的BVdss规范，可能需要对器件设计进行新的优化。
根据本文描述的实施例的器件100的制造在如图2中所示的衬底200开始。注意，仅示出衬底200的截面。在衬底200的顶层上注入外延层202。外延层202是n型的，并且可以使用磷来形成。可以使用其它材料来形成该外延层202，只要该材料能够提供n型注入物即可。
如图3所示，在外延层202的表面上形成光致抗蚀剂层204。使用公知的刻蚀方法来刻蚀光致抗蚀剂层204的一部分206。该部分206的宽度约等于RESURF板114的期望宽度。可以注入REFURF板114，或者也可以使用离子沉积的工艺来形成REFURF板114。应当注意，这里描述的工艺是用于制造NMOS器件。本领域技术人员将认识到，本文所述的工艺也可以用于制造PMOS器件。
图4示出通过该部分206注入p型外延208。硼或类似材料可以用于这种注入。然后，去除光致抗蚀剂层204，并且如图5所示，在表面上形成第二光致抗蚀剂层210。在中间蚀刻第二光致抗蚀剂层210。如图6所示，继续刻蚀以创建沟槽212。如图7所示，然后用原硅酸四乙酯(TEOS电介质)214或类似材料来填充沟槽212。类似于图6中所示的工艺，刻蚀沟槽212的一部分，并且在刻蚀空间的壁和底部上形成栅极氧化物(例如，二氧化硅)。然后，用n型多晶硅填充刻蚀空间以形成栅电极218。
如图8所示，形成光致抗蚀剂层220，并且刻蚀掉空间222。通过该空间222，注入第一p型本体区104，优选地使用硼来注入。在p型本体区104的顶部上，使用砷或类似材料来注入n型源极区102。
如图9所示，去除光致抗蚀剂层220，并且如图10所示，在RESURF板114、栅电极112和源极区102之上沉积TEOS电介质层224。
上述工艺使用标准制造技术，而不需要任何专用的工艺控制或工厂修改。该工艺还适用于制造具有各种BVdss的器件，无需改变任何制造步骤。与现有技术的制造技术相比，因为在该工艺中更容易控制RESURF板114的尺寸和栅电极112的尺寸，所以可以获得更高的BVdss。
上图描述了半单元的制造。图11绘出组合这样的两个半单元以制造晶体管。两个半单元以镜像方式并排对称地制造，使得两个半单元共享RESURF板114。根据每半个单元只有一个沟道的事实，该器件可以与使用其他技术制造的其他器件区分开。由深沟槽108限定的区域对Rdson没有贡献，但是该区域在源极处被偏置以产生0伏的RESURF屏蔽。
这些实施例中的一些或全部可以组合，一些可以完全省略，以及可以添加额外工艺步骤的同时仍然实现本文所述的产品。因此，本文描述的主题可以以许多不同的变化来实现，并且所有这些变化都被认为在所要求保护的范围内。
虽然已经通过示例和按照特定实施例来描述了一个或更多个实施方式，但是要理解，一个或更多个实施方式不限于所公开的实施例。相反，旨在覆盖对本领域技术人员明显的各种变型和类似的布置。因此，所附权利要求的范围应当被赋予最宽泛的解释，以便包括所有这些变型和类似的布置。
在描述主题的上下文中(特别是在所附权利要求的上下文中)使用术语“一”、“一个”和“该”以及类似指示物的使用要被解释为涵盖单数和复数二者，除非在本文中另有说明或者明确地与上下文相矛盾。除非在本文中另有说明，否则本文中对数值范围的描述仅旨在用作单独提及落在该范围内的每个单独值的速记方法，并且将每个单独值并入本说明书中就好像其在本文中被单独列举一样。此外，前面的描述仅仅是出于说明的目的，而不是出于限制的目的，因为所寻求的保护范围由下文所阐述的权利要求以及有权享有的任何等同物来限定。本文提供的任何和所有示例或示例性语言(例如，“诸如”)的使用仅旨在更好地说明主题，并且不对主题的范围构成限制，除非另外要求保护。在权利要求书和书面说明书中，术语“基于”和其它表示用于引起结果的条件的类似短语并不旨在排除导致该结果的任何其他条件。说明书中的语言不应被解释为表示对于实践所要求保护的本发明所必需的任何未要求保护的元件。
在本文中描述了优选实施例，包括对发明人已知的用于实施所要求保护主题的最佳方式。当然，一旦阅读了前面的说明书，这些优选实施例的变化对于本领域普通技术人员将变得明显。发明人期望技术人员适当地采用这种变化，并且发明人旨在不同于本文中特定描述的内容来实践所要求保护的主题。因此，这个所要求保护的主题包括根据适用法律允许的在所附权利要求中所述的主题的所有变型物和等同物。此外，除非另有说明或者明确地与上下文相矛盾，否则包含所有可能变化的上述元件的任意组合。

Claims (13)

1.一种制造半导体器件的工艺，所述工艺包括：
在衬底上形成第一导电类型的外延层；
在所述外延层中形成第二导电类型的第一垂直部分；
通过靠近所述第一垂直部分进行垂直刻蚀来创建第一垂直沟槽；
用第一类型氧化物填充所述第一垂直沟槽；
在所述第一垂直沟槽中形成第二垂直沟槽，其中，所述第二垂直沟槽由所述第一垂直沟槽中的所述第一类型氧化物来限定；
在所述第二垂直沟槽的内壁上形成第二类型氧化物；
用多晶硅填充所述第二垂直沟槽；
在所述外延层的垂直靠近所述第一垂直沟槽的第二垂直部分中，注入所述第二导电类型的离子来创建本体区；以及
在所述第二垂直部分中，注入离子以在所述本体区的顶层中创建源极区；
所述第一垂直部分与所述第二垂直部分位于所述第一垂直沟槽的不同侧。
2.如权利要求1所述的制造半导体器件的工艺，还包括：在所述第一垂直部分、所述第一垂直沟槽和所述第二垂直部分之上形成所述第一类型氧化物的层。
3.如权利要求1所述的制造半导体器件的工艺，其中，所述第一类型氧化物是原硅酸四乙酯，即TEOS电介质。
4.如权利要求1所述的制造半导体器件的工艺，其中，所述第二类型氧化物是氧化硅。
5.如权利要求1所述的制造半导体器件的工艺，其中，所述第一导电类型是n型。
6.如权利要求1所述的制造半导体器件的工艺，其中，所述第二导电类型是p型。
7.一种半导体器件，包括：
衬底，具有第一导电类型的外延层；
在所述外延层中实现的两个对称且相同的单元，其中，这两个对称单元中的每个单元包括深沟槽、第二导电类型的降低表面场RESURF板、在所述深沟槽中实现的栅电极、在所述第一导电类型的外延层中实现的本体区和源极区、以及漏极区；并且
其中，组合这两个对称的单元使得该组合共享所述漏极区和所述降低表面场RESURF板；
其中，所述第二导电类型的降低表面场RESURF板和所述第一导电类型的外延层位于所述深沟槽不同侧。
8.如权利要求7所述的半导体器件，其中，所述深沟槽用氧化物来填充。
9.如权利要求7所述的半导体器件，其中，所述本体区具有所述第二导电类型。
10.如权利要求7所述的半导体器件，其中，所述栅电极在所述深沟槽中实现。
11.如权利要求10所述的半导体器件，其中，所述栅电极用多晶硅来填充并且由栅极氧化物来限定。
12.如权利要求7所述的半导体器件，其中，所述源极区形成在所述本体区之上使得所述源极区完全覆盖所述本体区。
13.如权利要求7所述的半导体器件，其中，所述两个对称且相同的单元中的每个单元包括实质覆盖所述栅电极和所述源极区的电介质层。
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