CN104900529A - 一种提高栅控晶体管线性度的方法及其结构 - Google Patents

一种提高栅控晶体管线性度的方法及其结构 Download PDF

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CN104900529A
CN104900529A CN201510196111.9A CN201510196111A CN104900529A CN 104900529 A CN104900529 A CN 104900529A CN 201510196111 A CN201510196111 A CN 201510196111A CN 104900529 A CN104900529 A CN 104900529A
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王元刚
冯志红
吕元杰
敦少博
徐鹏
宋旭波
周幸叶
谭鑫
顾国栋
郭红雨
蔡树军
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract

本发明公开了一种提高栅控晶体管线性度的方法及其结构,涉及半导体器件技术领域;通过采用离子注入或挖槽技术实现沟道层上栅电极正下方区域沿栅电极的宽度方向沟道浓度单调递增,有效增加了栅控晶体管的线性度。本发明结构应用于栅控晶体管,相比于前馈法和功率回退法,简化了电路结构和体积,提高了栅控晶体管的输出功率和效率,方法简便,可靠性高。

Description

一种提高栅控晶体管线性度的方法及其结构
技术领域
本发明涉及半导体器件技术领域。
背景技术
近年来,无线通信技术飞速发展,极大的方便了人们的生活,推动了社会经济的发展。通信系统中的功率放大器在发送信号时会产生失真,容易导致相邻频段用户信号的干扰、频谱扩展、误码率恶化等。因此,提高功率放大器的线性度具有重要意义。目前,改善通信微波功率放大器线性度的常用方法是功率回退法和前馈法,功率回退法以牺牲功放的效率为代价,一般应用于对功率和线性度要求不高的情况。而前馈法需要采用辅助电路来提高线性度,结构较复杂,造价较高。
发明内容
本发明所要解决的技术问题是提供一种提高栅控晶体管线性度的方法及其结构,通过改变器件的材料结构有效增加栅控晶体管的线性度,且简化了电路结构和体积,提高了栅控晶体管的输出功率和效率,方法简便,可靠性高。
为解决上述技术问题,本发明所采取的技术方案是:
一种提高栅控晶体管线性度的方法,沟道层上栅电极正下方区域沿栅电极的宽度方向沟道浓度单调递增。
进一步的技术方案,采用离子注入或挖槽技术实现沟道层上栅电极正下方区域沿栅电极的宽度方向沟道浓度单调递增。
进一步的技术方案,所述沟道层上栅电极正下方区域沿栅电极的宽度方向沟道面密度在1×1012/cm-2~5×1013/cm-2范围内。
一种提高栅控晶体管线性度的结构,包括衬底层,衬底层上形成的沟道层,沟道层上从左至右依次形成的有源电极、栅介质和漏电极,栅介质上形成的栅电极,所述沟道层上栅电极正下方区域沿栅电极的宽度方向体掺杂浓度单调递增。
进一步的技术方案,采用离子注入或挖槽技术实现沟道层上栅电极正下方区域沿栅电极的宽度方向体掺杂浓度单调递增,沟道层的线性递增区域的面密度在1×1012/cm-2~5×1013/cm-2范围内。
进一步的技术方案,所述沟道层为Si、Ge、SiC、GaAs、金刚石或GaN,沟道层体掺杂浓度不小于5×1017cm-3,衬底层为Si、Ge、SiC、GaAs、金刚石、蓝宝石、SiO2或GaN。
进一步的技术方案,所述沟道层上栅电极正下方区域沿栅电极的宽度方向体掺杂浓度线性递增。
一种提高栅控晶体管线性度的结构,包括衬底层,衬底层上形成的缓冲层,缓冲层上形成的沟道层,沟道层上形成的势垒层,势垒层上从左至右依次形成有源电极、栅电极和漏电极,所述沟道层上栅电极正下方区域沿栅电极的宽度方向二维电子气浓度单调递增。
进一步的技术方案,采用离子注入或挖槽技术实现沟道层上栅电极正下方区域沿栅电极的宽度方向二维电子气浓度单调递增,沟道层的单调递增区域的面密度在1×1012/cm-2~5×1013/cm-2范围内。
进一步的技术方案,所述沟道层为GaN或者AlxGa1-xN(0<x<1),所述衬底层为Si、蓝宝石、SiC、GaN或金刚石,所述缓冲层为AlN、GaN、AlN和AlxGa1-xN(0<x<1)或者AlN和InxAl1-xN(0<x<1),所述势垒层为InxAlyGa1-x-yN(0≤x≤1,0≤y≤1,x+y≤1)。
采用上述技术方案所产生的有益效果在于:本发明通过离子注入或者挖槽技术实现沟道浓度沿栅宽方向单调变化,从而实现随着栅压的增加,沟道沿栅宽方向从高浓度到低浓度不断开启,漏电流的变化量基本保持不变,增加器件跨导的线性度。本发明结构应用于栅控晶体管,相比于前馈法和功率回退法,简化了电路结构和体积,提高了栅控晶体管的输出功率和效率,方法简便,可靠性高。
附图说明
图1是本发明实施例1、实施例2和实施例3的俯视图;
图2是本发明实施例1的剖面图;
图3是本发明实施例1和实施例3中沿图1栅宽方向AA’栅下沟道浓度分布示意图;
图4是本发明实施例2的剖面图;
图5是本发明实施例2中沿图1栅宽方向AA’栅下沟道浓度分布示意图;
图6是本发明实施例3的剖面图;
在附图中:1、源电极;2、栅电极;3、漏电极;4、沟道层;5、栅介质;6、衬底层;7、势垒层;8、缓冲层。
具体实施方式
下面结合附图和具体实施方式对本发明作进一步详细的说明。
一种提高栅控晶体管线性度的方法,沟道层4上栅电极2正下方区域沿栅电极2的宽度方向沟道浓度单调递增。采用离子注入或挖槽技术实现沟道层4上栅电极2正下方区域沿栅电极2的宽度方向沟道浓度单调递增。沟道层4上栅电极2正下方区域沿栅电极2的宽度方向沟道面密度在1×1012/cm-2~5×1013/cm-2范围内。
实施例1
如图2所示,一种提高栅控晶体管线性度的结构,包括衬底层6,衬底层6上形成的沟道层4,沟道层4上从左至右依次形成的源电极1、栅介质5和漏电极3,栅介质5上形成的栅电极2,沟道层4上栅电极2正下方区域沿栅电极2的宽度方向体掺杂浓度单调递增。如图1和图3所示,采用离子注入实现沟道层4上栅电极2正下方区域沿栅电极2的宽度AA’方向体掺杂浓度线性递增(浓度的增长率恒定),沟道层4的线性递增区域的面密度在1×1012/cm-2~5×1013/cm-2范围内。沟道层4体掺杂为Si、Ge、SiC、GaAs、金刚石或GaN,沟道层4体掺杂浓度不小于5×1017cm-3,衬底层6为Si、Ge、SiC、GaAs、金刚石、蓝宝石、SiO2或GaN。
实施例2
如图4所示,一种高线性场效应晶体管结构——高线性III族氮化物HEMT,包括衬底层6,衬底层6上形成的缓冲层8,缓冲层8上形成的沟道层4,沟道层4上形成的势垒层7,势垒层7上从左至右依次形成有源电极1、栅电极2和漏电极3,沟道层4上栅电极2正下方区域沿栅电极2的宽度方向二维电子气浓度单调递增。如图1和图5所示,采用离子注入或挖槽技术实现沟道层4上栅电极2正下方区域沿栅电极2的宽度AA’方向二维电子气浓度非线性递增(浓度的增长率不恒定),沟道层4的非线性递增区域的面密度在1×1012/cm-2~5×1013/cm-2范围内。沟道层4为GaN或者AlxGa1-xN(0<x<1),衬底层6为Si、蓝宝石、SiC、GaN或金刚石,缓冲层8为AlN、GaN、AlN和AlxGa1-xN(0<x<1)或者AlN和InxAl1-xN(0<x<1),势垒层7为InxAlyGa1-x-yN(0≤x≤1,0≤y≤1,x+y≤1)。
实施例3
如图6所示,一种提高栅控晶体管线性度的结构——高线性delta掺杂场效应管,包括衬底层6,衬底层6上形成的沟道层4,沟道层4上从左至右依次形成的源电极1、栅电极2和漏电极3,沟道层4上栅电极2正下方区域沿栅电极2的宽度方向delta掺杂浓度单调递增。如图6和图3所示,采用离子注入实现沟道层4上栅电极2正下方区域沿栅电极2的宽度AA’方向delta掺杂浓度线性递增,沟道层4的线性递增区域的面密度在1×1012/cm-2~5×1013/cm-2范围内。沟道层4为Si、Ge、SiC、GaAs、金刚石或GaN,沟道层4体掺杂浓度不小于5×1017cm-3,衬底层6为Si、Ge、SiC、GaAs、金刚石、蓝宝石、SiO2或GaN。
根据上述实施例的描述,本领域的普通技术人员还可做出一些显而易见的改变,例如选用本发明描述以外器件类型(如MOS-HEMT)等,但这些改变均应落入本发明权利要求的保护范围之内。

Claims (10)

1.一种提高栅控晶体管线性度的方法,其特征在于沟道层(4)上栅电极(2)正下方区域沿栅电极(2)的宽度方向沟道浓度单调递增。
2.根据权利要求1所述的一种提高栅控晶体管线性度的方法,其特征在于采用离子注入或挖槽技术实现沟道层(4)上栅电极(2)正下方区域沿栅电极(2)的宽度方向沟道浓度单调递增。
3.根据权利要求1所述的一种提高栅控晶体管线性度的方法,其特征在于所述沟道层(4)上栅电极(2)正下方区域沿栅电极(2)的宽度方向沟道面密度在1×1012/cm-2~5×1013/cm-2范围内。
4.一种提高栅控晶体管线性度的结构,包括衬底层(6),衬底层(6)上形成的沟道层(4),沟道层(4)上从左至右依次形成的有源电极(1)、栅介质(5)和漏电极(3),栅介质(5)上形成的栅电极(2),其特征在于所述沟道层(4)上栅电极(2)正下方区域沿栅电极(2)的宽度方向体掺杂浓度单调递增。
5.根据权利要求4所述的一种提高栅控晶体管线性度的结构,其特征在于采用离子注入或挖槽技术实现沟道层(4)上栅电极(2)正下方区域沿栅电极(2)的宽度方向体掺杂浓度单调递增,沟道层(4)的线性递增区域的面密度在1×1012/cm-2~5×1013/cm-2范围内。
6.根据权利要求4所述的一种提高栅控晶体管线性度的结构,其特征在于所述沟道层(4)为Si、Ge、SiC、GaAs、金刚石或GaN,沟道层(4)体掺杂浓度不小于5×1017cm-3,衬底层(6)为Si、Ge、SiC、GaAs、金刚石、蓝宝石、SiO2或GaN。
7.根据权利要求4所述的一种提高栅控晶体管线性度的结构,其特征在于所述沟道层(4)上栅电极(2)正下方区域沿栅电极(2)的宽度方向体掺杂浓度线性递增。
8.一种提高栅控晶体管线性度的结构,包括衬底层(6),衬底层(6)上形成的缓冲层(8),缓冲层(8)上形成的沟道层(4),沟道层(4)上形成的势垒层(7),势垒层(7)上从左至右依次形成有源电极(1)、栅电极(2)和漏电极(3),其特征在于所述沟道层(4)上栅电极(2)正下方区域沿栅电极(2)的宽度方向二维电子气浓度单调递增。
9.根据权利要求8所述的一种提高栅控晶体管线性度的结构,其特征在于采用离子注入或挖槽技术实现沟道层(4)上栅电极(2)正下方区域沿栅电极(2)的宽度方向二维电子气浓度单调递增,沟道层(4)的单调递增区域的面密度在1×1012/cm-2~5×1013/cm-2范围内。
10.根据权利要求8所述的一种提高栅控晶体管线性度的结构,其特征在于所述沟道层(4)为GaN或者AlxGa1-xN(0<x<1),所述衬底层(6)为Si、蓝宝石、SiC、GaN或金刚石,所述缓冲层(8)为AlN、GaN、AlN和AlxGa1-xN(0<x<1)或者AlN和InxAl1-xN(0<x<1),所述势垒层(7)为InxAlyGa1-x-yN(0≤x≤1,0≤y≤1,x+y≤1)。
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