CN104867830A - Method of manufacturing double diffusion metal-oxide-semiconductor (DMOS) device - Google Patents
Method of manufacturing double diffusion metal-oxide-semiconductor (DMOS) device Download PDFInfo
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- CN104867830A CN104867830A CN201410058122.6A CN201410058122A CN104867830A CN 104867830 A CN104867830 A CN 104867830A CN 201410058122 A CN201410058122 A CN 201410058122A CN 104867830 A CN104867830 A CN 104867830A
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Abstract
The present invention discloses a method of manufacturing a DMOS device, and relates to the semiconductor technology field. According to the present invention, by the adjustment of the steps, SRC photomasks are not needed, thereby reducing the number of the photomask sets in a DMOS device production technology, and reducing the production cost of the DMOS device.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of method making DMOS device.
Background technology
DMOS device and complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, CMOS) device architecture similar, the electrode such as also active, leakage, grid, but drain terminal puncture voltage is high.DMOS mainly contains two types, vertical double-diffusion metal-oxide-semiconductor field effect transistor VDMOSFET(vertical double-diffused MOSFET) and lateral double diffusion metal oxide semiconductor field effect transistor LDMOSFET(lateral double-dif fused MOSFET).
With reference to Fig. 1; in traditional DMOS device production process; usually employing six is needed to overlap light shield; be respectively make guard ring, active area, polysilicon layer, source electrode (SRC), contact hole and metal level time use; in figure; " Source " is the source port of DMOS device, the grid port that " Gate " is DMOS device, the drain terminal mouth that " Drain " is DMOS device.From the angle of technology, making SRC light shield is the shape in order to form source electrode (N+ region), final object makes source electrode follow the P well region in tagma (P-Body) (P+ region) to contact to form short-circuit structure, to improve the avalanche resistance breakdown capability of device, but because the cost of light shield is very high, and in traditional DMOS device production process, often overlap light shield all indispensable, cause the production cost of DMOS device very high.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is: how to reduce the light shield tricks in DMOS device production process, to reduce the production cost of DMOS device.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of method making DMOS device, said method comprising the steps of:
S1: grow gate oxide and polysilicon layer successively from top to bottom at the upper surface of epitaxial loayer;
S2: described polysilicon layer is adulterated, and the polysilicon layer after doping is etched, to form grid polycrystalline silicon;
S3: inject described epitaxial loayer, to form tagma;
S4: on the basis of previous step, carries out comprehensive injection of upper surface, to make to form N well region in described tagma;
S5: on the basis of previous step, carries out the dielectric layer deposition of upper surface;
S6: offer contact hole above described tagma, and adopted by described contact hole and dig silicon etching process the N well region in described tagma is dug along preset direction disconnected, described preset direction is the direction perpendicular to described tagma upper surface;
S7: inject from described contact hole, to form P well region, thus realizes the contact between N well region and P well region.
Wherein, also comprise before step S1:
S0: at the upper surface grown epitaxial layer of substrate.
Wherein, also comprise between step S0 and S1:
S001: superficial growth initial oxide layer on said epitaxial layer there;
S002: divest described initial oxide layer, to open active area.
Wherein, in step S1, described gate oxide and polysilicon layer are grown in described active area.
Wherein, in step S3, after described epitaxial loayer is injected, also comprise: annealing in process is carried out to described epitaxial loayer.
Wherein, in step S5, after carrying out the dielectric layer deposition of upper surface, also carry out reflow treatment.
Wherein, after step S7, also comprise:
S801: on the basis of previous step, carries out the Metal deposition of upper surface.
Wherein, in step S801, after carrying out Metal deposition, also carry out metal and return quarter.
Wherein, after step S7, also comprise:
S802: carry out Metal deposition at the lower surface of described substrate.
Wherein, also comprise before step S802: reduction processing is carried out to the lower surface of described substrate.
(3) beneficial effect
The present invention, by the adjustment of step, without the need to using SRC light shield, decreasing the light shield tricks in DMOS device production process, reducing the production cost of DMOS device.
Accompanying drawing explanation
Fig. 1 is the structural representation of DMOS device of the prior art;
Fig. 2 is the flow chart of the method for the making DMOS device of one embodiment of the present invention;
Fig. 3 is the schematic diagram of the 1st step in the method for the making DMOS device of an embodiment of the present invention;
Fig. 4 is the schematic diagram of the 2nd step in the method for the making DMOS device of an embodiment of the present invention;
Fig. 5 is the schematic diagram of the 3rd step in the method for the making DMOS device of an embodiment of the present invention;
Fig. 6 is the schematic diagram of the 4th step in the method for the making DMOS device of an embodiment of the present invention;
Fig. 7 is the schematic diagram of the 5th step in the method for the making DMOS device of an embodiment of the present invention;
Fig. 8 is the schematic diagram of the 6th step in the method for the making DMOS device of an embodiment of the present invention;
Fig. 9 is the schematic diagram of the 7th step in the method for the making DMOS device of an embodiment of the present invention;
Figure 10 is the schematic diagram that an embodiment of the present invention makes the 8th step in the method for DMOS device;
Figure 11 is the schematic diagram of the 9th step in the method for the making DMOS device of an embodiment of the present invention;
Figure 12 is the schematic diagram of the 10th step in the method for the making DMOS device of an embodiment of the present invention;
Figure 13 is the schematic diagram of the 11st step in the method for the making DMOS device of an embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
Fig. 2 is the flow chart of the method for the making DMOS device of an embodiment of the present invention; With reference to Fig. 2, the method for present embodiment comprises the following steps:
S1: grow gate oxide and polysilicon layer successively from top to bottom at the upper surface of epitaxial loayer;
S2: described polysilicon layer is adulterated, and the polysilicon layer after doping is etched, to form grid polycrystalline silicon;
S3: inject described epitaxial loayer, to form tagma;
S4: on the basis of previous step, carries out comprehensive injection of upper surface, to make to form N well region in described tagma;
S5: on the basis of previous step, carries out the dielectric layer deposition of upper surface;
S6: offer contact hole above described tagma, and adopted by described contact hole and dig silicon etching process the N well region in described tagma is dug along preset direction disconnected, described preset direction is the direction perpendicular to described tagma upper surface;
S7: inject from described contact hole, to form P well region, thus realizes the contact between N well region and P well region.
Preferably, also comprise before step S1:
S0: at the upper surface grown epitaxial layer of substrate.
Preferably, also comprise between step S0 and S1:
S001: superficial growth initial oxide layer on said epitaxial layer there;
S002: divest described initial oxide layer, with open active area (terminal structure position needs to leave initial oxide layer, for ease of describe, herein and subsequent step all eliminate terminal structure).
Preferably, in step S1, described gate oxide and polysilicon layer are grown in described active area.
For ensureing the effect injected, preferably, in step S3, after described epitaxial loayer is injected, also comprise: annealing in process is carried out to described epitaxial loayer.
For ensureing the density of dielectric layer, preferably, in step S5, after carrying out the dielectric layer deposition of upper surface, also carry out reflow treatment.
Preferably, after step S7, also comprise:
S801: on the basis of previous step, carries out the Metal deposition of upper surface.
For the source port in formation DMOS device and grid port, preferably, in step S801, after carrying out Metal deposition, also carry out metal and return quarter.
Preferably, after step S7, also comprise:
S802: carry out Metal deposition at the lower surface of described substrate.
For ensureing that the volume of DMOS device meets the requirements, preferably, also comprise before step S802: reduction processing is carried out to the lower surface of described substrate.
Embodiment
With a specific embodiment, manufacture method of the present invention is described below, but does not limit protection scope of the present invention.The manufacture method of the present embodiment comprises the following steps:
1, with reference to Fig. 3, at the upper surface grown epitaxial layer (" N-EPI " namely in figure) of substrate (" N+Sub " namely in figure), and initial oxide layer (" Int-OX " namely in figure) is grown at the upper surface of epitaxial loayer;
2, with reference to Fig. 4, divest initial oxide layer, open active area (terminal structure position needs to leave initial oxide layer, for ease of describing, herein and subsequent step all eliminate terminal structure);
3, with reference to Fig. 5, in the upper surface active area of described epitaxial loayer, grow gate oxide and polysilicon layer successively from top to bottom, and described polysilicon layer is adulterated;
4, with reference to Fig. 6, etch or photoetching the polysilicon layer after doping, to form grid polycrystalline silicon, PR is photoresistance;
5, with reference to Fig. 7, described epitaxial loayer is injected and annealing in process, to form tagma (" P-Body " namely in figure);
6, with reference to Fig. 8, on the basis of previous step, carry out comprehensive injection (SRC injects, and namely source electrode injects) and the annealing in process of upper surface, to make to form N well region (" N+ " region namely in figure) in described tagma, described N well region is the source electrode of DMOS unit;
7, with reference to Fig. 9, on the basis of previous step, dielectric layer deposition and the backflow of upper surface is carried out;
8, with reference to Figure 10, above described tagma, offer contact hole, and adopted by described contact hole and dig silicon etching process and dig along preset direction disconnected by the N well region in described tagma, described preset direction is the direction perpendicular to described tagma upper surface;
9, with reference to Figure 11, inject from described contact hole, to form P well region, thus realize the contact between N well region and P well region;
10, with reference to Figure 12, on the basis of previous step, the Metal deposition and the metal that carry out upper surface return quarter, and " Metal " in figure is metal level;
11, with reference to Figure 13, reduction processing is carried out to the lower surface of described substrate, Metal deposition is carried out at the lower surface of described substrate, the metal level that described " Ti-Ni-Ag " is the back side, " Source " is the source port of DMOS device, the grid port that " Gate " is DMOS device, the drain terminal mouth that " Drain " is DMOS device.
Above execution mode is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1. make a method for DMOS device, it is characterized in that, said method comprising the steps of:
S1: grow gate oxide and polysilicon layer successively from top to bottom at the upper surface of epitaxial loayer;
S2: described polysilicon layer is adulterated, and the polysilicon layer after doping is etched, to form grid polycrystalline silicon;
S3: inject described epitaxial loayer, to form tagma;
S4: on the basis of previous step, carries out comprehensive injection of upper surface, to make to form N well region in described tagma;
S5: on the basis of previous step, carries out the dielectric layer deposition of upper surface;
S6: offer contact hole above described tagma, and adopted by described contact hole and dig silicon etching process the N well region in described tagma is dug along preset direction disconnected, described preset direction is the direction perpendicular to described tagma upper surface;
S7: inject from described contact hole, to form P well region, thus realizes the contact between N well region and P well region.
2. the method for claim 1, is characterized in that, also comprises before step S1:
S0: at the upper surface grown epitaxial layer of substrate.
3. method as claimed in claim 2, is characterized in that, also comprise between step S0 and S1:
S001: superficial growth initial oxide layer on said epitaxial layer there;
S002: divest described initial oxide layer, to open active area.
4. method as claimed in claim 3, it is characterized in that, in step S1, described gate oxide and polysilicon layer are grown in described active area.
5. the method for claim 1, is characterized in that, in step S3, after injecting, also comprises: carry out annealing in process to described epitaxial loayer to described epitaxial loayer.
6. the method for claim 1, is characterized in that, in step S5, after carrying out the dielectric layer deposition of upper surface, also carries out reflow treatment.
7. the method for claim 1, is characterized in that, after step S7, also comprises:
S801: on the basis of previous step, carries out the Metal deposition of upper surface.
8. method as claimed in claim 7, is characterized in that, in step S801, after carrying out Metal deposition, also carry out metal and return quarter.
9. method as claimed in claim 2, is characterized in that, after step S7, also comprise:
S802: carry out Metal deposition at the lower surface of described substrate.
10. method as claimed in claim 9, is characterized in that, also comprise before step S802: carry out reduction processing to the lower surface of described substrate.
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| CN201410058122.6A CN104867830A (en) | 2014-02-20 | 2014-02-20 | Method of manufacturing double diffusion metal-oxide-semiconductor (DMOS) device |
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| CN201410058122.6A CN104867830A (en) | 2014-02-20 | 2014-02-20 | Method of manufacturing double diffusion metal-oxide-semiconductor (DMOS) device |
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Citations (5)
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|---|---|---|---|---|
| US4503598A (en) * | 1982-05-20 | 1985-03-12 | Fairchild Camera & Instrument Corporation | Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques |
| CN1161758A (en) * | 1994-09-01 | 1997-10-08 | 国际整流器公司 | Prodn. of MOS gated device with reduced mask count |
| US20020030233A1 (en) * | 1998-09-29 | 2002-03-14 | Sanyo Electric Co., Ltd. | Semiconductor device and a method of fabricating the same |
| CN101383287A (en) * | 2008-09-27 | 2009-03-11 | 电子科技大学 | Manufacturing method for vertical DMOS device |
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
-
2014
- 2014-02-20 CN CN201410058122.6A patent/CN104867830A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4503598A (en) * | 1982-05-20 | 1985-03-12 | Fairchild Camera & Instrument Corporation | Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques |
| CN1161758A (en) * | 1994-09-01 | 1997-10-08 | 国际整流器公司 | Prodn. of MOS gated device with reduced mask count |
| US20020030233A1 (en) * | 1998-09-29 | 2002-03-14 | Sanyo Electric Co., Ltd. | Semiconductor device and a method of fabricating the same |
| CN101383287A (en) * | 2008-09-27 | 2009-03-11 | 电子科技大学 | Manufacturing method for vertical DMOS device |
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
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