CN101447433B - Manufacturing method of double diffusion field effect transistor - Google Patents
Manufacturing method of double diffusion field effect transistor Download PDFInfo
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- CN101447433B CN101447433B CN200710094293A CN200710094293A CN101447433B CN 101447433 B CN101447433 B CN 101447433B CN 200710094293 A CN200710094293 A CN 200710094293A CN 200710094293 A CN200710094293 A CN 200710094293A CN 101447433 B CN101447433 B CN 101447433B
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Abstract
The invention discloses a manufacturing method of a double diffusion field effect transistor, comprising the following steps: a drift region of the transistor can form a gradient slope with certain dosage concentration in a channel direction (namely in transverse direction) and a direction vertical to the channel direction (namely in longitudinal direction) by increasing one selective ions injection process for forming a second drift region, so that the junctions of the whole transistor in the transverse direction and longitudinal direction have approximately equal breakdown voltages and the transistor will not be broken down with small voltages; furthermore, the saturation currents of the transistor can be increased by increasing the dosage concentration at the drift region with certain breakdown voltages.
Description
Technical field
The present invention relates to the manufacture of semiconductor technology, relate in particular to a kind of manufacturing method of double diffusion field effect transistor.
Background technology
For the conventional semiconductor process technique, bilateral diffusion field-effect tranisistor (Double DiffuseDrain MOS is called for short DDDMOS) is the high-voltage device structure of main flow, is widely used in chip for driving and power device.
As shown in Figure 1, in the prior art, all be to make double-diffused transistor as follows generally:
At first, on silicon substrate, carry out ion and inject the formation well region, in described well region, carry out the selectivity ion then and inject, form the drift region;
Then, growth one deck grid silicon oxide layer on well region;
The 3rd step, deposit one deck gate polysilicon layer on the magnificent silicon layer of described grid oxygen;
The 4th step, use known photoetching technique, described gate polysilicon layer is carried out etching, form transistorized grid;
The 5th step, carry out the selectivity source and leak the ion injection, form transistorized source electrode and drain electrode, at this moment the cross-section structure of formed double-diffused transistor is as shown in Figure 2.
Because the restriction of the method for above-mentioned common manufacturing double-diffused transistor, make to be difficult to obtain optimized result (promptly guarantee under certain puncture voltage, make saturation current reach maximum) between the saturation current of bilateral diffusion field-effect tranisistor and the puncture voltage.This mainly is because the transistor that above-mentioned common process manufacturing obtains, the dopant profiles of drift region (being horizontal direction) on channel direction does not have certain concentration gradient to change, specifically as shown in Figure 2, so when increasing the drift region doping content in order to improve saturation current when, the puncture voltage of the horizontal abrupt junction of device drift region will descend rapidly owing to the raising of drift region doping content, thereby make the puncture voltage of entire device descend rapidly.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of manufacturing method of double diffusion field effect transistor, can make the drift region (being on the longitudinal direction) on (promptly in a lateral direction) and vertical-channel direction on the channel direction of bilateral diffusion field-effect tranisistor can both form the gradient of certain doping content, thereby make device can under less voltage, just not puncture, also can satisfy under the certain breakdown-voltage simultaneously, can improve transistorized saturation current by the doping content that improves the drift region in assurance.
For solving the problems of the technologies described above, the invention provides a kind of manufacturing method of double diffusion field effect transistor, comprising:
Carrying out for the first time, the selectivity ion injects the operation that forms first drift region;
Form the operation of grid;
Form the operation of source electrode and drain electrode;
Also comprise: carrying out for the second time, the selectivity ion injects the operation that forms second drift region.
And the operation of described formation second drift region can be carried out between the operation of operation that forms first drift region and described formation grid, also can carry out between the operation of the operation that forms grid and described formation source electrode and drain electrode.
The present invention is owing to adopted technique scheme, has such beneficial effect, promptly by increasing the selectivity ion implantation process that once forms second drift region, thereby make transistorized drift region (being on the longitudinal direction) on (promptly in a lateral direction) and vertical-channel direction on the channel direction can form the gradient of certain doping content, make the knot of the horizontal and vertical direction of entire device have approximately equalised puncture voltage, thereby make device can under less voltage, just not puncture, also can satisfy under the certain breakdown-voltage simultaneously, can improve transistorized saturation current by the doping content that improves the drift region in assurance.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is a flow chart of making bilateral diffusion field-effect tranisistor in the prior art;
Fig. 2 is the structural representation according to the bilateral diffusion field-effect tranisistor of prior art manufacturing;
Fig. 3 is the flow chart of an embodiment of manufacturing method of double diffusion field effect transistor of the present invention;
Fig. 4 a-4c is according to the sectional structure chart in the described method manufacturing of Fig. 3 bilateral diffusion field-effect tranisistor process;
Fig. 5 is the flow chart of another embodiment of manufacturing method of double diffusion field effect transistor of the present invention;
Fig. 6 a-6d is according to the sectional structure chart in the described method manufacturing of Fig. 5 bilateral diffusion field-effect tranisistor process.
Embodiment
In one embodiment, as shown in Figure 3, the method for the invention may further comprise the steps:
The first step is carried out ion and is injected the formation well region on silicon substrate, be the N transistor npn npn if persons skilled in the art should be understood that the transistor that at this moment will make, and then the ion that at this moment need inject should be the boron ion; And if the transistor of making is the P transistor npn npn, then the ion that at this moment need inject should be phosphonium ion.
Second step, carry out the selectivity ion injection first time in the position of described silicon substrate well region, form first drift region, cross-section structure at this moment is shown in Fig. 4 a.One of ordinary skill in the art should be understood that then the ion that is at this moment injected should be phosphonium ion if the transistor that will make is the N transistor npn npn; And if the transistor that will make is the P transistor npn npn, then the ion that is at this moment injected should be the boron ion.
The 3rd step, carry out selectivity ion injection second time in the position of described silicon substrate well region, form second drift region, and described second drift region should encase by described first drift region fully, cross-section structure at this moment is shown in Fig. 4 b.If the transistor that will make is the N transistor npn npn, then the ion that is at this moment injected should be phosphonium ion; And if the transistor that will make is the P transistor npn npn, then the ion that is at this moment injected should be the boron ion.And, in this step, inject different and different that energy of ions and dosage should be according to actual conditions and requirement, for example, if the transistor that will make for the having relatively high expectations of puncture voltage, the dosage that then injects ion just should be less than normal; And if the transistor that will make is had relatively high expectations for saturation current, then injecting ion implantation dosage will be more higher; This should carry out suitable selection according to actual requirement for persons skilled in the art.
The 4th step, at silicon substrate grown on top one deck grid silicon oxide layer, deposit one deck gate polysilicon layer on described grid silicon oxide layer then.
The 5th step, use known photoetching technique, described gate polysilicon layer and grid silicon oxide layer are carried out etching, thereby form grid;
The 6th step, in described drift region, carry out the selectivity source and leak the ion injection, form source-drain electrode, finally form the transistor of cross-section structure shown in Fig. 4 c.
In another embodiment, the described selectivity ion injection second time forms the operation of second drift region and also can carry out later at the formation grid, and as shown in Figure 5, its concrete steps are as follows:
The first step is carried out ion and is injected the formation well region on silicon substrate, be the N transistor npn npn if persons skilled in the art should be understood that the transistor that at this moment will make, and then the ion that at this moment need inject should be the boron ion; And if the transistor of making is the P transistor npn npn, then the ion that at this moment need inject should be phosphonium ion.
Second step, carry out the selectivity ion injection first time in the position of described silicon substrate well region, form first drift region, cross-section structure at this moment is shown in Fig. 6 a.One of ordinary skill in the art should be understood that then the ion that is at this moment injected should be phosphonium ion if the transistor that will make is the N transistor npn npn; And if the transistor that will make is the P transistor npn npn, then the ion that is at this moment injected should be the boron ion.
The 3rd step, at silicon substrate grown on top one deck grid silicon oxide layer, deposit one deck gate polysilicon layer on described grid silicon oxide layer then.
The 4th step, use known photoetching technique, described gate polysilicon layer and grid silicon oxide layer are carried out etching, thereby form grid, cross-section structure at this moment is shown in Fig. 6 b;
The 5th step, carry out selectivity ion injection second time in the position of described silicon substrate well region, form second drift region, and described second drift region should encase by described first drift region fully, cross-section structure at this moment is shown in Fig. 6 c.If the transistor that will make is the N transistor npn npn, then the ion that at this moment need inject should be phosphonium ion; And if the transistor that will make is the P transistor npn npn, then the ion that at this moment need inject should be the boron ion.And, in this step, inject different and different that energy of ions and dosage should be according to actual conditions and requirement, for example, if the transistor that will make for the having relatively high expectations of puncture voltage, the dosage that then injects ion just should be less than normal; And if the transistor that will make is had relatively high expectations for saturation current, then injecting ion implantation dosage will be more higher; This should carry out suitable selection according to actual requirement for persons skilled in the art.
The 6th step, in described drift region, carry out the selectivity source and leak the ion injection, form source-drain electrode, finally form the transistor of cross-section structure shown in Fig. 6 d.
By above-mentioned two embodiment as can be seen, owing on silicon substrate, carried out the drift region ion implantation process twice, therefore make transistorized first drift region and second drift region on (being horizontal direction) and vertical-channel direction on the channel direction (being on the longitudinal direction) form the gradient of certain doping content, the knot of the horizontal and vertical direction of entire device will have approximately equalised puncture voltage like this, thereby make device can under less voltage, just not puncture, also can satisfy under the certain breakdown-voltage in assurance simultaneously, the doping content that improves the drift region improves transistorized saturation current.
Claims (5)
1. manufacturing method of double diffusion field effect transistor comprises:
Carrying out for the first time, the selectivity ion injects the operation that forms first drift region;
Form the operation of grid;
Form the operation of source electrode and drain electrode;
It is characterized in that, also comprise: carry out the operation that selectivity ion injection for the second time forms second drift region, first drift region and polysilicon gate have overlapping, and source electrode and drain electrode all drop in second drift region.
2. according to the described manufacturing method of double diffusion field effect transistor of claim 1, it is characterized in that the operation of described formation second drift region is carried out between the operation of operation that forms first drift region and described formation grid.
3. according to the described manufacturing method of double diffusion field effect transistor of claim 1, it is characterized in that the operation of described formation second drift region is carried out between the operation of the operation that forms grid and described formation source electrode and drain electrode.
4. according to claim 2 or 3 described manufacturing method of double diffusion field effect transistor, it is characterized in that in the operation of described formation second drift region, if the transistor that will make is the N transistor npn npn, then the ion that is injected should be phosphonium ion; And if the transistor that will make is the P transistor npn npn, then the ion that is injected should be the boron ion.
5. according to claim 2 or 3 described manufacturing method of double diffusion field effect transistor, it is characterized in that the dosage that injects ion in the operation of described formation second drift region depends on the specific requirement to puncture voltage and saturation current of the transistor that will make.
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| CN103151391B (en) * | 2013-03-18 | 2015-08-12 | 北京大学 | The short grid tunneling field-effect transistor of vertical non-uniform doped channel and preparation method |
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| CN1815757A (en) * | 2005-01-18 | 2006-08-09 | 夏普株式会社 | Lateral double-diffused mos transistor and manufacturing method therefor |
| US7233018B2 (en) * | 2004-11-17 | 2007-06-19 | Electronics And Telecommunications Research Institute | High voltage MOSFET having Si/SiGe heterojuction structure and method of manufacturing the same |
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| US7233018B2 (en) * | 2004-11-17 | 2007-06-19 | Electronics And Telecommunications Research Institute | High voltage MOSFET having Si/SiGe heterojuction structure and method of manufacturing the same |
| CN1815757A (en) * | 2005-01-18 | 2006-08-09 | 夏普株式会社 | Lateral double-diffused mos transistor and manufacturing method therefor |
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| JP特开2001-15734A 2001.01.19 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
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