CN205488139U - Trench gate surpasses knot MOSFET device - Google Patents

Abstract

The utility model provides a trench gate surpasses knot MOSFET device, including a plurality of cellulars, the cellular includes N+ type substrate, do it have N to grow on the N+ type substrate the type epitaxial layer, does the N+ type substrate back precipitate the drain electrode that the drain electrode metal formed the MOSFET device, at the N of cellular type epitaxial layer both sides are formed with P type post deep groove structure downwards from the top, N at the cellular type epitaxial layer top intermediate formation has trench gate, be formed with lateral wall bars oxygen structure in trench gate 's side, trench gate 's bottom is formed with buried layer bars oxygen structure, N at the cellular be formed with P type tagma between type epitaxial layer top trench gate 's lateral wall bars oxygen structure and the P type post deep groove structure, and P type tagma top is formed with N+ type source region, P type tagma and P type post deep groove structure top are formed with the P+ type district that is used for the contact, is the source electrode metal deposit at N type epitaxial layer top has the dielectric layer to keep apart between source electrode metal and the trench gate. The utility model discloses conducting resistance is little, and is adjustable during the gate -drain capacitance preparation.

Description

Groove grid super node MOSFET device

Technical field

This utility model relates to a kind of semiconductor device, a kind of high pressure MOSFET element.

Background technology

Current existing common VDMOS device is as it is shown in figure 1, include N+ type substrate 1, N-type epitaxial layer 2 (N-epi), gate oxide 4, polysilicon gate 5 (Poly Gate), PXing Ti district 6(Pbody)；Common VDMOS device is wanted to improve pressure, needs more high resistivity, thicker N-type epitaxial layer 2, but so can increase the conducting resistance of MOS device greatly；

Existing planar gate superjunction MOS device is as in figure 2 it is shown, include N+ type substrate 1, N-type epitaxial layer 2 (N-epi), p-type post deep groove structure 3(P pillar trench), gate oxide 4, polysilicon gate 5 (Poly Gate), PXing Ti district 6(Pbody)；By introducing deep trouth Trench structure at device inside, it is possible to achieve horizontal p-type post/N-type epitaxial layer exhausts, so can just realize the highest pressure, and reduce conducting resistance under the N-type epitaxial layer of very low-resistivity；Traditional planar gate super node MOSFET, because the JFET region existed between PXing Ti district 6, can increase conducting resistance.And limit due to channel length etc., be difficult to reduce device size further.

Summary of the invention

For the deficiencies in the prior art, this utility model provides a kind of groove grid super node MOSFET device, uses trench gate structure, shields JFET effect completely, and the degree of depth of trench gate can regulate when making, thus changes channel length and junction capacity.The technical solution adopted in the utility model is:

A kind of groove grid super node MOSFET device, including multiple cellulars, described cellular includes that N+ type substrate, N+ type Grown have N-type epitaxial layer；N+ type substrate back deposit drain metal forms the drain electrode of MOSFET element,

It is formed with p-type post deep groove structure from top down in the N-type epitaxial layer both sides of cellular；

N-type epitaxial layer crown center at cellular is formed with trench gate, and trench gate is as the grid of MOSFET element；

Being formed with sidewall gate oxygen structure in the side of trench gate, the bottom of trench gate is formed with buried regions gate oxygen structure；

It is formed with PXing Ti district between sidewall gate oxygen structure and the p-type post deep groove structure of the N-type epitaxial layer top channel grid of cellular；Top, QiePXing Ti district is formed with N+ type source region；PXing Ti district is formed with the P+ type contact area for contacting with p-type post deep groove structure top；

Source metal is deposited on N-type epitaxial layer top, is connected with p-type post deep groove structure, PXing Ti district and N+ type source region, forms the source electrode of MOSFET element；Dielectric layer is had to isolate between source metal and trench gate.

Further, the thickness of described buried regions gate oxygen structure is more than the thickness of sidewall gate oxygen structure.

Further, trench gate is filled with polysilicon.

Advantage of the present utility model: the gate oxygen structure in this utility model trench gate is innovation, wherein conventional sidewall grid oxygen is just used to the control carrying out grid to raceway groove, but introduce buried regions grid oxygen bottom gate trench, it is thicker than sidewall grid oxygen, thus regulate gate leakage capacitance, and the switching characteristic of optimised devices.Specifically have an advantage that

1) p-type post deep groove structure forms superjunction with N-type extension interlayer, can reduce conducting resistance；

2) trench gate structure is different from traditional planar gate structure, it is also possible to reduce conducting resistance；

3) trench gate medial wall grid oxygen and buried regions gate oxide thickness are inconsistent, can regulate gate leakage capacitance.

Accompanying drawing explanation

Fig. 1 is existing VDMOS device structural representation.

Fig. 2 is existing planar gate superjunction MOS device structural representation.

Fig. 3 is that p-type post deep groove structure of the present utility model etches schematic diagram.

Fig. 4 is that p-type post deep groove structure of the present utility model fills schematic diagram.

Fig. 5 is that gate trench of the present utility model etches schematic diagram.

Fig. 6 is growth oxide layer schematic diagram in gate trench of the present utility model.

Fig. 7 is that gate trench oxide layer of the present utility model etches and formed buried regions gate oxygen structure schematic diagram.

Fig. 8 is that gate trench sidewalls of the present utility model growth oxide layer forms sidewall gate oxygen structure schematic diagram.

Fig. 9 is that gate trench polysilicon of the present utility model deposits and formed trench gate structure schematic diagram.

Figure 10 is that formation ChengPXing Ti district and N+ type source region schematic diagram are injected in N-type epitaxial layer top of the present utility model.

Figure 11 is somatomedin layer of the present utility model etch media layer formation contact hole schematic diagram.

Figure 12 is that deposit source metal of the present utility model forms source electrode schematic diagram.

Detailed description of the invention

Below in conjunction with concrete drawings and Examples, the utility model is described in further detail.

First the present embodiment introduces the manufacture method of groove grid super node MOSFET device, eventually forms required super-junction MOSFET device structure.

Groove grid super node MOSFET device, inside comprises many cellulars, and the present embodiment respectively schemes to be depicted as the structure of a cellular.

Step one, as shown in Figure 3, it is provided that N+ type substrate 1, on N+ type substrate 1, growth has N-type epitaxial layer 2；Formation deep groove structure 3 ' is performed etching from top down in N-type epitaxial layer 2 both sides of cellular；

Step 2, as shown in Figure 4, at deep groove structure 3 ' middle epitaxial growth p type impurity layer, carries out the fill process of deep groove structure 3 ', forms p-type post deep groove structure 3；This structure is the most pressure for super node MOSFET；

Step 3, as it is shown in figure 5, carry out the etching of gate trench 5 ', channel length as required and junction capacity at N-type epitaxial layer 2 crown center of cellular, can be controlled the gate trench 5 ' degree of depth；

Step 4, as shown in Figure 6, utilizes the mode of hot oxide growth or deposit, at gate trench 5 ' growth inside filling oxide layer 4；

Step 5, as it is shown in fig. 7, utilize etchback (Etchback) technique, etches away the oxide layer of gate trench 5 ' internal upper part, leaves behind the oxide layer of bottom, form buried regions gate oxygen structure 42, and junction capacity as required regulates the thickness of buried regions gate oxygen structure 42；

Step 6, as shown in Figure 8, utilizes dry oxide growth technique, forms relatively thin sidewall gate oxygen structure 41 at gate trench 5 ' sidewall, thus realizes the grid control to raceway groove；

Step 7, as it is shown in figure 9, carry out deposit and the etching of polysilicon in gate trench 5 ', forms the structure of trench gate 5；

Step 8, as shown in Figure 10, between sidewall gate oxygen structure 41 and the p-type post deep groove structure 3 of the N-type epitaxial layer 2 top channel grid of cellular, first carry out p type impurity injection diffuse to form PXing Ti district 6(Pbody), the injection then carrying out N+ type impurity diffuses to form N+ type source region 7；

Step 9, as shown in figure 11, at N-type epitaxial layer 2 grown on top dielectric layer 9, in dielectric layer 9, etching forms contact hole 91 (contact hole i.e. contact), and contact hole 91 is directed at p-type post deep groove structure 3, PXing Ti district 6 and part N+ type source region 7；Contact hole 91 can be with etch away sections N-epi-layer surface；In contact hole 91, carry out the injection of P+ type impurity, form P+ type contact area；It should be noted that in Figure 11 and Figure 12, all there is distribution P+ type contact area in PXing Ti district 6 and p-type post deep groove structure 3 top；The P+ type contact area at p-type post deep groove structure 3 top is not drawn into；

Step 10, as shown in figure 12, at N-type epitaxial layer 2 deposited on top source metal 8, source metal 8 filling contact hole 91, and is connected with p-type post deep groove structure 3, PXing Ti district 6 and N+ type source region 7；Form the source electrode of device；Dielectric layer 9 is had to isolate between source metal 8 and trench gate 5.

Finally carry out the thinning back side of device, form the drain electrode of MOSFET element in N+ type substrate 1 back side deposit drain metal.

By above-mentioned processing step, defining groove grid super node MOSFET device of the present utility model, including multiple cellulars, described cellular includes N+ type substrate 1, and on N+ type substrate 1, growth has N-type epitaxial layer 2；N+ type substrate 1 back side deposit drain metal forms the drain electrode of MOSFET element；

It is formed with p-type post deep groove structure 3 from top down in N-type epitaxial layer 2 both sides of cellular；

N-type epitaxial layer 2 crown center at cellular is formed with trench gate 5, and trench gate 5 is as the grid of MOSFET element；

Be formed with sidewall gate oxygen structure 41 in the side of trench gate 5, the bottom of trench gate 5 is formed with buried regions gate oxygen structure 42；

It is formed with PXing Ti district 6 between sidewall gate oxygen structure 41 and the p-type post deep groove structure 3 of the N-type epitaxial layer 2 top channel grid of cellular；Top, QiePXing Ti district 6 is formed with N+ type source region 7；PXing Ti district 6 is formed with the P+ type contact area for contacting with p-type post deep groove structure 3 top；

Source metal 8 is deposited on N-type epitaxial layer 2 top, is connected with p-type post deep groove structure 3, PXing Ti district 6 and N+ type source region 7；Dielectric layer 9 is had to isolate between source metal 8 and trench gate 5.

Preferably, the thickness of described buried regions gate oxygen structure 42 is more than the thickness of sidewall gate oxygen structure 41.

Claims (3)

1. a groove grid super node MOSFET device, including multiple cellulars, described cellular includes that the upper growth of N+ type substrate (1), N+ type substrate (1) has N-type epitaxial layer (2)；N+ type substrate (1) back side deposit drain metal forms the drain electrode of MOSFET element, it is characterised in that:

It is formed with p-type post deep groove structure (3) from top down in N-type epitaxial layer (2) both sides of cellular；

N-type epitaxial layer (2) crown center at cellular is formed with trench gate (5), and trench gate (5) is as the grid of MOSFET element；

Be formed with sidewall gate oxygen structure (41) in the side of trench gate (5), the bottom of trench gate (5) is formed with buried regions gate oxygen structure (42)；

It is formed with PXing Ti district (6) between sidewall gate oxygen structure (41) and p-type post deep groove structure (3) of N-type epitaxial layer (2) the top channel grid of cellular；QiePXing Ti district (6) top is formed with N+ type source region (7)；PXing Ti district (6) is formed with the P+ type contact area for contacting with p-type post deep groove structure (3) top；

Source metal (8) is deposited on N-type epitaxial layer (2) top, is connected with p-type post deep groove structure (3), PXing Ti district (6) and N+ type source region (7), forms the source electrode of MOSFET element；Dielectric layer (9) is had to isolate between source metal (8) and trench gate (5).

2. groove grid super node MOSFET device as claimed in claim 1, it is characterised in that:

The thickness of described buried regions gate oxygen structure (42) is more than the thickness of sidewall gate oxygen structure (41).

3. groove grid super node MOSFET device as claimed in claim 1, it is characterised in that:

Trench gate is filled with polysilicon in (5).