CN104810283B - A kind of igbt chip manufacturing method suitable for compression joint type encapsulation - Google Patents
A kind of igbt chip manufacturing method suitable for compression joint type encapsulation Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 230000006835 compression Effects 0.000 title claims abstract description 32
- 238000007906 compression Methods 0.000 title claims abstract description 32
- 238000005538 encapsulation Methods 0.000 title claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 230000008569 process Effects 0.000 claims abstract description 7
- 230000012010 growth Effects 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 238000001459 lithography Methods 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 229910000838 Al alloy Inorganic materials 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 238000005289 physical deposition Methods 0.000 claims description 5
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 238000005234 chemical deposition Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
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- 230000000694 effects Effects 0.000 description 2
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- 238000012545 processing Methods 0.000 description 2
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- 229910020776 SixNy Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 238000002161 passivation Methods 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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- 108010063955 thrombin receptor peptide (42-47) Proteins 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical group O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention relates to a kind of igbt chip manufacturing methods suitable for compression joint type encapsulation, including choose silicon substrate and pre-process to the silicon substrate；Field oxide growth is carried out in the surface of silicon, and the field oxide is performed etching；Manufacturing gate oxide layers and polygate electrodes；Make p-well and N trap；Make Spacer, P+ type doped region and N+ type doped region；Front electrode EM2 is formed above the polygate electrodes；Front electrode EM1 is formed on the outside of the front electrode EM2；P+ collecting zone is formed at the silicon substrate back side；Make the rear electrode C.Technical solution provided by the invention is low to craft precision requirement, and saves flow cost.
Description
Technical field:
The present invention relates to power electronic devices fields, are more particularly to a kind of igbt chip system suitable for compression joint type encapsulation
Make method.
Background technique:
Compression joint type IGBT structure form does not need chip weldering derived from the packing forms of the conventional power devices such as thyristor, GTO
It connects, avoids the binding of lead, it is possible to reduce the parasitic inductance of circuit；Compression joint type IGBT module can be with two-side radiation, and radiate effect
Rate is higher, better reliability；It is easy to connect based on compression joint type IGBT module, equipment voltage class can be improved, this characteristic, pressure
The formula module of connecing is widely used in extra-high voltage (HVDC), static reactive power compensation (SVC), multi-electrical level inverter etc.；Furthermore compression joint type
The short circuit failure mode of IGBT module makes power grid more stable, is increasingly used in transmission and disttrbution, and industrial motor drives
The dynamic or pulse power.Compression joint type IGBT module has widened the application field of welded type IGBT module.Consider in compression joint type application
Igbt chip needs to bear pressure (between 8-65kN), this pressure can have an impact chip structure and then influence its electricity spy
Property, therefore special designing need to be made for the igbt chip for being applied to compression joint type encapsulation, reduce influence of the pressure to electrical characteristics to the greatest extent.
General method is to increase metal thickness on traditional igbt chip front electrode in the world at present, increases by one layer of soft metal (one
As use Ag or Al and Al alloy), using metal ductility to chip stress rise certain buffer function.From conventional half
It from semiconductor process processing flow, can choose there are two types of scheme: first, carrying out secondary metals after the completion of metal electrode
Deposit, photoetching process, metal etch complete but such method needs first to grow one layer of corruption before second layer metal deposit
Lose barrier layer (generally SixNy), it needs to increase by one of photoetching process, chip manufacture cycle stretch-out, processing cost is caused to increase；
Second, directly depositing thick metal, completed by Twi-lithography technique, metal etch, but since metal etch is usually wet
The thickness of method etching, double layer of metal is not easy to control, and craft precision is more demanding.
Summary of the invention:
The object of the present invention is to provide a kind of igbt chip manufacturing methods suitable for compression joint type encapsulation, want to craft precision
It asks low, and saves flow cost；Influence of the pressure to MOS channel is effectively reduced, ensure that the electrical characteristics of IGBT.
To achieve the above object, the invention adopts the following technical scheme: a kind of igbt chip suitable for compression joint type encapsulation
Manufacturing method, comprising:
It chooses silicon substrate and the silicon substrate is pre-processed；
Field oxide growth is carried out in the surface of silicon, and the field oxide is performed etching；
Manufacturing gate oxide layers and polygate electrodes；
Make p-well region and N well region；
Make Spacer, P+ type doped region and N+ type doped region；
Front electrode EM2 is formed above the polygate electrodes；
Front electrode EM1 is formed on the outside of the front electrode EM2；
P+ collecting zone is formed at the silicon substrate back side；
Make the rear electrode C.
A kind of igbt chip manufacturing method suitable for compression joint type encapsulation provided by the invention, the silicon substrate are uniformly to mix
Miscellaneous n type single crystal silicon substrate；The pretreatment is to be chemically treated to its surface.
A kind of igbt chip manufacturing method suitable for compression joint type encapsulation provided by the invention, the thickness of the field oxide
1000-1500 nanometers.
Another preferred a kind of igbt chip manufacturing method suitable for compression joint type encapsulation provided by the invention, the production
Gate oxide and polygate electrodes include: to carry out high-temperature oxydation to the n type single crystal silicon substrate of Uniform Doped, so that the silicon serves as a contrast
Bottom surface grows oxidation film, forms gate oxide, and use deposit mode growing polycrystalline silicon, then formed by lithography and etching
Polygate electrodes.
Another preferred a kind of igbt chip manufacturing method suitable for compression joint type encapsulation provided by the invention, the production
P-well region and N well region include:
Opening injecting p-type doping to the polygate electrodes that the gate oxide is formed, then carry out high annealing knot
P-well region is formed, p-well region carries out n-type doping after being formed and injects to form N trap.
Another preferred a kind of igbt chip manufacturing method suitable for compression joint type encapsulation provided by the invention, the production
Spacer includes；Oxidation film is grown by deposit mode, anti-carves to form Spacer comprehensively；The production P+ type doped region and N+ type
Doped region includes；After the Spacer is formed, P+ doping is implanted sequentially using self-registered technology and N+ is adulterated, forms P+ type doping
Area and N+ type doped region.
Another preferred a kind of igbt chip manufacturing method suitable for compression joint type encapsulation provided by the invention, described more
Front electrode EM2 is formed above crystal silicon gate electrode includes；Boron phosphorus doping glass film quality is grown by chemical deposition mode, uses object
Reason deposit or evaporation mode grow aluminium alloy, carry out the lithography and etching of metal, form front electrode EM2.
It is provided by the invention it is another it is preferred it is a kind of suitable for compression joint type encapsulation igbt chip manufacturing method, it is described just
It includes: to carry out lithography and etching to the boron phosphorus doping glass film quality to form contact that front electrode EM1 is formed on the outside of the electrode EM2 of face
Hole grows aluminium alloy on the isolating oxide layer and EM2 using sputtering mode, etches 50 angstroms to EM2 backwash before sputtering,
Then the lithography and etching of metal is carried out again, forms front electrode EM1.
Another preferred a kind of igbt chip manufacturing method suitable for compression joint type encapsulation provided by the invention, in the silicon
It includes: that the silicon substrate grinding back surface is thinned that substrate back, which forms P+ collecting zone, and then wet etching is cleaned, in the silicon wafer
The back side is generated using the impurity that ion implanting mode carries out P+ current collection region, then carries out annealing process, carry out the activation of ion with
Knot, knot to required depth.
Another preferred a kind of igbt chip manufacturing method suitable for compression joint type encapsulation provided by the invention, the production
Rear electrode C includes: to form back metal electrode using physical deposition or evaporation, completes the connection of chip back electrical characteristics.
Compared with the nearest prior art, the technical scheme provide by that invention has the following excellent effect:
1, technical solution of the present invention utilizes the extension of metal by being further added by one layer of metal Al on chip front side electrode
Property to chip stress rise certain buffer function；
2, technical solution of the present invention double layer of metal is formed using two secondary growth Twi-lithographies, and double layer of metal etches intermediate nothing
Etching barrier layer is needed, low, one of photolithography plate of saving, saving flow cost are required craft precision；
3, using field oxide that the metal layer above one's respective area is padded above the area technical solution of the present invention JFET, it is pressure
The main part of the force of formula encapsulation chip is connect, distance MOS channel has certain distance (about 10-12 μm), effectively reduces pressure
Influence to MOS channel；
4, technical solution of the present invention avoids pressure from ensure that the electrical characteristics of IGBT to the influence of IGBT electrical characteristics.
Detailed description of the invention
Fig. 1 is that compression joint type of the invention encapsulates igbt chip stress diagram；
Fig. 2 is the igbt chip vertical section schematic diagram for being suitable for compression joint type encapsulation of the invention；
Wherein, 1-N type monocrystalline silicon piece substrate, 2- field oxide, 3- gate oxide, 4- polygate electrodes, 5-P well region,
6-N well region, 7-Spacer structure, 8-P+ type doped region, 9-N+ type doped region, 10- isolating oxide layer, 11- front metal electrode
EM2,12- front metal electrode EM1,13-P+ collecting zone, the area 14- back metal electrode C, 15-JFET.
Specific embodiment
Below with reference to embodiment, the invention will be described in further detail.
Embodiment 1:
A kind of igbt chip manufacturing method suitable for compression joint type encapsulation that the invention of this example provides, including as shown in Fig. 2,
(1) doping concentration of n type single crystal silicon piece substrate 1, substrate N impurity needs to be hit according to different from substrate thickness
Wearing voltage and forward conduction voltage drop demand, (600V to 6500V) select and the works such as is cleaned by ultrasonic by acid, alkali, deionized water
Sequence is chemically treated silicon face.
(2) growth of field oxide 2 and etching: using the method for high-temperature oxydation, oxide layer, thickness are grown in silicon chip surface
1000-1500nm, growth carry out photoetching, wet etching after completing, and the gentler oxide layer etching angle the better, and final angle is about
It is 30 °, field oxygen is open 10-12 μm away from polycrystalline.
(3) chip plane gate oxide 3 and 4 structure of polygate electrodes are made: to the n type single crystal silicon piece of Uniform Doped
Substrate 1 carries out the mode of high-temperature oxydation, forms grid oxygen in the oxidation film that silicon chip surface grows about 0.1 micron to 0.2 micron
Change layer 3, and use deposit mode growing polycrystalline silicon, then 4 structure of polygate electrodes is formed by photoetching, etching.
(4) chip p-well 5,6 structure of N trap are made: p-type doping is carried out by injection mode to polygate electrodes opening,
High annealing knot is carried out again and forms p-well 5, and p-well carries out N-type after being formed and injects to form N trap 6.
(5) chip surface P+ type doped region 8,9 structure of N+ type doped region are made: oxidation film being grown by deposit mode, entirely
Face anti-carves to form Spacer7 structure, successively carries out P+ doping, N+ doping using autoregistration ion implanting mode, forms P+ type and mix
Miscellaneous area 8, N+ type doped region 9.
(6) it makes chip front side electrode EM211 structure: growing boron phosphorus doping glass film quality using chemical deposition mode, make
Aluminium alloy is grown with physical deposition or evaporation mode, with a thickness of 4-10 μm, the lithography and etching of metal is carried out, forms front electrode
EM211 structure.
(7) it makes chip front side metal electrode EM112 structure: carrying out the photoetching of contact hole to boron phosphorus doping glass film quality
10 structure of isolating oxide layer is formed with etching, plays grid source buffer action, 10 structure of isolating oxide layer uses sputtering mode after being formed
Aluminium alloy is grown, the 50 Izods right side is etched to EM2 backwash before sputtering, to remove the oxidation film on surface, it secondly can be by table
Face feather plucking keeps the adhesiveness of double layer of metal more preferable, then carries out the lithography and etching of metal again, forms front metal electrode
EM112 structure.Welding window is opened using lithography and etching mode using deposit and coating method growth of passivation layer, to guarantee
Emitter, the polygate electrodes of chip front side are electrically connected, and complete the connection of chip front side electrode.
(8) it makes 13 structure of chip back P+ collecting zone: grinding back surface being carried out to the silicon substrate for finishing above step and is subtracted
Thin, then wet etching is cleaned, and is generated in silicon chip back side using the impurity that ion implanting mode carries out P+ current collection region, then carry out
Annealing process carries out activation and the knot of ion, knot to required depth, in 0.5 micron to 1 micron range.
(9) it makes chip back metal electrode C14 structure: back metal electrode C14 is formed using physical deposition or evaporation
Structure completes the connection of chip back electrical characteristics.
The igbt chip includes: n type single crystal silicon piece substrate 1, setting field oxide 2 on the silicon substrate and grid oxygen
Change layer 3, the polygate electrodes 4 being arranged on the gate oxide 3, the isolation from oxygen being arranged on the polygate electrodes 4
The front metal electrode EM112 for changing layer 10 and being arranged on the isolating oxide layer 10；The isolating oxide layer 10 with it is described
Front metal electrode EM211 is set between front metal electrode EM112.
The thickness 1000-1500nm of the field oxide 2, opening of the field oxide 2 apart from polygate electrodes 4
10-12μm.The igbt chip further includes the area JFET being arranged in below the field oxide 2.The polygate electrodes 4
Opening is equipped with p-well region 5；5 surface of p-well region is equipped with N well region 6；Spacer7 is equipped with above the N well region 6.The p-well
Area 5 is additionally provided with P+ type doped region 8 and N+ type doped region 9.The back side of the silicon substrate is equipped with P+ collecting zone 13.The P+ collecting zone
13 lower section is equipped with back metal electrode C14.The front metal electrode EM211 is aluminium alloy, with a thickness of 4-10 μm.
In this application, the field oxide above the area JFET is padded by the metal layer above one's respective area, is compression joint type encapsulation
The main part of the force of middle chip, as shown in Figure 1；Due to JFET offset from MOS channel have with a certain distance from (about 10-12 μm), pressure
Influence very little of the power stress to MOS channel, effectively reduces influence of the pressure to MOS channel；Double layer of metal uses two secondary growths
Twi-lithography is formed, and double layer of metal etching is intermediate to be not necessarily to etching barrier layer, saves one of photolithography plate, this scheme wants craft precision
It asks low, saves flow cost.
Finally it should be noted that: the above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, institute
The those of ordinary skill in category field is although should be understood with reference to the above embodiments: still can be to a specific embodiment of the invention
It is modified or replaced equivalently, these are without departing from any modification of spirit and scope of the invention or equivalent replacement, in Shen
Within claims of the invention that please be pending.
Claims (6)
1. a kind of igbt chip manufacturing method suitable for compression joint type encapsulation, it is characterised in that: include:
It chooses silicon substrate and the silicon substrate is pre-processed；
Field oxide growth is carried out in the surface of silicon, and the field oxide is performed etching；
Manufacturing gate oxide layers and polygate electrodes；
Make p-well region and N well region；
Make Spacer, P+ type doped region and N+ type doped region；
Front electrode EM2 is formed above the polygate electrodes；
Front electrode EM1 is formed on the outside of the front electrode EM2；
P+ collecting zone is formed at the silicon substrate back side；
Make the rear electrode C；
It includes: to carry out lithography and etching to boron phosphorus doping glass film quality that front electrode EM1 is formed on the outside of the front electrode EM2
Contact hole is formed, grows aluminium alloy on isolating oxide layer and EM2 using sputtering mode, EM2 backwash is etched before sputtering
50 angstroms, the lithography and etching of metal is then carried out again, forms front electrode EM1；
The silicon substrate is the n type single crystal silicon substrate of Uniform Doped；The pretreatment is to be chemically treated to its surface；
1000-1500 nanometers of the thickness of the field oxide；
Front electrode EM2 is formed above the polygate electrodes includes；Boron phosphorus doping glass is grown by chemical deposition mode
Glass film quality grows aluminium alloy using physical deposition or evaporation mode, carries out the lithography and etching of metal, forms front electrode EM2.
2. a kind of igbt chip manufacturing method suitable for compression joint type encapsulation as described in claim 1, it is characterised in that: described
Manufacturing gate oxide layers and polygate electrodes include: to carry out high-temperature oxydation to the n type single crystal silicon substrate of Uniform Doped, so that described
The silicon chip surface of silicon substrate grows oxidation film, forms gate oxide, and use deposit mode growing polycrystalline silicon, then pass through photoetching
Polygate electrodes are formed with etching.
3. a kind of igbt chip manufacturing method suitable for compression joint type encapsulation as claimed in claim 2, it is characterised in that: described
Production p-well region and N well region include:
Opening injecting p-type doping to the polygate electrodes, then carry out high annealing knot and form p-well region, p-well region is formed
N-type doping is carried out afterwards to inject to form N trap.
4. a kind of igbt chip manufacturing method suitable for compression joint type encapsulation as described in claim 1, it is characterised in that: described
Making Spacer includes；Oxidation film is grown by deposit mode, anti-carves to form Spacer comprehensively；The production P+ type doped region and
N+ type doped region includes；After the Spacer is formed, P+ doping is implanted sequentially using self-registered technology and N+ is adulterated, forms P+ type
Doped region and N+ type doped region.
5. a kind of igbt chip manufacturing method suitable for compression joint type encapsulation as described in claim 1, it is characterised in that: in institute
Stating the silicon substrate back side and forming P+ collecting zone includes: that the silicon substrate grinding back surface is thinned, and then wet etching is cleaned, described
The silicon substrate back side is generated using the impurity that ion implanting mode carries out P+ current collection region, then carries out annealing process, carries out ion
Activation and knot, knot to required depth.
6. a kind of igbt chip manufacturing method suitable for compression joint type encapsulation as described in claim 1, it is characterised in that: described
Production rear electrode includes: to form back metal electrode using physical deposition or evaporation, completes the connection of chip back electrical characteristics.
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| CN106601799A (en) * | 2015-10-20 | 2017-04-26 | 上海联星电子有限公司 | Crimping-type IGBT device |
| CN107644810B (en) * | 2016-07-20 | 2024-05-31 | 全球能源互联网研究院 | Front electrode processing method of crimping IGBT/FRD chip |
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