GB2482479A - Semiconductor device operable as a vertical MOSFET and as a lateral insulated gate bipolar transistor, comprising a Schottky diode in the injector region. - Google Patents

Semiconductor device operable as a vertical MOSFET and as a lateral insulated gate bipolar transistor, comprising a Schottky diode in the injector region. Download PDF

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GB2482479A
GB2482479A GB1012951.8A GB201012951A GB2482479A GB 2482479 A GB2482479 A GB 2482479A GB 201012951 A GB201012951 A GB 201012951A GB 2482479 A GB2482479 A GB 2482479A
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region
conductivity type
injector
semiconductor
drift region
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GB2482479B (en
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Peter Ward
Philip Mawby
Martin Westmoreland
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University of Warwick
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University of Warwick
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Priority to GBGB1107979.5A priority patent/GB201107979D0/en
Priority to PCT/GB2011/051413 priority patent/WO2012017227A1/en
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    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Abstract

A semiconductor device operable as a vertical metal oxide semiconductor field effect transistor and a lateral insulated gate bipolar transistor is disclosed. The device comprises a semiconductor substrate (2, fig 1)) of a first conductivity type, a drift region 3 of the first conductivity type disposed on the semiconductor substrate (2, fig 1), a body region 12 of a second, opposite conductivity type disposed within the drift region 3 and a source region 15 of the first conductivity type disposed within the body region 12. The device further comprise a minority-carrier injector which comprises an injector region (131) of the second conductivity type disposed within the drift region 3 and laterally separated from the body region 12, the injector region and the drift region forming a p-n junction 201 and a metallic electrode 193 in contact with the drift region, laterally adjacent and electrically connected to the injector region. The metallic electrode and the drain region form a Schottky diode 21 in parallel with the p-n junction 201. The Schottky diode may have a barrier height of 0.7eV and may comprise a metallic electrode including a layer of platinum silicide. The semiconductor device may be based on silicon carbide, or other elemental compounds such as GaN.

Description

Semiconductor device
Description
The present invention relates to a semiconductor device and more specifically to a semiconductor device operable as a vertical metal oxide semiconductor field effect transistor (MOSFET) and a lateral insulated gate bipolar transistor (IGBT).
In a vertical MOSFET, current flows vertically between a source having one conductivity type and a substrate drain of the same conductivity type. The MOSFET operates based on the flow of only majority carriers through the drift region.
An IGBT has a similar structure to a vertical MOSFET, but differs in that the drain is of the opposite conductivity type. Thus, both majority and minority carriers are injected into the drift region. This has the effect of reducing the ON resistance of the IGBT compared to the MOSFET, but also has the effect of increasing the gate switching speed.
A form of vertical MOSFET device has been proposed in which a MOSFET is provided with a minority carrier injector in the form of a p-type region which forms a p-n junction with the n-type drift region so increase switching speed and reduce the ON resistance. Reference is made to "A novel trench-injector power device with low ON resistance and high switching speed", David K. Y. Liu and James D. Plummet, IEEE Electron Device Letters, volume 9, Issue 7, pages 321 -323 (1988) and "Design and analysis of a new conductivity-modulated power MOSFET", David K. Y. Liu and James D. Plummet, IEEE Transactions on Electron Devices, volume 40, Issue 2, pages 428 -438 (1993).
The device has a drawback of needing to control separately an additional terminal.
However, this can be avoided by connecting the injector to the drain. However, this arrangement presents a problem, namely that when the same bias is applied to the injector and drain, no voltage difference develops across the p-n junction and so no minority carrier injection occurs. In particular, a small voltage difference initially develops due to differing resistances between the source and the drain and the source and the injector. However, the differences in resistance are soon compensated by low-level minority carrier injection and so the effect stops.
An alternative approach is to form a hybrid vertical DMOS/lateral IGBT device and reference is made to "A new hybrid VDMOS-LIGBT transistor" T. Paul Chow & B. Jayant Baliga, IEEE Electron Device Letters, volume 9, pages 473 -475 (1988).
This device comprises two devices in parallel, namely a p-channel vertical MOSFET DMOSFET and a p-channel lateral IGBT. However, the hybrid device needs external resistors to bias the device and, since the resistors are fixed, bipolar action is not optimized.
In lateral MOSFET devices, it has been proposed to inject minority carriers using a Schottky contact and reference is made to "The SINFET -A Schottky injection MOS-gated power transistor", Johnny K. 0. Sin, C. Andre T. Salama and Li-Zhang Hou, IEEE Transactions on Electron Devices, volume ED-33, page 1940-1947 (1986).
However, the number of injected minority carriers is low. Thus, although conductivity can be modulated using minority carriers, the device falls well short of achieving full IGBT-like bipolar action.
The present invention seeks to provide an improved semiconductor device.
According to the present invention there is provided a semiconductor device operable as a vertical metal oxide semiconductor field effect transistor and a lateral insulated gate bipolar transistor, the device comprising a semiconductor substrate drain of a first conductivity type, a drift region of the first conductivity type disposed on the semiconductor substrate drain, a body region of a second, opposite conductivity type disposed within the drift region, a source region of the first conductivity type disposed within the body region. The device further comprises a minority-carrier injector which comprises an injector region of the second conductivity type disposed within the drift region and laterally separated from the body region, the injector region and the drift region forming a p-n junction, and a metallic electrode in contact with the drift region laterally adjacent to and electrically connected to the injector region, the metallic electrode and the drain region forming a Schottky diode in parallel with the p-n junction.
Thus, the Schottky diode helps to ensure that the p-n junction is forward biased and continues to the inject minority carriers into the drift region. Therefore, the device provides an integrated vertical metal oxide semiconductor field effect transistor and lateral insulated gate bipolar transistor.
The first and second conductivity types may be n-type and p-type respectively.
The body region and the substrate may be vertically separated by a first given distance and the body region and the injector region are laterally separated by a second given distance exceeding equal to or greater than the first given distance.
The second given distance may be about 6 to 12 m.
The device may further comprise a depletion reducing region comprising a semiconductor of the first conductivity type disposed within the drift region, more highly doped than the drift region and disposed between the body region and the injector region. This can help reduce the lateral size of the device.
The body region and the substrate may be vertically separated by a first given distance and the body region and the injector region are laterally separated by a second given distance less than the first given distance.
The Schottky diode may have a barrier height equal to or greater than 0.7 eV. The metallic electrode may include a layer of platinum suicide forming the Schottky diode.
The metallic electrode and the semiconductor substrate may be coupled so as to be at substantially the same potential. The device may comprise a further, different metallic electrode in contact with the source region.
The drift region may comprise comprises silicon. Alternatively, the drift region may comprise silicon carbide semiconductor. The drift region, the body region, the source region and the injector region may comprise the same semiconductor.
According to a second aspect of the present invention there is provided an integrated circuit comprising at least one semiconductor device.
According to a third aspect of the present invention there is provided a method of fabricating a semiconductor device operable as a vertical metal oxide semiconductor field effect transistor and a lateral insulated gate bipolar transistor, the method comprising providing a drift region of first conductivity type on a semiconductor substrate of the first conductivity type, forming a body region of a second, opposite conductivity type within the drift region, forming a source region of the first conductivity type within the body region, forming an injector region of the second conductivity type within the drift region, laterally separated from the body region, wherein the injector region and the drift region provide a p-n junction; and providing a metallic electrode in contact with the drift region laterally adjacent and electrically connected to the injector region, wherein the metallic electrode and the drain region provide a Schottky diode in parallel with the p-n junction.
The body region and the substrate may be vertically separated by a first given distance and wherein forming the injector region within the drift region comprises laterally separating the injector region from the body region by a second given distance exceeding the first given distance.
The device may further comprise a depletion reducing region comprising a semiconductor of the first conductivity type disposed within the drift region, more highly doped than the drift region and disposed between the body region and the injector region.
The body region and the substrate may be vertically separated by a first given distance and the body region and the injector region are laterally separated by a second given distance less than the first given distance.
According to a fourth aspect of the present invention there is provided a method of operating a semiconductor device operable as a vertical metal oxide semiconductor field effect transistor and a lateral insulated gate bipolar transistor, wherein the device comprises a semiconductor substrate of a first conductivity type, a drift region of the first conductivity type disposed on the semiconductor substrate, a body region of a second, opposite conductivity type disposed within the drift region, a source region of the first conductivity type disposed within the body region, an injector region of the second conductivity type disposed within the drift region and laterally separated from the body region, the injector region and the drift region forming a p-n junction and a metallic electrode in contact with the drift region laterally adjacent and electrically connected to the injector region, the metallic electrode and the drain region forming a Schottky diode in parallel with the p-n junction, the method comprising, grounding the source region and applying a given bias to the metallic electrode and the substrate.
Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a vertical section of an embodiment of a semiconductor device in accordance with the present invention; Figure la is more detailed view of the semiconductor device shown in Figure 1; Figure 2 illustrates a set of mask layers used to fabricate the semiconductor device shown in Figure 1; Figure 3 is a vertical section of the semiconductor device shown in Figure 1 illustrating operation; Figure 4 schematically illustrates the behaviour of the semiconductor device shown in Figure 1; and Figures 5a to 5p are vertical sections through the semiconductor device shown in Figure 1 at different stages during fabrication.
Referring to Figures 1, la and 2, an embodiment of a power semiconductor device in accordance with the present invention is shown. The semiconductor device takes the form of a hybrid silicon n-channel vertical metal oxide semiconductor field effect transistor and insulated gate bipolar transistor device 1. The transistor 1 is configured to permit injection of both majority and minority carriers into a drift region.
The transistor I includes a heavily-doped n-type monocrystalline silicon substrate 2 which functions as a drain region. An epitaxial layer 3 of lightly-doped n-type monocrystalline silicon (herein also referred to as the "drift region") is arranged on an upper surface 4 of the substrate 2. A field oxide 5 is located at an upper surface of the epitaxial layer 3 and has first and second windows 6, 62 defining first and second laterally-separated upper surfaces 2 of the epitaxial layer 3. The first and second windows 6, 62 have lengths 1, l of about 6 m and 4.8 m respectively and are separated by a length, 13, of about 7 m.
A gate oxide 8 is disposed within the first window 6 on the upper surface of the epitaxial layer 3. The gate oxide 8 runs along the upper surface of the epitaxial layer 3 and abuts the field oxide 5 thereby forming a step 9. A layer of heavily-doped n-type polycrystalline silicon 10 (which may also be referred to as the "gate poly") is disposed on the gate oxide 8 and runs over the step 9 onto the field oxide 5. Silicon dioxide spacers 11 ate formed on the sides of the gate poiy 10.
A p-type body 12 comprising a lightly-doped p-type diffusion well is disposed within the epitaxial layer 3 at the first upper surface As shown in Figure la, the p-type body extends laterally under the spacer 11 and the gate oxide 8.
First and second p-type injectors 13, 132 in the form of heavily-doped p-type diffusion wells are located within the epitaxial layer 3 at the second upper surface The p-type injectors 13k, 132 are spaced apart to leave a region 14 of the n-type epitaxial layer 3 extending up to the second upper surface 2 of the epitaxial layer 3.
An n-type source region 15 in the form of a heavily-doped n-type diffusion well is disposed within the p-type body 12 at the upper surface A p-type body short (not shown) in the form of a heavily-doped p-type diffusion well is also provided at the first upper surface using a body short mask (Figure 2).
A layer 17 of silicon dioxide runs over the gate poly 10 and the field oxide 5, and has windows 18, 182, 183. Layers of 19, 192, 193 of metallization are disposed on the silicon dioxide layer 17 covering windows 18k, 182, 183. The first metallisation layer 19 provides a source/emitter terminal S, the second metallisation layer 192 provides a gate terminal G and the third metallisation layer 19 provides a collector/injector terminal I. The metallization layers 19k, 192, 193 each comprise a -hi-layer comprising a high-barrier metal suicide base layer comprising, for example, platinum silicide (PtSi), and a high-conductivity overlayer comprising, for example, aluminium (Al).
As shown in Figure la, the third metallisation layer 193 is in contact with the first and second p-type injectors 13k, 132 and the n-type region 14 between the p-type injectors 13, 132. The p-type injectors 13k, 132 form respective p-n junctions 20k, 202 with the epitaxial layer 3 and the metallisation layer 193 forms a Schottky diode 21 with the epitaxial layer 3. Thus, the pair of p-n junctions 20k, 202 and the Schottky diode 21 are arranged in parallel between the metallisation layer 193 and the epitaxial layer 3.
The high-barrier metal silicide forms a Schottky diode with the epitaxial layer 3, but forms ohmic contacts to the heavily-doped injector and source regions 13k, 132, 15.
As shown in Figure 1, an inner edge 22 of the p-type body 12 and an inner edge 23 of the p-type injector 13 which is closest to the p-type body 12 are separated by a length, L. A bottom 24 of the p-type body 12 is separated from the highly-doped substrate 2 by a depth, d. The length, L, approximately equals the depth, d, i.e. L d, to maintain the breakdown voltage of the device. The separation length, L, and the depth, d, are about 8 m. As will be explained later, the length, L, can be smaller, if a highly-doped field stop region is used.
Also as shown in Figure 1, a source-drain depletion region 25 having an edge 26 is formed in the epitaxial layer 3 due to the junction between the p-type body 12 and the n-type epitaxial layer 3. As will be explained in more detail later, the transistor 1 is arranged so that, in blocking mode, the edge 26 of the depletion region 25 does not reach the inner edge 23 of the first injector 13k.
Referring also to Figures 3 to 5, operation of the transistor 1 will now be described.
The transistor 1 is arranged so that the source S is grounded and that the drain D and injector I are connected together to a positive voltage Vd. The gate G is used to control the transistor 1 and if a voltage Vg is applied to the gate G and the voltage exceeds a threshold voltage Vh, then current flows through the transistor 1 from the source region 15 into the epitaxial region 3.
The transistor 1 can simultaneously provide an integrated vertical metal oxide semiconductor field effect transistor and lateral insulated gate bipolar transistor.
At low Vd, most of the current (which comprises majority carriers, i.e. electrons) flows to the drain D with a few percent of the total current bled through the injector I. Thus, the transistor 1 operates in a similar way to a conventional vertical MOSFET.
As d increases, the total current increases and the current, I, bled through the injector I also increases. The Schottky diode 21 biases a region 28 beneath the p-type injectors 13k, 132 below Vd and, thus, forward biases the p-n junctions 20k, 202.
Thus, minority carriers are injected into the epitaxial layer 3 thereby reducing the ON-resistance. Thus, the transistot 1 starts to imitate operation of a conventional IGBT.
The Schottky diode 21 helps to dynamically bias the p-n junctions 20, 202 and ensure that the p-n junctions 20, 202 continue to inject minority carriers into the epitaxial region 3 at higher Vd unlike, for example, an ohmic resistor. If an ohmic resistor is used instead of the Schottky diode, then the p-n junctions 20, 202 would initially be forward biased. However, once this occurs, the resistivity of the epitaxial region would drop, resulting in less current bleed and, thus, reduce the injection of minority carriers.
The amount of current bleed can be altered depending on the choice of metallisation (which varies the barrier height), the area of the Schottky diode and the operating point of Schottky diode 21. A barrier height of at least 0.7 eV is preferred. For example, the metallization may be platinum suicide with an aluminium overlayer.
The geometry and dimensions of the transistor 1 are chosen so that the depletion layer 25 arising from junction between the p-type body region 12 and the epitaxial layer 3 does not touch the depletion layer arising from the closest p-n junction 20k.
If the depletion layer should touch, then the p-n junction 20 would be strongly forward biased and the device would break down catastrophically. Thus, although the injector works better the closer it is to the p-type body region 12, the lateral extent of the depletion layer 25 in blocking mode sets a minimum lateral separation, L. For silicon, for the dimensions given earlier, the transistor 1 has a breakdown voltage of about 120 V. An array (not shown) of vertical DMOS transistors I and bond pads (not shown) can be implemented in a chip having an area of about 3.3 mm2 and can support 10 A of current comprising majority carriers and 70 A of current comprising majority and minority carriers. For silicon carbide, for the dimensions given earlier, the transistor 1 has a breakdown voltage of about 1000 V. Referring to Figures 1, la, 2 and 5a to 5p, a method of fabricating the semiconductor device 1 will now be described.
Referring in particular to Figures 1 and 2, the device 1 is fabricated using a succession of masks including an active area mask for defining the extent of the field oxide 5, a gate poly mask for defining the extent of the gate poly 10, a p-body -10 -mask for defining the p-body well 12, an n-source mask for defining the n-source well 15, a body short mask for defining a body short (not shown), a contact mask for defining openings in the silicon dioxide layer 17 and a metal mask for defining metallization 19, 192, 193.
Referring in particular to Figure 5a, a layer 3' of lightly-doped n-type monocrystalline silicon is grown epitaxially on a highly-doped n-type monocrystalline substrate 2. The epitaxial layer 3' is doped i/i-situ during growth with arsenic or antimony to a concentration of about 5 xlO'5 cm3 and has a thickness of about 8 m.
Referring in particular to Figure 5b, a field oxide 5 is formed at the surface 7' (Figure 5a) of the epitaxial layer 3' (Figure 5a) by thermal oxidation using a LOGOS process. The field oxide 5 has thickness of about 1 pm.
As shown in Figure 5b, the field oxide 5 has first and second windows 6, 62 defining first and second laterally-separated upper surfaces 2 of the epitaxial layer 3.
Referring in particular to Figure 5c, a layer 8' of silicon dioxide is grown by thermal oxidation on the upper surfaces 7, 2 of the epitaxial layer 3. The silicon dioxide layer 8' has a thickness of about 1,500 A. Referring in particular to Figure 5d, a layer 10' of heavily-doped n-type polycrystalline silicon is grown by chemical vapour deposition (CVD) over the silicon dioxide layer 8' and field oxide 5. The polyctystalline layer 10' is doped in-situ during growth with phosphorous or arsenic to a concentration equal to or greater than about I x 1020 cm3 and has a thickness of about 3,000 A. Instead of in-situ doping, an undoped polycrystalline layer 10' can be grown and doped by ion implantation after growth.
A layer (not shown) of photoresist is applied over the polycrystalline layer 10' and is patterned to form a mask (not shown). The mask pattern is transferred to the -11 -underlying polycrystalline layer 10' and silicon dioxide layer 8' by reactive ion etching (RIE) using suitable feed gases.
Referring in particular to Figure 5e, the resulting structure includes the gate poiyiO and gate oxide 8.
Referring in particular to Figure 5f, with the mask (not shown) still in place, a further layer (not shown) of photoresist is applied and patterned so as to protect the epitaxial layer 3 in the second window 62. Boron ions are implanted at an energy between about 20 to 160 keV.
Referring to Figure 5g, the masks (not shown) are removed and the structure is annealed to activate the implant leaving a p-type well 12 doped to a concentration of between about 1 x1017 cm3 and about 5 x108 cm3 and having a depth of about 0.7 to 1.2 rim.
Referring to Figure 5h, a conformal layer (not shown) of silicon dioxide is deposited and globally etched back by RIE using suitable feed gases to form a spacer 11 around the sides of the gate poiy 10.
Referring in particular to Figure 5i, a layer (not shown) of photoresist is applied and patterned so as to protect the epitaxial layer 3 in the second window 62. Arsenic ions are implanted into the epitaxial layer 3 in the first window 6 at an energy of about 40 keV.
Referring to Figure 5j, the mask (not shown) is removed and the structure is annealed to activate the implant leaving an n-type well 15 doped to a concentration of between about I x102° cm3 and about 3 x102° cm3 and having a depth of about 1,000 A to 5,000 A. Referring to Figure 5k, a layer (not shown) of photoresist is applied and patterned to open a small hole over the first window 6 and two narrow windows (not shown) -12 -over the second window 62. Boron ions are implanted into the epitaxial layer 3 in the second window 62 at an energy of about 40 keV.
Referring to Figure 51, the mask (not shown) is removed and the structure is annealed to activate the implant leaving an p-type body short 16 (Figure 2) and p-type injectors 13k, 132 doped to a concentration of between about I x102° cm3 and about 3 x102° cm3 and having a depth of about 1,000 A to 5,000 A. Referring to Figure 5m, another layer 17' of silicon dioxide having a thickness of about 4,000 A. A layer (not shown) of photoresist is applied over the silicon dioxide layer 17' and is patterned to form a mask (not shown). The mask pattern is transferred to the underlying silicon dioxide layer 17' by RIE using suitable feed gases.
Referring in particular to Figure 5n, the resulting structure includes a patterned silicon dioxide layer 17 with contact windows 18, 182, 183.
Referring to Figure 5o, the mask (not shown) is removed and a layer 19' of a first metallization layer comprising platinum is deposited by physical vapour deposition (PYD). The metallization is annealed using one or more rapid thermal anneals (RTA). Unreacted platinum is removed using aqua regia. A second metallization layer comprising aluminium is deposited by PVD having a thickness of about 10,000 A. A layer (not shown) of photoresist is applied over the metallization 19' and is patterned to form a mask (not shown). The mask pattern is transferred to the underlying metallization 19' by RIE using suitable feed gases.
Referring in particular to Figure 5p, the resulting structure comprises metallization contacts 19k, 192, 193.
-13 -It will be appreciated that the fabrication process can include other steps, such as substrate thinning and depositing a metallization on the back side of the substrate.
It will be appreciated that many modifications may be made to the embodiments hereinbefore described.
The semiconductor device may be a p-channel device. Thus, the drift region, the body region, the source region and injector regions may take the form of a lightly-doped p-type semiconductor material, lightly-doped n-type semiconductor material, heavily-doped p-type semiconductor material and heavily-doped n-type semiconductor material respectively. Thus, the majority carriers may be holes instead of electrons and the minority carriers may be electrons instead of holes.
The semiconductor device may be based on silicon carbide. For example, the substrate may comprise 4H or 3C polytypes. The drift region and the body, source and injector regions may comprise silicon carbide, Other elemental or compound semiconductors, such as GaN, can be used.
A shallow n-type diffusion well may be inserted between p-type body region 12 and the p-type injectors 13, 132 to restrict the depletion layer width laterally and improve performance of the lateral PNP transistor. This "field stop" can be used to reduce the length, L, from about 8 tm to about 4 m.
Other metallizations can be used to provide the high Schottky barrier.
Processing steps and process parameters may be altered and optimised. For example, doping concentrations, dopant ions, ion-implant energies can be varied.
Methods of deposition and methods of etching can also be varied. Also, dielectric materials can be altered. For example, silicon dioxide need not be used and can be replaced, for example, by silicon oxynitride or high_k dielectrics.

Claims (16)

  1. -14 -Claims 1. A semiconductor device operable as a vertical metal oxide semiconductor field effect transistor and a lateral insulated gate bipolar transistor, the device comprising: a semiconductor substrate of a first conductivity type; a drift region comprising a semiconductor of the first conductivity type disposed on the semiconductor substrate; a body region comprising a semiconductor of a second, opposite conductivity type disposed within the drift region; a source region comprising a semiconductor of the first conductivity type disposed within the body region; the device further comprising: a minority-carrier injector which comprises: an injector region comprising a semiconductor of the second conductivity type disposed within the drift region and laterally separated from the body region, the injector region and the drift region forming a p-n junction; and a metallic electrode in contact with the drift region laterally adjacent and electrically connected to the injector region, the metallic electrode and the drain region forming a Schotticy diode in parallel with the p-n junction.
  2. 2. A device according to claim 1, wherein the body region and the substrate are vertically separated by a first given distance and the body region and the injector region are laterally separated by a second given distance equal to or greater than the first given distance.
  3. 3. A device according to claim 2, wherein the second given distance is about 6 to 12 rim.
  4. 4. A device according to claim 1, further comprising: a depletion reducing region comprising a semiconductor of the first conductivity type disposed within the drift region, more highly doped than the drift region and disposed between the body region and the injector region.
    -15 -
  5. 5. A device according to claim 4, wherein the body region and the substrate are vertically separated by a first given distance and the body region and the injector region are laterally separated by a second given distance less than the first given distance.
  6. 6. A device according to any preceding claim, wherein the Schottky diode has a barrier height equal to or greater than 0.7 eV.
  7. 7. A device according to any preceding claim, wherein the metallic electrode include a layer of platinum suicide forming the Schottky diode.
  8. 8. A device according to any preceding claim, wherein the metallic electrode and the semiconductor substrate are coupled so as to be at the same potential.
  9. 9. A device according to any one of claims 1 to 8, wherein the drift region comprises silicon.
  10. 10. A device according to any one of claims 1 to 8, wherein the drift region comprises silicon carbide semiconductor.
  11. 11. An integrated circuit comprising at least one semiconductor device according to any preceding claim.
  12. 12. A method of fabricating a semiconductor device operable as a vertical metal oxide semiconductor field effect transistor and a lateral insulated gate bipolar transistor, the method comprising: providing a drift region of first conductivity type on a semiconductor substrate of the first conductivity type; forming a body region of a second, opposite conductivity type within the drift region; forming a source region of the first conductivity type within the body region; forming an injector region of the second conductivity type within the drift -16 -region, laterally separated from the body region, wherein the injector region and the drift region provide a p-n junction; and providing a metallic electrode in contact with the drift region laterally adjacent and electrically connected to the injector region, wherein the metallic electrode and the drain region provide a Schottky diode in parallel with the p-n junction.
  13. 13. A method according to claim 12, wherein the body region and the substrate are vertically separated by a first given distance and wherein forming the injector region within the drift region comprises laterally separating the injector region from the body region by a second given distance exceeding the first given distance.
  14. 14. A device according to claim 12, further comprising: a depletion reducing region comprising a semiconductor of the first conductivity type disposed within the drift region, more highly doped than the drift region and disposed between the body region and the injector region.
  15. 15. A device according to claim 14, wherein the body region and the substrate are vertically separated by a first given distance and the body region and the injector region are laterally separated by a second given distance less than the first given distance.
  16. 16. A method of operating a semiconductor device operable as a vertical metal oxide semiconductor field effect transistor and a lateral insulated gate bipolar transistor, wherein the device comprises a semiconductor substrate of a first conductivity type, a drift region of the first conductivity type disposed on the semiconductor substrate, a body region of a second, opposite conductivity type disposed within the drift region, a source region of the first conductivity type disposed within the body region, an injector region of the second conductivity type disposed within the drift region and laterally separated from the body region, the injector region and the drift region forming a p-n junction and a metallic electrode in contact with the drift region laterally adjacent and electrically connected to the injector region, the metallic electrode and the drain region forming a Schottky diode -17 -in parallel with the p-n junction, the method comprising: grounding the source region; and applying a given bias to the metallic electrode and the substrate.
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