CN104766920A - 一种大功率led驱动芯片的sop8封装引线框架 - Google Patents

一种大功率led驱动芯片的sop8封装引线框架 Download PDF

Info

Publication number
CN104766920A
CN104766920A CN201510038815.3A CN201510038815A CN104766920A CN 104766920 A CN104766920 A CN 104766920A CN 201510038815 A CN201510038815 A CN 201510038815A CN 104766920 A CN104766920 A CN 104766920A
Authority
CN
China
Prior art keywords
dao
chip
sop8
island
led driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510038815.3A
Other languages
English (en)
Inventor
姜喆
姜英伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangzhou Microtronics Of China AS
Original Assignee
Guangzhou Microtronics Of China AS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Microtronics Of China AS filed Critical Guangzhou Microtronics Of China AS
Priority to CN201510038815.3A priority Critical patent/CN104766920A/zh
Publication of CN104766920A publication Critical patent/CN104766920A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

本发明公开了一种大功率LED驱动芯片的SOP8封装引线框架，包括引脚、侧连筋、第一基岛和第二基岛，1个引脚与2个侧连筋共同支撑起第一基岛及第二基岛，第一基岛的宽度尺寸比SOP8封装基岛的标准宽度尺寸大，第二基岛的宽度尺寸比SOP8封装基岛的标准宽度尺寸小。本发明增加了第一基岛最大承载的MOSFET芯片尺寸，除了适用于3-9W内置隔离式LED驱动芯片的封装外，也适用于12-24W内置隔离式的LED驱动芯片，适用范围广；相应扩大了第一基岛的承载面积，散热性能好；对MOSFET芯片无特别要求，成本较低；只需占用1个引脚，扩展性较好。本发明可广泛应用于半导体器件领域。

Description

一种大功率LED驱动芯片的SOP8封装引线框架
技术领域
本发明涉及半导体器件领域，尤其是一种大功率LED驱动芯片的SOP8封装引线框架。
背景技术
SOP8的封装是一种非常普及的小型贴片式形式,它被目前的半导体芯片封装所普遍采用。SOP8封装形式只是DIP8封装形式的占用面积的2/5,而且,PCB板焊接时,SOP8封装这一贴片式封装有着DIP8插入式封装无以比拟的优势和效率。SOP8封装形式与DIP8封装形式的关键尺寸简要对比图如图1所示。
内置隔离式的LED驱动芯片需要把一个IC控制芯片和一个耐压650V的MOSFET芯片封装在一个SOP8或一个DIP8的封装形式内，功率越大的LED驱动芯片须要封入的MOSFET芯片的开启阻抗(Rdson)就越低，MOSFET芯片的开启阻抗越低也就意味芯片的面积就越大。
如图2和图3所示，现有的SOP8封装引线框架采用了两个对等的双基岛式设计，由于承载MOSFET芯片的基岛2及3的尺寸为2.77x2.05mm（2.05mm即为SOP8封装基岛的标准宽度尺寸），再加上粘片的银胶在贴片时式的四面溢出宽度通常至少为5mil(即0.125mm),因此留给MOSFET芯片的宽度尺寸为1.80mm。目前业界的3-9W内置隔离式的LED驱动芯片通常采用1N65NC系列的VDMOSFET芯片，这个系列的芯片尺寸在1.80x1.80mm的尺寸范围内，没有超出1.80mm的宽度尺寸，因此目前3-9W小功率内置隔离式的LED驱动芯片均采用SOP8的封装形式。但是，12-15W内置隔离式的LED驱动芯片须要采用一个2N65NC或3N65NC的VDMOSFET芯片，这两种芯片的尺寸通常为2x2mm或2.3x2.1mm，均超出了1.80mm的宽度尺寸，已不再适合采用SOP8的封装形式。
正是基于以上尺寸的限制，目前SOP8的封装形式通常只用于3-9W内置隔离式LED驱动芯片的封装，适用范围较窄。另外，从散热的角度考虑，承载体的面积越小其吸热也越小，因此封装后的VDMOSFET芯片的温升也会增加。为了解决这个问题，也有人提出采用COOLMOS的芯片来替代VDMOSFET芯片来解决这个问题。在同样的开启阻抗条件下，COOLMOS的芯片会比VDMOSFET芯片的面积小。但是，由于目前国内COOLMOS的工艺还不太成熟，生产厂家很少而且价格也高了许多。因此从成本角度考虑，采用COOLMOS的LED驱动芯片目前尚无有力的竞争力。
再者，现有内置隔离式LED驱动芯片的SOP8引线框架采用了两个相邻的引脚1、一个侧连筋4与基岛2相连来做支撑（如图2所示），这样使SOP8的封装形式的有效引脚数减少为6，减少了2个有效引脚，不利于LED驱动芯片的功能性扩展。
综上所述，目前业内亟需一种适用范围广、散热效果好、成本低和扩展性好的SOP8封装引线框架。
发明内容
为了解决上述技术问题，本发明的目的是：提供一种适用范围广、散热效果好、成本低和扩展性好的，大功率LED驱动芯片的SOP8封装引线框架。
本发明解决其技术问题所采用的技术方案是：
一种大功率LED驱动芯片的SOP8封装引线框架，包括引脚、侧连筋、用于承载MOSFET芯片的第一基岛和用于承载IC控制芯片的第二基岛，所述1个引脚与2个侧连筋共同支撑起第一基岛及第二基岛，所述第一基岛的宽度尺寸比SOP8封装基岛的标准宽度尺寸大，所述第二基岛的宽度尺寸比SOP8封装基岛的标准宽度尺寸小。
进一步，所述第一基岛的宽度尺寸为2.355mm，所述第二基岛的宽度尺寸为1.1700mm。
进一步，所述引脚、第一基岛及第二基岛均设置有用于在塑封固化后起固定作用的塑封锁孔。
进一步，在所述第一基岛与MOSFET芯片之间、第二基岛与IC控制芯片之间均设置有银胶层。
进一步，所述MOSFET芯片为VDMOSFET芯片或COOLMOSFET芯片。
本发明的有益效果是：把现有两个相同尺寸的独立基岛改为第一基岛和第二基岛这两个大小不一的独立基岛，第一基岛的宽度尺寸比SOP8封装基岛的标准宽度尺寸大，增加了第一基岛最大承载的MOSFET芯片尺寸，除了适用于3-9W内置隔离式LED驱动芯片的封装外，也适用于12-24W内置隔离式的LED驱动芯片，适用范围广；第一基岛的宽度尺寸的增加也相应扩大了第一基岛的承载面积，有利于MOSFET芯片的散热，有效地降低了封装后MOSFET芯片的温升，散热性能好；对MOSFET芯片无特别要求，可以沿用传统的VDMOSFET芯片工艺，成本较低；通过1个引脚与2个侧连筋共同支撑起第一基岛及第二基岛，只需占用1个引脚，使得SOP8的封装形式的有效引脚数由传统的6个增加为7个，有利于LED驱动芯片的功能性扩展，扩展性较好。进一步，引脚、第一基岛及第二基岛均设置有用于在塑封固化后起固定作用的塑封锁孔，能在塑封固化后将引脚、第一基岛及第二基岛牢牢锁住，避免了在封装的切筋成型工序中，因成型模具异常产生额外的拉拔力造成引脚、第一基岛或第二基岛的表面与塑封料之间产生分层。
附图说明
下面结合附图和实施例对本发明作进一步说明。
图1为SOP8封装形式与DIP8封装形式的关键尺寸简要对比图；
图2为现有的SOP8封装引线框架示意图；
图3为现有SOP8封装的焊线示意图；
图4为本发明一种大功率LED驱动芯片的SOP8封装引线框架示意图；
图5为本发明SOP8封装引线框架的焊线示意图；
图6为采用本发明引线框架的SOP8产品塑封后的局部剖面图。
附图标记：1、引脚；2、第一基岛；3、第二基岛；4、侧连筋；5、塑封锁孔；6、银胶层；7、焊线；8、芯片；9、塑封料；10、IC控制芯片；11、MOSFET芯片。
具体实施方式
参照图4和图5，一种大功率LED驱动芯片的SOP8封装引线框架，包括引脚1、侧连筋4、用于承载MOSFET芯片11的第一基岛2和用于承载IC控制芯片10的第二基岛3，所述1个引脚1与2个侧连筋4共同支撑起第一基岛2及第二基岛3，所述第一基岛2的宽度尺寸比SOP8封装基岛的标准宽度尺寸大，所述第二基岛3的宽度尺寸比SOP8封装基岛的标准宽度尺寸小。
其中，SOP8封装基岛的标准宽度尺寸为2.05mm。
进一步作为优选的实施方式，所述第一基岛2的宽度尺寸为2.355mm，所述第二基岛3的宽度尺寸为1.1700mm。
参照图4和图5，进一步作为优选的实施方式，所述引脚1、第一基岛2及第二基岛3均设置有用于在塑封固化后起固定作用的塑封锁孔5。
参照图6，进一步作为优选的实施方式，在所述第一基岛2与MOSFET芯片之间、第二基岛3与IC控制芯片之间均设置有银胶层6。
进一步作为优选的实施方式，所述MOSFET芯片11为VDMOSFET芯片或COOLMOSFET芯片。
其中,VDMOSFET芯片为1-3N VDMOSFET芯片，COOLMOSFET芯片为3-6N COOLMOSFET。如果内置的MOSFET芯片为1-3N VDMOSFET芯片，则该LED驱动芯片的功率可以达到12W-15W；如果能内置的MOSFET芯片为3-6N COOLMOSFET芯片，则该LED驱动芯片的功率可以达到12-24W。
下面结合说明书附图和具体实施例对本发明作进一步详细说明。
实施例一
参照图4、图5和图6，本发明的第一实施例：
本发明的SOP8引线框架把现有两个相同尺寸的独立基岛改为大小不一的的两个独立基岛：将其中的大基岛（即第一基岛2）的宽度尺寸由原先的2.05mm变为2.335mm,从而使得其最大承载的MOSFET芯片尺寸达到了2.1mm左右。因此用于12-15W的1-3N 650V耐压的 VDMOSFET芯片或12-24W的3-6N耐压650V的COOLMOSFET芯片也就可以放入本发明的引线框架进行封装，解决了传统SOP8的封装不适用于大功率内置隔离式LED驱动芯片的封装这一问题。第一基岛2宽度尺寸的增大，也意味着其所能承载的最大MOSFET芯片面积也由原先的5.68mm2扩大到6.47mm2,其最大承载面积大约扩大了14%，这样也有利于扩大MOSFE芯片的散热，有效地降低了封装后MOSFE芯片的温升。
本发明的引线框架在IC控制芯片10的基岛设计上也作了改进，通过采用一个引脚1和一个侧连筋4来支撑IC芯片的第二基岛3，从而把SOP8的封装形式的有效引脚数由6增加为7，这为以后大功率LED驱动芯片的功能扩展提供了空间。
此外，参照图6（图中的8是MOSFET芯片11和IC控制芯片10的统称），本发明的引线框架与现有的引线框架相比，不仅为每一个独立的引脚上增加了一个塑封锁孔5，而且为第一基岛2和第二基岛3也增加了塑封锁孔5。带有塑封锁孔5的引线框架在塑封工序进行塑封固化后，固化的塑封材料会通过框架上的塑封锁孔5连通，这样就会把引脚1、第一基岛2和第二基岛3牢牢锁住，从而增加封装的可靠性和产品的可靠性。当产品在封装制程的切筋成型工序时，机械成型过程会对产品引脚进行拉伸，本发明引入了塑封锁孔5，增加了引脚1的固定性，避免了因成型模具异常产生额外的拉拔力而造成引脚表面与塑封料之间产生分层的可能性，从而为产品的封装提供更好的可靠性。
与现有技术相比，本发明把现有两个相同尺寸的独立基岛改为第一基岛和第二基岛这两个大小不一的独立基岛，第一基岛的宽度尺寸比SOP8封装基岛的标准宽度尺寸大，增加了第一基岛最大承载的MOSFET芯片尺寸，除了适用于3-9W内置隔离式LED驱动芯片的封装外，也适用于12-24W内置隔离式的LED驱动芯片，适用范围广；第一基岛的宽度尺寸的增加也相应扩大了第一基岛的承载面积，有利于MOSFET芯片的散热，有效地降低了封装后MOSFET芯片的温升，散热性能好；对MOSFET芯片无特别要求，可以沿用传统的VDMOSFET芯片工艺，成本较低；通过1个引脚与2个侧连筋共同支撑起第一基岛及第二基岛，只需占用1个引脚，使得SOP8的封装形式的有效引脚数由传统的6个增加为7个，有利于LED驱动芯片的功能性扩展，扩展性较好。此外，本发明的引脚、第一基岛及第二基岛均设置有用于在塑封固化后起固定作用的塑封锁孔，能在塑封固化后将引脚、第一基岛及第二基岛牢牢锁住，避免了在封装的切筋成型工序中，因成型模具异常产生额外的拉拔力造成引脚、第一基岛或第二基岛的表面与塑封料之间产生分层。
以上是对本发明的较佳实施进行了具体说明，但本发明创造并不限于所述实施例，熟悉本领域的技术人员在不违背本发明精神的前提下还可做作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (5)

1.一种大功率LED驱动芯片的SOP8封装引线框架，其特征在于：包括引脚（1）、侧连筋（4）、用于承载MOSFET芯片（11）的第一基岛（2）和用于承载IC控制芯片（10）的第二基岛（3），所述1个引脚（1）与2个侧连筋（4）共同支撑起第一基岛（2）及第二基岛（3），所述第一基岛（2）的宽度尺寸比SOP8封装基岛的标准宽度尺寸大，所述第二基岛（3）的宽度尺寸比SOP8封装基岛的标准宽度尺寸小。
2.根据权利要求1所述的一种大功率LED驱动芯片的SOP8封装引线框架，其特征在于：所述第一基岛（2）的宽度尺寸为2.355mm，所述第二基岛（3）的宽度尺寸为1.1700mm。
3.根据权利要求1所述的一种大功率LED驱动芯片的SOP8封装引线框架，其特征在于：所述引脚（1）、第一基岛（2）及第二基岛（3）均设置有用于在塑封固化后起固定作用的塑封锁孔（5）。
4.根据权利要求1所述的一种大功率LED驱动芯片的SOP8封装引线框架，其特征在于：在所述第一基岛（2）与MOSFET芯片之间、第二基岛（3）与IC控制芯片之间均设置有银胶层（6）。
5.根据权利要求1所述的一种大功率LED驱动芯片的SOP8封装引线框架，其特征在于：所述MOSFET芯片（11）为VDMOSFET芯片或COOLMOSFET芯片。
CN201510038815.3A 2015-01-26 2015-01-26 一种大功率led驱动芯片的sop8封装引线框架 Pending CN104766920A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510038815.3A CN104766920A (zh) 2015-01-26 2015-01-26 一种大功率led驱动芯片的sop8封装引线框架

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510038815.3A CN104766920A (zh) 2015-01-26 2015-01-26 一种大功率led驱动芯片的sop8封装引线框架

Publications (1)

Publication Number Publication Date
CN104766920A true CN104766920A (zh) 2015-07-08

Family

ID=53648644

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510038815.3A Pending CN104766920A (zh) 2015-01-26 2015-01-26 一种大功率led驱动芯片的sop8封装引线框架

Country Status (1)

Country Link
CN (1) CN104766920A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785345A (zh) * 2017-11-17 2018-03-09 上海晶丰明源半导体股份有限公司 引线框架、引线框架阵列及封装体
CN114023730A (zh) * 2021-10-29 2022-02-08 苏州华太电子技术有限公司 芯片封装结构与电子器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040026744A1 (en) * 2002-05-15 2004-02-12 Mitsuhiro Kameda Semiconductor module
CN201392828Y (zh) * 2009-04-03 2010-01-27 登丰微电子股份有限公司 控制芯片封装结构
KR20110013401A (ko) * 2008-05-16 2011-02-09 가부시키가이샤 메이오 카세이 Ｌｅｄ 패키지, 리드 프레임 및 그 제조법
CN204011394U (zh) * 2014-06-04 2014-12-10 深圳深爱半导体股份有限公司 双岛sop封装结构
CN204424316U (zh) * 2015-01-26 2015-06-24 广州华微电子有限公司 一种大功率led驱动芯片的sop8封装引线框架

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040026744A1 (en) * 2002-05-15 2004-02-12 Mitsuhiro Kameda Semiconductor module
KR20110013401A (ko) * 2008-05-16 2011-02-09 가부시키가이샤 메이오 카세이 Ｌｅｄ 패키지, 리드 프레임 및 그 제조법
CN201392828Y (zh) * 2009-04-03 2010-01-27 登丰微电子股份有限公司 控制芯片封装结构
CN204011394U (zh) * 2014-06-04 2014-12-10 深圳深爱半导体股份有限公司 双岛sop封装结构
CN204424316U (zh) * 2015-01-26 2015-06-24 广州华微电子有限公司 一种大功率led驱动芯片的sop8封装引线框架

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785345A (zh) * 2017-11-17 2018-03-09 上海晶丰明源半导体股份有限公司 引线框架、引线框架阵列及封装体
CN114023730A (zh) * 2021-10-29 2022-02-08 苏州华太电子技术有限公司 芯片封装结构与电子器件
CN114023730B (zh) * 2021-10-29 2023-11-28 苏州华太电子技术股份有限公司 芯片封装结构与电子器件

Similar Documents

Publication Publication Date Title
WO2011071603A3 (en) Module package with embedded substrate and leadframe
CN105489571A (zh) 一种带散热片的半导体封装及其封装方法
CN206807850U (zh) 基于qfn封装的pcb散热结构
CN104766920A (zh) 一种大功率led驱动芯片的sop8封装引线框架
KR101255930B1 (ko) 전력 모듈 패키지 및 그 제조방법
CN110323199A (zh) 一种多基岛引线框架及电源转换模块的qfn封装结构
CN204424316U (zh) 一种大功率led驱动芯片的sop8封装引线框架
CN210778596U (zh) 一种led驱动ic封装结构
CN104810462B (zh) 一种中大功率led驱动芯片的esop8引线框架
CN208596671U (zh) 大功率封装体
CN203733783U (zh) 一种引线框架
CN103441085B (zh) 一种芯片倒装bga封装方法
CN201936866U (zh) 一种功率半导体封装结构
CN208014690U (zh) 一种改进的便于加工的220fw-2l引线框架
CN105932003A (zh) 一种便封装的集成电路
CN202839586U (zh) 一种采用弹性装置的无外引脚扁平半导体封装结构
CN202259261U (zh) 一种含有热沉的引线框架
JP2012074599A (ja) 半導体装置の製造方法
CN102468260B (zh) 兼容高低电压的引线框、引线框阵列及其封装结构
CN204596842U (zh) 一种中大功率led驱动芯片的esop8引线框架
CN206432261U (zh) 一种全包封形式的塑封引线框架
CN209183538U (zh) 高集成功率模块和电器
CN112420649A (zh) 芯片封装结构及电子产品
CN103441080A (zh) 一种芯片正装bga封装方法
CN203445111U (zh) 异型铜带to-252封装引线框架

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20150708

RJ01 Rejection of invention patent application after publication