CN104766880A - p型铋锶钴氧化物半导体沟道薄膜晶体管及其制备方法 - Google Patents

p型铋锶钴氧化物半导体沟道薄膜晶体管及其制备方法 Download PDF

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CN104766880A
CN104766880A CN201510160660.0A CN201510160660A CN104766880A CN 104766880 A CN104766880 A CN 104766880A CN 201510160660 A CN201510160660 A CN 201510160660A CN 104766880 A CN104766880 A CN 104766880A
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cobalt oxide
bismuth strontium
type bismuth
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邓赞红
方晓东
邵景珍
陶汝华
董伟伟
王时茂
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Hefei Institutes of Physical Science of CAS
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    • H01ELECTRIC ELEMENTS
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract

本发明公开了一种p型铋锶钴氧化物半导体沟道薄膜晶体管及其制备方法,在基底上形成栅电极;形成栅极绝缘体;形成沟道层;以及形成源电极和漏电极。基底上形成p型铋锶钴氧化物半导体沟道,在沟道上形成源电极和漏电极;形成栅极绝缘体;以及形成栅电极。其中,沟道层通过溅射来形成,p型铋锶钴氧化物半导体包括铋、锶、钴和氧四种元素,溅射包括脉冲激光溅射、射频磁控溅射、直流磁控溅射、离子束溅射中的至少一种。

Description

p型铋锶钴氧化物半导体沟道薄膜晶体管及其制备方法
技术领域
本发明涉及晶体管领域,具体是一种p型铋锶钴氧化物半导体沟道薄膜晶体管及其制备方法。
背景技术
薄膜晶体管(TFT)一般由基底、栅极绝缘体、沟道层、栅电极、源电极以及漏电极构成,包括底栅结构的TFT(如图1所示)和顶栅结构的TFT(如图2所示),在液晶显示器中被用作开关元件来驱动像素,其中硅基(非晶硅或多晶硅为沟道)TFT占主导地位,但非晶硅TFT和多晶硅TFT都具有不可克服的缺点,诸如光致性能退化,较低的场效应迁移率,开口率有限及功耗较高等。因而,显示技术的发展客观上要求替代硅材料并开发新型TFT。
宽禁带氧化物在可见光波段透明且具有高的电子迁移率,因此宽禁带氧化物TFT可大大提高有源显示矩阵的开口率,从而提高亮度,降低功耗,对透明电子学具有里程碑的意义。然而,多数氧化物半导体是n型导电的,所以,透明薄膜晶体管(TTFT)的应用被限制在n沟道类型。由于p型氧化物沟道层具有空穴注入的特点,更适合驱动OLED高开口率像素单元,因此发展p型氧化物TFT与n型同等重要;此外,n型氧化物TFT只有与p型氧化物结合才能组成全氧化物双极型薄膜场效应晶体管以及互补型反相器逻辑电路,这是实现电路全透明化的基础。由于目前p型透明氧化物半导体材料的发展远远落后于n型,因此研究开发具有与n型器件质量相匹配的p型透明氧化物材料成为透明氧化物半导体TFT发展的当务之急。近年来,基于氧化镍、氧化亚铜、氧化铜、氧化锡和氧化亚锡等p型材料的p沟道TFT相继见诸报端。然而这些p沟道TFT的场效应迁移率仍然很低,通常小于1 cm2V-1s-1,虽然制备p型氧化物外延膜作为沟道层的TFT可以获得高达6cm2V-1s-1的场效应迁移率,但制备工艺复杂,成本高。
发明内容    本发明的目的是提供一种p型铋锶钴氧化物半导体沟道薄膜晶体管及其制备方法,以克服p沟道TFT的场效应迁移率低的缺点。
为了达到上述目的,本发明所采用的技术方案为:
p型铋锶钴氧化物半导体沟道薄膜晶体管,为顶栅结构或底栅结构,包括基底、沟道层、栅极绝缘体、栅极、源极、漏极,其特征在于:沟道层为p型铋锶钴氧化物薄膜。
所述的p型铋锶钴氧化物半导体沟道薄膜晶体管,其特征在于:所述沟道层中,p型铋锶钴氧化物为由铋、锶、钴、氧四种元素组成的任意化学计量比的p型氧化物,p型铋锶钴氧化物薄膜形式为非晶薄膜、多晶薄膜以及外延单晶薄膜中的至少一种。
所述的p型铋锶钴氧化物半导体沟道薄膜晶体管,其特征在于:所述基底为商业化的单晶硅、蓝宝石、石英、玻璃、聚碳酸酯、聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二酯中的一种。
所述的p型铋锶钴氧化物半导体沟道薄膜晶体管,其特征在于:所述栅极绝缘体优选氧化铝或者氧化硅,厚度为100纳米到500纳米。
所述的p型铋锶钴氧化物半导体沟道薄膜晶体管,其特征在于:所述源电极、漏电极和栅电极材料为金属金、铂、镍、钴、铟和铝中的至少一种。
一种p型铋锶钴氧化物半导体沟道薄膜晶体管制备方法,所述晶体管为顶栅结构时,首先在基底上形成由p型铋锶钴氧化物薄膜构成的沟道层,然后在沟道层上形成栅极绝缘体,最后在沟道层上位于栅极绝缘体旁形成源极和漏极、在栅极绝缘体上形成栅极;所述晶体管为底栅结构时,首先在基底上形成栅极,然后在栅电极上形成栅极绝缘体,其次在栅极绝缘体上形成由p型铋锶钴氧化物薄膜构成的沟道层,最后在沟道层上形成源极和漏极,其特征在于:构成沟道层的p型铋锶钴氧化物薄膜通过溅射的方法制备在基底或栅极绝缘体上。
所述的一种p型铋锶钴氧化物半导体沟道薄膜晶体管制备方法,其特征在于:溅射的方法包括脉冲激光溅射、射频磁控溅射、直流磁控溅射、离子束溅射中的至少一种,溅射的基底温度或栅极绝缘体温度从室温到900℃,沟道层的厚度为10纳米到60纳米。
本发明中,p型铋锶钴氧化物多晶薄膜的载流子迁移率高达43 cm2V-1s-1,可以克服p沟道TFT的场效应迁移率低的缺点。此外,p型铋锶钴氧化物薄膜沟道可以采用磁控溅射的方法在室温普通玻璃基底上制备,具有成本低,便于大规模制备的优点。
本发明与现有技术相比的优点在于:
本发明以p型铋锶钴氧化物薄膜作为沟道层,于原有p型氧化物沟道层材料相比,具有更高的场效应迁移率。
本发明对基体的选择无特别要求,沟道层与基体之间无需外延关系,因而采用本发明制备的晶体管可以采用顶栅结构和底栅结构,后者相对于前者来说,其电极的制备工艺更为简单,甚至无需采用光刻技术,降低了器件制备的难度并节约了成本。
本发明提供的p型铋锶钴氧化物非晶薄膜可以在室温下通过溅射的方法制备,工艺简单、成本低,使其制作在玻璃、有机柔性基底上成为可能,增加了其工业应用的机会。
附图说明
图1是底栅结构p型铋锶钴氧化物沟道薄膜晶体管的示意图;
图2是顶栅结构p型铋锶钴氧化物沟道薄膜晶体管的示意图;
图3 是本发明实施例所制备的p型铋锶钴氧化物沟道非晶薄膜晶体管的结构示意图;
图4 是磁控溅射法制备的p型铋锶钴氧化物非晶薄膜表面与断面的扫面电子显微镜图片,其中:图4a为表面图片,图4b为断面图片。
具体实施方式
p型铋锶钴氧化物半导体沟道薄膜晶体管,为顶栅结构或底栅结构,包括基底、沟道层、栅极绝缘体、栅极、源极、漏极,沟道层为p型铋锶钴氧化物薄膜。
沟道层中,p型铋锶钴氧化物为由铋、锶、钴、氧四种元素组成的任意化学计量比的p型氧化物,p型铋锶钴氧化物薄膜形式为非晶薄膜、多晶薄膜以及外延单晶薄膜中的至少一种。
基底为商业化的单晶硅、蓝宝石、石英、玻璃、聚碳酸酯、聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二酯中的一种。
栅极绝缘体优选氧化铝或者氧化硅,厚度为100纳米到500纳米。
源电极、漏电极和栅电极材料为金属金、铂、镍、钴、铟和铝中的至少一种。
一种p型铋锶钴氧化物半导体沟道薄膜晶体管制备方法,晶体管为顶栅结构时,首先在基底上形成由p型铋锶钴氧化物薄膜构成的沟道层,然后在沟道层上形成栅极绝缘体,最后在沟道层上位于栅极绝缘体旁形成源极和漏极、在栅极绝缘体上形成栅极;晶体管为底栅结构时,首先在基底上形成栅极,然后在栅电极上形成栅极绝缘体,其次在栅极绝缘体上形成由p型铋锶钴氧化物薄膜构成的沟道层,最后在沟道层上形成源极和漏极,构成沟道层的p型铋锶钴氧化物薄膜通过溅射的方法制备在基底或栅极绝缘体上。
溅射的方法包括脉冲激光溅射、射频磁控溅射、直流磁控溅射、离子束溅射中的至少一种,溅射的基底温度或栅极绝缘体温度从室温到900℃,沟道层的厚度为10纳米到60纳米。图4给出了采用磁控溅射方法在普通玻璃衬底上400℃沉积的p型铋锶钴氧化物薄膜的表面和断面扫描电镜照片。
具体实施例:
本实施例描述了在二氧化硅/p型单晶硅基体上制备底栅结构的p型铋锶钴氧化物沟道晶体管(如图3所示)的过程。
选择商业化的热氧化硅片二氧化硅/重掺杂p型单晶硅为基体,其中二氧化硅层作为栅极绝缘体,厚度为280纳米,同时重掺杂p型单晶硅又可以作为栅电极;
采用射频磁控溅射法,以铋锶钴氧化物多晶材料为靶材,室温条件下在栅极绝缘体上沉积40纳米的铋锶钴氧化物非晶薄膜,其后在真空下进行热退火处理,退火温度为400℃,退火时间为30分钟;
采用磁控溅射法和铝模板制备铝源电极和铝漏电极,源漏之间的沟道长和宽分别为2500微米和60微米,制得p型铋锶钴氧化物沟道薄膜晶体管;
本发明未详细阐述部分属于本领域技术人员的公知技术。
以上所述,仅为本发明中的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉该技术的人在本发明所揭露的技术范围内,可理解想到的变换或替换,都应涵盖在本发明的包含范围之内,因此,本发明的保护范围应该以权利要求书的保护范围为准。

Claims (7)

1.p型铋锶钴氧化物半导体沟道薄膜晶体管,为顶栅结构或底栅结构,包括基底、沟道层、栅极绝缘体、栅极、源极、漏极,其特征在于:沟道层为p型铋锶钴氧化物薄膜。
2.根据权利要求1所述的p型铋锶钴氧化物半导体沟道薄膜晶体管,其特征在于:所述沟道层中,p型铋锶钴氧化物为由铋、锶、钴、氧四种元素组成的任意化学计量比的p型氧化物,p型铋锶钴氧化物薄膜形式为非晶薄膜、多晶薄膜以及外延单晶薄膜中的至少一种。
3.根据权利要求1所述的p型铋锶钴氧化物半导体沟道薄膜晶体管,其特征在于:所述基底为商业化的单晶硅、蓝宝石、石英、玻璃、聚碳酸酯、聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二酯中的一种。
4.根据权利要求1所述的p型铋锶钴氧化物半导体沟道薄膜晶体管,其特征在于:所述栅极绝缘体优选氧化铝或者氧化硅,厚度为100纳米到500纳米。
5.根据权利要求1所述的p型铋锶钴氧化物半导体沟道薄膜晶体管,其特征在于:所述源电极、漏电极和栅电极材料为金属金、铂、镍、钴、铟和铝中的至少一种。
6.一种p型铋锶钴氧化物半导体沟道薄膜晶体管制备方法,所述晶体管为顶栅结构时,首先在基底上形成由p型铋锶钴氧化物薄膜构成的沟道层,然后在沟道层上形成栅极绝缘体,最后在沟道层上位于栅极绝缘体旁形成源极和漏极、在栅极绝缘体上形成栅极;所述晶体管为底栅结构时,首先在基底上形成栅极,然后在栅电极上形成栅极绝缘体,其次在栅极绝缘体上形成由p型铋锶钴氧化物薄膜构成的沟道层,最后在沟道层上形成源极和漏极,其特征在于:构成沟道层的p型铋锶钴氧化物薄膜通过溅射的方法制备在基底或栅极绝缘体上。
7.根据权利要求6所述的一种p型铋锶钴氧化物半导体沟道薄膜晶体管制备方法,其特征在于:溅射的方法包括脉冲激光溅射、射频磁控溅射、直流磁控溅射、离子束溅射中的至少一种,溅射的基底温度或栅极绝缘体温度从室温到900℃,沟道层的厚度为10纳米到60纳米。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105742188A (zh) * 2015-11-25 2016-07-06 青岛大学 一种多元醇还原技术制备p型氧化物薄膜材料的方法
CN109417036A (zh) * 2016-06-30 2019-03-01 流慧株式会社 p-型氧化物半导体及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101419947A (zh) * 2008-12-09 2009-04-29 河北大学 一种过渡金属氧化物p-n异质结及其制备方法
CN101826570A (zh) * 2010-03-25 2010-09-08 河北大学 一种p-n异质结光探测器
CN101826594A (zh) * 2010-03-25 2010-09-08 河北大学 一种错配层钴氧化合物热电薄膜光探测器
CN102723367A (zh) * 2012-06-29 2012-10-10 昆山工研院新型平板显示技术中心有限公司 一种氧化物半导体薄膜晶体管
US20130269740A1 (en) * 2010-09-29 2013-10-17 Siemens Aktiengesellschaft Thermoelectric generator
WO2014100723A1 (en) * 2012-12-21 2014-06-26 The Regents Of The University Of California Vertically stacked heterostructures including graphene

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101419947A (zh) * 2008-12-09 2009-04-29 河北大学 一种过渡金属氧化物p-n异质结及其制备方法
CN101826570A (zh) * 2010-03-25 2010-09-08 河北大学 一种p-n异质结光探测器
CN101826594A (zh) * 2010-03-25 2010-09-08 河北大学 一种错配层钴氧化合物热电薄膜光探测器
US20130269740A1 (en) * 2010-09-29 2013-10-17 Siemens Aktiengesellschaft Thermoelectric generator
CN102723367A (zh) * 2012-06-29 2012-10-10 昆山工研院新型平板显示技术中心有限公司 一种氧化物半导体薄膜晶体管
WO2014100723A1 (en) * 2012-12-21 2014-06-26 The Regents Of The University Of California Vertically stacked heterostructures including graphene

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105742188A (zh) * 2015-11-25 2016-07-06 青岛大学 一种多元醇还原技术制备p型氧化物薄膜材料的方法
CN109417036A (zh) * 2016-06-30 2019-03-01 流慧株式会社 p-型氧化物半导体及其制造方法
CN109417036B (zh) * 2016-06-30 2024-03-15 株式会社Flosfia p-型氧化物半导体及其制造方法

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