CN104716057A - 具有嵌入部件的集成电路封装系统及其制造方法 - Google Patents

具有嵌入部件的集成电路封装系统及其制造方法 Download PDF

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CN104716057A
CN104716057A CN201410784761.0A CN201410784761A CN104716057A CN 104716057 A CN104716057 A CN 104716057A CN 201410784761 A CN201410784761 A CN 201410784761A CN 104716057 A CN104716057 A CN 104716057A
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buried patterns
integrated circuit
parts
insert material
patterns
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CN104716057B (zh
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田东柱
朴敬熙
卢泳达
郑鉁熙
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Stats Chippac Pte Ltd
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Abstract

一种集成电路封装系统及其集成电路封装系统的制造方法，所述集成电路封装系统包括：在部件上的嵌入材料；在所述嵌入材料上的掩模层；在所述掩模层中的掩埋图案，所述掩埋图案的外表面与所述掩模层的外表面共面，所述掩埋图案电气连接至所述部件；在所述掩埋图案的一部分上的图案化电介质；以及，在所述掩埋图案上的集成电路管芯。

Description

具有嵌入部件的集成电路封装系统及其制造方法
相关申请的交叉引用
本申请要求2013年12月16日提交的美国临时专利申请案第61/916,405号的权益，并且全部内容通过引用结合在本申请中。
技术领域
本发明一般涉及一种集成电路封装系统，更加具体地，涉及一种具有嵌入式电子部件的系统。
背景技术
计算机产业的持续目标是部件越来越小型化，使集成电路(IC,IntegratedCircuits)的封装密度更大，性能更高，成本更低。半导体封装结构继续朝着小型化发展，在减小由半导体封装结构制成的产品尺寸的同时，增加封装在半导体封装结构中的部件的密度。这是响应于对信息和通信产品不断增长的需求：不断减小的尺寸、厚度和成本以及不断提高的性能。
这些日益增长的小型化需求尤其引人注目，例如，对诸如蜂窝电话、免提蜂窝电话耳机、个人数据助理(PDA,Persnal Data Asistant)、便携式摄像机、笔记本电脑等便携式信息和通信装置的小型化需求。所有这些装置不断地被做得更小更薄以提高它们的可携带性。因此，并入这些装置中的大规模IC(LSI,LargeScale IC)封装要求更小更薄。包覆并保护LSI的封装结构也要求更小更薄。
消费性电子产品的要求需要更多的集成电路在集成电路封装中，然而在系统中却为增加的集成电路内容提供了更小的物理空间。另一需求是继续减少成本。一些技术主要专注于将更多功能集成到每个集成电路中。另一些技术则专注于将这些集成电路堆叠到单个封装中。虽然这些方法在集成电路内提供了更多功能，但是，并未完全满足集成和成本减少的需要。
由此，仍然需要一种实现集成、节省空间和低制造成本的支持系统的制造方法。鉴于商业竞争压力不断增加，以及消费者期望的增长和市场中有意义的产品差异化机会的减少，寻找解决这些问题的方法至关重要。此外，降低成本、提高效率和性能、并且满足竞争压力的需要使寻找这些问题的解决方法迫在眉睫。
人们早就已经在寻找解决这些问题的方案，但是，现有发展尚未教导或提出任何解决方案，由此，本领域的技术人员一直没能掌握解决这些问题的方案。
发明内容
本发明提供一种集成电路封装系统的制造方法，包括：在无源装置上形成嵌入材料；将干膜层沉积在所述嵌入材料上；将所述干膜层图案化；将掩埋图案沉积在所述干膜层中，所述掩埋图案的外表面与所述干膜层的外表面共面，所述掩埋图案电气连接至所述无源装置；在所述掩埋图案的一部分上形成图案化电介质；以及，将集成电路管芯安装在所述掩埋图案上。
本发明提供一种集成电路封装系统，所述集成电路封装系统包括：在无源装置上的嵌入材料；在所述嵌入材料上的干膜层；在所述干膜层中的掩埋图案，所述掩埋图案的外表面与所述干膜层的外表面共面，所述掩埋图案电气连接至所述无源装置；在所述掩埋图案的一部分上的图案化电介质；以及，在所述掩埋图案上的集成电路管芯。
本发明的特定实施例具有除了这些上述提到的步骤或元件之外的或者替换这些步骤或元件的其他步骤或元件。对本领域中的技术人员而言，当参考附图时，通过阅读下面的详细说明，这些步骤或元件将变得显而易见。
附图说明
图1是根据本发明的第一实施例的集成电路封装系统的俯视图。
图2是沿截面线2-2所做的图1的集成电路封装系统的一部分的截面视图。
图3是根据本发明的第二实施例的集成电路封装系统的截面视图。
图4是在制造的开始阶段中的图2的集成电路封装系统。
图5是在制造的第一电镀阶段中的图4的结构。
图6是在制造的粘合剂沉积阶段中的图5的结构。
图7是在制造的无源装置附接阶段中的图6的结构。
图8是在制造的层压阶段中的图7的结构。
图9是在制造的第一图案化阶段中的图8的结构。
图10是在制造的分离阶段中的图9的结构。
图11是在制造的过孔形成阶段中的图10的结构。
图12是在制造的过孔开口阶段中的图11的结构。
图13是在制造的沉积阶段中的图12的结构。
图14是在制造的去除阶段中的图13的结构。
图15是在用于制造图3的集成电路封装系统的制造的交错分层阶段中的图9的结构。
图16是在制造的过孔形成阶段中的图15的结构。
图17是在制造的拆卸阶段中的图16的结构。
图18是在制造的进一步过孔形成阶段中的图17的结构。
图19是在制造的过孔开口阶段中的图18的结构。
图20是在制造的沉积阶段中的图19的结构。
图21是在制造的去除阶段中的图20的结构。
图22是根据本发明的进一步实施例中的集成电路封装系统的制造方法的流程图。
具体实施方式
对下面的实施例进行足够详细地描述，从而使本领域中的技术人员能够制作和使用本发明。需要理解的是，其他实施例基于本公开将会是显而易见的，并且，在不背离本发明的范围的情况下，可以对系统、工艺或机械做出改变。
在下面的说明中，图示了多种具体细节以提供对本发明实施例的全面理解。然而，显而易见的是，在不具有这些具体细节的情况下，也可以实践本发明。为了避免导致本发明晦涩，一些已知的电路、系统配置和工艺步骤不再详细公开。
示出的系统的实施例的附图是半示意性质的并且并不一定是按比例绘制，并且，尤其，一些尺寸是出于表示的清晰起见并且在附图中放大示出。相似地，虽然附图中的视图出于方便说明之目的一般示出了相似的方向，但是附图中的这种描绘在大多数的情况下是任意的。一般地，本发明可以以任何方向操作。
在多个实施例被公开并且描述为具有一些共同特征的情况下，为了清楚且方便地图示、说明和理解实施例起见，相似的和相同的特征通常用相似的附图标记描述。为了方便进行描述，已经将实施例编号为第一实施例、第二实施例等，但是，并不意在具有任何其他意义或提供对本发明的限制。
出于阐释之目的，在本文中使用的术语“水平”定义为平行于最低导电图案的平面或表面的平面，而无论方向如何。术语“垂直”指垂直于刚才定义的“水平”的方向。术语，诸如“上方”、“下方”、“底部”、“顶部”、“侧”(如在“侧壁”中)、“更高”、“更低”、“上”、“之上”和“之下”均是相对于水平面而定义的，如附图所示。术语“在…上”指元件之间存在直接接触。术语“直接在…上”指在一个元件和另一元件之间存在直接接触，无中间元件。
术语“有源侧”指管芯、模块、封装、或电子结构的一侧，该侧上具有制造出的有源电路或具有用于连接至在管芯、模块、封装或电子结构内的有源电路的元件。
在本文中使用的术语“处理”包括：按形成所描述结构的需要，对材料或光刻胶(photoresist)进行沉积、图案化、曝光、显影、蚀刻、清洗和/或去除材料或光刻胶。
现在参考图1，图中示出了根据本发明第一实施例的集成电路封装系统100的俯视图。俯视图示出了嵌入式部件基板102的一部分，集成电路管芯104安装在嵌入式部件基板102的顶部上。可以理解的是，可以根据需要在嵌入式部件基板102上安装更多管芯，但是，出于图示之目的，仅示出一个管芯。为清楚起见，还省略了诸如暴露出来的焊盘(pad)或迹线等其他特征。嵌入式部件基板102的顶表面106在集成电路管芯104周围可以看见。
现在参考图2，图中示出了沿截面线2-2所做的图1的集成电路封装系统100的一部分的截面视图。示出了集成电路管芯104和嵌入式部件基板102。嵌入式部件基板102包括作为嵌入部件的部件208，该部件208与嵌入材料210直接接触并且被嵌入材料210围住，该嵌入材料210可以是例如预浸渍材料(PPG)。例如，部件208可以是有源或无源装置，诸如集成电路管芯、电容器或电阻器。
在嵌入于嵌入材料210中的部件208之上的是掩埋图案(buried pattern)212，该掩埋图案212是埋入掩模层(mask layer)214中的导电图案，从而使掩埋图案212的外表面与掩模层214的外表面共面。掩模层214可以是例如光刻胶、干膜、或光可成像的电介质。集成电路管芯104通过掩埋图案212连接至部件208，该掩埋图案212通过嵌入式部件过孔216连接至部件208，该嵌入式部件过孔216向下延伸以穿过装置粘合剂218直接接触部件208。
在部件208下方的是位于嵌入材料210上和外部的导电图案220。嵌入式部件过孔216将部件208连接至导电图案220。已经发现，掩埋图案212可以使焊盘、线、迹线和过孔形成与建立在电介质表面上的导电图案相同的图案，因此，利用掩埋图案212，不存在路由能力的损失。
诸如阻焊等图案化电介质222覆盖住掩埋图案212和导电图案220的一部分，以保护非接触区域免受腐蚀、意外短路、或者其他意想不到的外力。掩埋图案212的一些掩埋接触焊盘224和导电图案220的外层接触焊盘226暴露在图案化电介质222外。迹线228连接各个导电图案的各种接触焊盘，虽然仅仅示出了一部分迹线228。
在嵌入式部件基板102的某些部分中，掩埋接触焊盘224通过穿过嵌入材料210的垂直过孔230直接连接至外层接触焊盘226。在掩埋接触焊盘224与外层接触焊盘226之间的该直接连接例如使电信号的路由灵活性更大。在本示例中，垂直过孔230和嵌入式部件过孔216为锥形，一端薄于另一端，但是应理解，这仅仅是出于图示之目的。例如，相比于激光钻孔，如果通过机械钻孔制成，那么，垂直过孔230的厚度可以始终相同。
已经发现，掩模层214中的掩埋图案212实现了迹线228与掩埋接触焊盘224之间以及多个其他迹线之间的细微节距控制。例如，通过使用掩模层214帮助创建掩埋图案212，导电图案布线或迹线的线宽(line width，LW)或布线宽度(wire width，WW)和线之间的线间隔(也称为L/S)可以分别为15微米(um)和15um(15/15)。术语“细微节距”指15/15um或者更小的LW/LS。
还发现，相较于安装两个部件表面，将集成电路管芯104直接附接在部件208上方改善了电气性能。由于例如通过掩埋图案212和嵌入式部件过孔216，在集成电路管芯104和部件208之间的电气路径更短且更加直接，所以，极大地减少了电压噪声并且降低了阻抗，这还可以降低功率要求。
现在参考图3，图中示出了根据本发明第二实施例的集成电路封装系统300的截面视图。示出了集成电路管芯304和嵌入式部件基板302。嵌入式部件基板302包括作为嵌入部件的部件308，该部件308与嵌入材料310直接接触并且被嵌入材料310围住，该嵌入材料310可以是例如预浸渍材料(PPG)。例如，部件208可以是有源或无源装置，诸如集成电路管芯、电容器或电阻器。
在嵌入于嵌入材料310中的部件308之上的是掩埋图案312，该掩埋图案312是埋入掩模层314中的导电图案，从而使掩埋图案312的外表面与掩模层314的外表面共面。掩模层214可以是例如光刻胶、干膜、或光可成像的电介质。
集成电路管芯304通过掩埋图案312连接至部件308，该掩埋图案312通过嵌入式部件过孔316连接至部件308，该嵌入式部件过孔316向下延伸以穿过装置粘合剂318直接接触部件308。
在部件308下方的是分层导电图案331，该分层导电图案331具有在嵌入材料310上和外部的外层和由嵌入材料覆盖的内层。嵌入式部件过孔316将部件308连接至分层导电图案331。分层导电图案331示出为通过内部过孔连接的两层式结构，但是可以理解的是，如果需要，也可以使用任何层数。例如，分层导电图案331可以是三层或更多层以增加路由灵活性。
诸如阻焊等图案化电介质322覆盖住掩埋图案312和分层导电图案331的外层的一部分，以保护非接触区域免受腐蚀、意外短路、或者其他意想不到的外力。掩埋图案312的掩埋接触焊盘324和分层导电图案331的外层接触焊盘326暴露在图案化电介质322外。迹线328连接各个导电图案的各种接触焊盘，虽然仅仅示出了一部分迹线328。
在嵌入式部件基板302的某些部分中，掩埋接触焊盘324通过穿过嵌入材料310的一部分的垂直过孔330直接连接至内层接触焊盘332。在掩埋接触焊盘324与内层接触焊盘332之间的该直接连接例如使电信号的路由灵活性更大。在本示例中，垂直过孔330为锥形，垂直过孔330的一端薄于另一端，但是应理解，这仅仅是出于图示之目的。例如，相比于激光钻孔，如果通过机械钻孔制成，那么，垂直过孔330的厚度可以始终相同。
内部过孔将一些内层接触焊盘332连接至外层接触焊盘326，并且可以理解的是，如路由要求需要，内部过孔的位置可以调节。分层导电图案331的外层的迹线328可以由图案化电介质322覆盖。
现在参考图4，图中示出的是在制造开始阶段中的图2的集成电路封装系统100。可以看见双面承载体434，其中，诸如铜等导电层436在双面承载体434的两面可以看见。双面承载体434例如可以是具有电介质核芯的覆铜板(copperclad laminate，CCL)。
现在参考图5，图中示出了在制造的第一电镀阶段中的图4的结构。将掩模层214施加于导电层436并且将其图案化后进行沉积，以形成成图2的掩埋图案212。例如，用于掩埋图案212的材料可以与导电层436的材料相同。需要理解的是，在使用双面承载体434的所有步骤中，对工艺的说明针对双面承载体434的两面。
已经发现，本发明的形成集成电路封装系统100的各个实施例通过用图2的嵌入材料210所用的PPG层压板替代覆铜板(CCL)使材料成本降低。还发现，由于具有对称结构，使用双面承载体434和在两面同时进行处理抑制了高温带翘曲。
还发现，使用掩模层214来形成掩埋图案212可以提高可靠性并且减少空洞陷阱(void traps)的可能性。当将粘合绝缘体涂覆或印刷在与掩模层214共面的掩埋图案212上时，减少了形成空洞的风险。通过在导电图案周围使用例如光可成像图案保护材料，可以将粘合绝缘体涂覆或印刷在更平滑的表面上，以降低或者消除空洞陷阱的风险。在基板或封装中的空洞是引起可靠性问题的主要根源之一。
现在参考图6，图中示出了在制造的粘合剂沉积阶段中的图5的结构。将装置粘合剂218沉积在掩模层214和掩埋图案212上，以准备安装图2的部件208。例如，可以通过诸如印刷或涂覆等工艺进行该沉积。
参考图7，图中示出了在制造的无源装置附着阶段中的图6的结构。部件208通过装置粘合剂218附着至掩埋图案212。装置粘合剂218在水平上大于部件208。
参考图8，图中示出了在制造的层压阶段中的图7的结构。在该阶段中，沉积嵌入材料210和基础导电材料838，基础导电材料838的一部分将变成图2的导电图案220。可按照多种方式进行沉积或层压工艺，并且，示出嵌入材料210的多个部分之间相分开仅是出于清楚起见。
参考图9，图中示出了在制造的第一图案化阶段中的图8的结构。例如，可通过注入掩模和电镀等工艺将导电图案220图案化在位于嵌入材料210上的基础导电材料838的顶部。在形成导电图案220之前，可在沉积导电材料之后通过诸如钻孔(激光或机械)或蚀刻等工艺形成嵌入式部件过孔216和垂直过孔230。可通过基础导电材料838和嵌入材料210形成嵌入式部件过孔216和垂直过孔230。沉积可通过例如电镀的方法实现。然后，可将导电图案220图案化以接触垂直过孔230、嵌入式部件过孔216和基础导电材料838。
参考图10，图中示出了在制造的拆卸阶段中的图9的结构。在该阶段中，可从图4的双面承载体434的核心(core)拆卸导电层436。可以理解的是，可按照相同的方式对在双面承载体434的每一面上的结构进行处理，这在此图之后描述。还可以理解的是，该图以及该图之后的图示出了相较于图2的集成电路封装系统100呈上下翻转(flipped upside-down)的结构。可以理解的是，所示结构的方向仅出于示例之目的，并且，工艺不受限于所示方向。
参考图11，图中示出了在制造的过孔形成阶段中的图10的结构。在该阶段中，利用诸如蚀刻或钻孔等工艺穿过导电层436和掩埋图案212形成嵌入式部件过孔216。在本示例中，使用图案化掩模1140穿过导电材料进行保形蚀刻，但是，停止于装置粘合剂218。
参考图12，图中示出了在制造的过孔开口阶段中的图11的结构。在该阶段中，通过在装置粘合剂218中开孔来完成嵌入式部件过孔216，以暴露出部件208的触头。在本示例中，通过激光钻孔对装置粘合剂218进行开口。
参考图13，图中示出了在制造的沉积阶段中的图12的结构。用导电材料(诸如，铜)填充从装置粘合剂218中穿过的嵌入式部件过孔216，该导电材料直接接触部件208。此外，在填充嵌入式部件过孔216之后，去除图11的图案化掩模1140。
参考图14，图中示出了在制造的去除阶段中的图13的结构。去除图4的导电层436和图8的基础导电材料838，从而充分形成掩埋图案212和分层导电图案220。例如，可以通过诸如蚀刻等方法进行去除。
在去除阶段之后，将图2的图案化电介质222沉积在掩埋图案212、导电图案220和嵌入材料210上。这就完成了图2中的嵌入式部件基板102的形成。将图2的集成电路管芯104安装在嵌入式部件基板102上以完成图2的集成电路封装系统100。
已经发现，通过使用掩模层214来形成掩埋图案212减少了制造缺陷，从而提高了产率和可靠性。已经发现，由于电镀不均匀，先前的块上过孔(via onbump，VOB)结构在导电图案中存在不均匀的凹痕。利用具有与掩模层214共面的表面的掩埋图案212，将VOB结构形成为平坦结构就变得更加容易，从而减少了缺陷的发生率。
参考图15，图中示出了在用于制造图3的集成电路封装系统300的制造的可替代分层阶段中的图9的结构。在该阶段中，进行蚀刻以去除图8的基础导电材料838，并且，在导电图案的顶部上层压另一层嵌入材料310，该导电图案将变成图3的分层导电图案331的内层。然后，可将外基础导电层1542沉积在嵌入材料310上。
参考图16，图中示出了在制造的过孔形成阶段中的图15的结构。可在嵌入材料310中创建内部过孔，该内部过孔穿过外基础导电层1542以与连接至部件308的嵌入式部件过孔316对齐。然后，可在将分层导电图案331的外层图案化在外基础导电层1542的表面上的同时，用导电材料(诸如，铜)填充内部过孔。可以理解的是，填充内部过孔和沉积分层导电图案331的外层可同时或分开进行。
现在参考图17，图中示出了在制造的拆卸阶段中的图16的结构。相较于图3中的集成电路封装系统300的方向，该结构示出为翻转的方向，但是，可以理解的是，该方向仅出于图示之目的而示出，任何方向均是可能的。
参考图18，图中示出了在制造的进一步过孔形成阶段中的图17的结构。在该阶段中，利用诸如蚀刻或钻孔等工艺穿导电层436和掩埋图案312形成嵌入式部件过孔316。在本示例中，使用图案化掩模1840穿过导电材料进行保形蚀刻，但是，停止于装置粘合剂318。
现在参考图19，图中示出了在制造的过孔开口阶段中的图18的结构。在该阶段中，通过在装置粘合剂318中开孔来完成嵌入式部件过孔316，以暴露出部件308的触头。在本示例中，通过激光钻孔对装置粘合剂318进行开口。
现在参考图20，图中示出了在制造的沉积阶段中的图19的结构。用导电材料(诸如，铜)填充从装置粘合剂318中穿过的嵌入式部件过孔316，该导电材料直接接触部件308。可以在填充嵌入式部件过孔316之后，去除图案化掩模1840。
参考图21，图中示出了在制造的去除阶段中的图20的结构。去除图4的导电层436和图8的基础导电材料838，从而充分形成掩埋图案312和分层导电图案331。例如，可以通过诸如蚀刻等方法进行去除。
在去除阶段之后，将图3的图案化电介质322沉积在掩埋图案312、分层导电图案331和嵌入材料310上。这就完成了图3中的嵌入式部件基板302的形成。安装图3的集成电路管芯304完成图3的集成电路封装系统300。
已经发现，上面针对形成集成电路封装系统300所描述的无芯工艺流程使导电图案331的层易于延伸。因为嵌入材料仅建立到所需的厚度，所以可容易地添加额外的厚度，通过添加另一层嵌入材料310然后将顶部上的导电层图案化可以使添加分层导电图案331的附加层相对简单。这仅以少量的成本增加实现了更大的路由选择。
现在参考图22，示出了根据本发明的进一步实施例的制造集成电路封装系统100的方法2200的流程图。方法2200包括：在框2202中，在无源装置上形成嵌入材料；在框2204中，将干膜层沉积在嵌入材料上；在框2206中，将干膜层图案化；在框2208中，将掩埋图案沉积在干膜层中，掩埋图案的外表面与干膜层的外表面共面，掩埋图案电气连接至无源装置；在框2210中，在掩埋图案的一部分上形成图案化电介质；以及，在框2212中，将集成电路管芯安装在掩埋图案上。
由此产生的方法、工艺、设备、装置、产品和/或系统简单直接、性价比高、不复杂、高度通用、准确、灵敏和有效，并且，可以通过采取已知部件来实施以便容易地、高效地且经济地制造、应用和利用。
本发明的另一重要方面是其有益地支持和服务于减少成本、简化系统和提高性能的历史趋势。
本发明的这些和其他有益方面因此使技术状态进步到至少下一个等级。
虽然已经结合具体的最佳模式对本发明进行了描述，但是需要理解的是，鉴于上面的说明书，对本领域中的技术人员而言，各种替代、修改和变型都是显而易见的。因此，本发明旨在包含落入所附权利要求书范围内的所有这类替代、修改和变型。本文中提到的或附图中示出的所有事物均应理解为图示性质，无限制意义。

Claims (10)

1.一种集成电路封装系统的制造方法，包括：
在部件上形成嵌入材料；
将掩模层沉积在所述嵌入材料上；
将所述掩模层图案化；
将掩埋图案沉积在所述掩模层中，所述掩埋图案的外表面与所述掩模层的外表面共面，所述掩埋图案电气连接至所述部件；
在所述掩埋图案的一部分上形成图案化电介质；以及
将集成电路管芯安装在所述掩埋图案上。
2.根据权利要求1所述的方法，其中，所述嵌入材料是预浸渍材料。
3.根据权利要求1所述的方法，其中：
沉积所述掩埋图案包括，沉积具有掩埋接触焊盘的所述掩埋图案；以及
形成所述图案化电介质包括，形成所述图案化电介质，使所述掩埋接触焊盘暴露出来。
4.根据权利要求1所述的方法，其进一步包括：在所述嵌入材料上形成导电图案，所述导电图案电气连接至所述部件的与所述掩埋图案相反的一侧。
5.根据权利要求1所述的方法，其进一步包括：形成将所述掩埋图案电气连接至所述部件的嵌入式部件过孔。
6.一种集成电路封装系统，包括：
在部件上的嵌入材料；
在所述嵌入材料上的掩模层；
在所述掩模层中的掩埋图案，所述掩埋图案的外表面与所述掩模层的外表面共面，所述掩埋图案电气连接至所述部件；
在所述掩埋图案的一部分上的图案化电介质；以及
在所述掩埋图案上的集成电路管芯。
7.根据权利要求6所述的系统，其中，所述嵌入材料是预浸渍材料。
8.根据权利要求6所述的系统，其中，所述掩埋图案具有暴露在所述图案化电介质外的掩埋接触焊盘。
9.根据权利要求6所述的系统，其进一步包括在所述嵌入材料上的导电图案，所述导电图案电气连接至所述部件的与所述掩埋图案相反的一侧。
10.根据权利要求6所述的系统，其进一步包括嵌入式部件过孔，所述嵌入式部件过孔将所述掩埋图案电气连接至所述部件。
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