CN104701156B - 用于在裸片分离过程期间减小背面裸片损坏的方法 - Google Patents
用于在裸片分离过程期间减小背面裸片损坏的方法 Download PDFInfo
- Publication number
- CN104701156B CN104701156B CN201410740485.8A CN201410740485A CN104701156B CN 104701156 B CN104701156 B CN 104701156B CN 201410740485 A CN201410740485 A CN 201410740485A CN 104701156 B CN104701156 B CN 104701156B
- Authority
- CN
- China
- Prior art keywords
- bare die
- semiconductor wafer
- chip
- sawing
- anchor material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000000926 separation method Methods 0.000 title abstract description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 38
- 238000005520 cutting process Methods 0.000 claims abstract description 16
- 238000010276 construction Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 13
- 230000000717 retained effect Effects 0.000 claims description 4
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 238000004873 anchoring Methods 0.000 claims description 2
- 239000000945 filler Substances 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- 239000002390 adhesive tape Substances 0.000 claims 1
- 239000011231 conductive filler Substances 0.000 claims 1
- 238000013467 fragmentation Methods 0.000 abstract description 5
- 238000006062 fragmentation reaction Methods 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000002322 conducting polymer Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
- H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
- H01L2224/2732—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
- H01L2224/27416—Spin coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
- H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/278—Post-treatment of the layer connector
- H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
Abstract
本申请案涉及一种用于在裸片分离过程期间减小背面裸片损坏的方法。在本发明的一个方面中,将描述一种锯割半导体晶片(101)的方法。将半导体晶片(101)定位于晶片锯割设备中,所述晶片锯割设备包含锯割刀片(102)及物理上支撑所述半导体晶片(101)的可移动支撑结构(103)。所述半导体晶片(101)借助包含切片胶带(107)及锚定材料(106)的各种层与所述支撑结构(103)耦合。借助所述锯割刀片(102)切割所述锚定材料(106)及所述晶片(101)。在切割操作期间,所述锚定材料(106)减少裸片的背面碎裂且使裸片不会飞开。本发明的各个方面涉及牵涉到前述锯割方法的若干布置及一晶片锯割设备。
Description
技术领域
本发明涉及集成电路封装。更具体来说,本发明涉及用于锯割及分离半导体晶片上的裸片的方法及布置。
背景技术
存在用以形成集成电路的各种各样的方式。一种常规方法涉及在一片半导体材料上形成各种装置及互连件。这些操作在单个半导体晶片101上形成同一集成电路设计105的通过锯切道(saw street)分离的多个复制品。
参考图1,接着使用锯割机器(未展示)对半导体晶片101进行切片或锯割以分离集成电路。
锯割机器(未展示)由锯刀片102、驱动锯刀片102的电动机(未展示)及在锯刀片下方前后移动以沿着晶片的锯切道进行线性切割的卡盘工作台103构成。
晶片安装于卡盘工作台103上,其间具有切片胶带104。
在切割操作期间,锯割刀片以高速旋转且卡盘工作台103使晶片101及其下伏层朝向锯割刀片102移动。锯割刀片102接着切穿晶片101。锯割刀片102还切到切片胶带104中但不完全穿过切片胶带104,使得切片胶带可帮助在切割操作期间将裸片固持在一起。重复此过程多次以沿着锯切道切割晶片101。
一旦完成所有切割操作,便将每一裸片抬离切片胶带104且定位到适合衬底或引线框架(未展示)上。将裸片粘附到其下伏衬底。在一些实施方案中,接着将裸片电连接到衬底且包封于模制材料中以形成集成电路封装。
用于将半导体晶片切片的现有布置及方法展现背面损坏及小裸片的乱飞的裸片。存在进一步改进此类技术的有效性的持续努力。
发明内容
下文呈现简化发明内容以便提供对本发明的一或多个方面的基本理解。本发明内容并非本发明的扩展概述,且既不打算识别本发明的关键或紧要元件,也不打算记述其范围。而是,本发明内容的主要目的为以简化形式呈现本发明的一些概念作为稍后所呈现的更详细说明的前言。
根据本申请案的一实施例,提供一种锯割半导体晶片的方法。所述半导体晶片锯割方法包括:提供具有有源装置表面及背表面的半导体晶片;研磨所述晶片的所述背表面直到所述晶片达到所要厚度;将锚定材料应用到所述经研磨晶片的所述背表面;使用热量使所述锚定材料固化;将所述半导体晶片定位于包含锯割刀片及物理上支撑所述半导体晶片的可移动支撑结构的晶片锯割设备中,其中所述半导体晶片使用包含锚定材料及切片胶带的多个连接层与所述支撑结构耦合;借助所述锯割刀片切割所述晶片及所述锚定材料,其中在所述切割操作期间,所述锯割刀片的接触部分切割所述切片胶带的一部分;使用所述切割操作单切所述半导体晶片以形成多个集成电路裸片,每一集成电路裸片具有顶部表面、相对底部表面及侧表面,每一集成电路裸片的所述底部表面覆盖有所述锚定材料。
附图说明
可通过参考连同附图一起进行的以下说明来最佳地理解本发明及其优点,附图中:
图1是实例性锯割刀片及使用切片胶带与卡盘工作台耦合的半导体晶片的图解性侧视图。
图2是图解说明提供半导体晶片以将所述晶片上的裸片组装成经封装装置的过程的流程图。
图3图解说明半导体晶片,在晶片的一个表面上具有有源装置。
图4图解说明半导体晶片,在背面研磨之后在晶片的一个表面上具有有源装置。
图5图解说明半导体晶片,在背面研磨之后在晶片的一个表面上具有有源装置,其中锚定材料应用到所述背面。
图6图解说明图5中的经烘焙以使图5中所应用的锚定材料固化的半导体晶片。
图7图解说明图6中的安装于切片胶带上的半导体晶片。
图8图解说明图7中的经锯割以单切个别裸片的半导体晶片。
图9图解说明来自图8中的半导体晶片的经拾取以放置并安装于衬底上的经单切裸六。
图10是经封装裸片的图解性视图。
在图式中,相同元件符号有时用于标示相同结构元件。还应了解,各图中的描绘为示意性的且并不按比例。
具体实施方式
参考附图描述本发明。所述图未按比例绘制且其仅经提供以图解说明本发明。下文参考用于图解说明的实例性应用来描述本发明的数个方面。应理解,众多特定细节、关系及方法经陈述以提供对本发明的理解。然而,相关领域的技术人员将容易地认识到,可在不使用所述特定细节中的一或多者或者使用其它方法的情况下实践本发明。在其它实例中,未详细展示众所周知的结构或操作以避免使本发明模糊。本发明不受动作或事件的所图解说明排序限制,这是因为一些动作可以不同次序发生及/或与其它动作或事件同时发生。此外,未必需要所有所图解说明的动作或事件来实施根据本发明的方法。
本发明一般来说涉及用于将半导体晶片切片的方法及布置。更具体来说,本发明的各种实施例涉及一种在切片之前将锚定层添加到半导体晶片的背面的方法。
常规切片技术虽然对于许多应用有效,但可在使用机械锯刀片来切割0.2毫米(mm)×0.2mm的区域中的非常小的裸片大小时导致若干问题。使用图1中所图解说明的方法,可发生如侧壁碎裂、背面碎裂及裸片脱离切片胶带等问题。
如图1中所展示,半导体晶片101借助粘合剂附接到切片胶带104。在机械锯割过程期间,机械锯割刀片102切穿半导体晶片101且部分地切割切片胶带104。在锯割过程中,可在半导体晶片101、切片胶带104界面处发生较大的裸片碎裂,这是因为将所述两者固持在一起的粘合剂为相对弱的。另外,由于将所述两者固持在一起的粘合剂为弱的,因此裸片可能倾斜,且旋转的锯刀片可能啮合裸片并将其从切片胶带104弹开。这些问题导致较高数目的缺陷裸片。
本发明的各种实施方案解决以上问题中的一或多者。接下来参考图2到9,将描述根据本发明的实施例的用于对半导体晶片101上的裸片进行切片及分离的经改进方法。
最初,如步骤601中所描述及图3中所图解说明,提供具有包含有源装置105的前表面及背表面的半导体晶片101。
接下来,如步骤602中所描述及图4中所图解说明,研磨半导体晶片101的背表面以提供最终所要晶片厚度。半导体晶片的背面研磨为半导体工业中的众所周知的工艺。
接下来,如步骤603中所描述及图5中所图解说明,将锚定材料106应用到半导体晶片101的背面。可通过选自层压、印刷或旋涂的群组的方式应用锚定材料。所述锚定材料可由具有导电材料、非导电材料或无材料作为填料的聚合物组成。所述锚定材料经设计以具有>2400MPa(在室温下)的弹性模数、>20MPa(在室温下)的剪切强度及在固化之后等于或大于硅的硬度。在实践中,所附接锚定材料106按剪切强度与半导体晶片101统一。以上性质允许单遍次锯割,因此解决背面及侧面碎裂损坏及乱飞的裸片的问题,借此改进合格率及生产量。
由于裸片牢固地固定于锚定材料106上,因此测试已展示背面损坏的减小,尤其是在芯片的小的裸片上从80微米(um)减小到10um。
接下来,如步骤604中所描述及图6中所图解说明,借助在介于150℃与180℃之间的温度下的热量使锚定材料固化达最少1小时。
接下来,如步骤605中所描述及图7中所图解说明,将附接有锚定材料106的半导体晶片101附接到切片胶带107,其中锚定材料106接触切片胶带107的顶部表面。
接下来,如步骤606中所描述及图8中所图解说明,将半导体晶片101、锚定材料106及切片胶带107组合定位于晶片锯割设备(未展示)的卡盘工作台103上。图8是根据本发明的特定实施例的半导体晶片101及晶片锯割设备的各种组件的图解性侧视图。
晶片锯割设备(未展示)包含用于物理上支撑半导体晶片101的支撑结构103(例如,卡盘工作台)及用于切割晶片101的锯割刀片102。
在步骤606及图8处,使用锯割刀片102来切穿半导体晶片101、锚定材料106及部分地切到切片胶带107的一部分中。在图8之所图解说明实施例中,锯割刀片102定位于半导体晶片101上方。支撑结构103(卡盘工作台)的移动对照旋转的锯割刀片102定位半导体晶片101、切片胶带107及其间的锚定材料106(步骤606及图8)。因此,锯割刀片102切割多个层,包含半导体晶片101、锚定材料106及部分地切到切片胶带107中。
上文所使用的锯割刀片102可为此技术领域中已知的用于切割半导体晶片的任何切割仪器。举例来说,在所图解说明实施例中,锯割刀片102为圆形的,在其中心轴上旋转及/或在切割过程期间保持实质上固定。在各种实施例中,取决于半导体晶片101上的锯切道的宽度,步骤606中所使用的锯割刀片102可更厚或更薄。一些方法涉及使用金刚石锯割刀片。
支撑结构103(卡盘工作台)可为经布置以物理上支撑且载运半导体晶片及其下伏层的任何适合结构。一般来说,支撑结构103经布置以朝向固定的锯割刀片线性地移动,使得锯割刀片啮合并切穿晶片/锚定材料堆叠的部分。
在步骤607处,如图9中所图解说明,接着从支撑结构移除经单切集成电路裸片108(及其下伏锚定材料106)且将其定位于适合衬底(例如,引线框架)上。在此步骤中可使用此技术领域中已知的任何适合引线框架或电子衬底设计。
举例来说,在图10之所图解说明实施例中,衬底为具有多个装置区域的引线框架面板。每一装置区域包含多个引线434及一裸片附接垫432。使用裸片附接垫432上的用以附接裸片108的额外粘合剂430,将至少一个集成电路裸片108紧固到裸片附接垫432。
在裸片已定位于衬底上之后,可执行额外封装操作(步骤608,如图10中所图解说明)。举例来说,在所图解说明实施例中,将每一裸片电连接(例如,使用线接合436)到其对应装置区域的引线434。此后,应用模制材料428以实质上同时包封衬底及集成电路裸片424的部分,以形成经模制结构400。接着将经模制结构400单切以形成多个集成电路封装。裸片附接膜430帮助将裸片108粘附到裸片附接垫432,且裸片108电连接到引线434中的至少一者。引线434部分地暴露于封装的外部以充当集成电路封装的电触点。可结合各种各样的封装设计利用裸片附接膜430,图10中的设计仅为所述封装设计的一个实例。
尽管上文已描述本发明的各种实施例,但应理解,所述实施例仅通过实例而非限制的方式呈现。在不背离本发明的精神或范围的情况下,可根据本文中的揭示内容对所揭示实施例做出众多改变。因此,本发明的广度及范围不应受上文所描述的实施例中的任一者限制。而是,本发明的范围应根据所附权利要求书及其等效物来界定。
Claims (8)
1.一种锯割半导体晶片的方法,其包括:
提供具有有源装置表面及背表面的半导体晶片;
研磨所述晶片的所述背表面直到所述晶片达到所要厚度;
将锚定材料应用到所述晶片的所述背表面;
使所述锚定材料固化;
将所述半导体晶片定位于晶片锯割设备中,所述晶片锯割设备包含锯割刀片及物理上支撑所述半导体晶片的可移动支撑结构,其中所述半导体晶片是使用包含锚定材料及切片胶带的多个连接层与所述支撑结构耦合;
借助所述锯割刀片切割所述晶片及所述锚定材料,其中在所述切割操作期间,所述锯割刀片的接触部分切割所述切片胶带的一部分;
使用所述切割操作单切所述半导体晶片以形成多个集成电路裸片,每一集成电路裸片具有第一表面、相对第二表面及侧表面,每一集成电路裸片的所述第二表面覆盖有所述锚定材料。
2.根据权利要求1所述的方法,其进一步包括:
将经单切裸片中的第一裸片定位于衬底的装置区域上,其中下伏于所述第一裸片下的所述锚定材料帮助将所述第一裸片粘附到所述衬底;
将所述第一裸片电连接到所述衬底;以及
包封所述衬底及所述裸片的部分以形成集成电路封装。
3.根据权利要求2所述的方法,其中:
所述衬底为包含多个装置区域的引线框架面板;
所述方法进一步包括将所述多个集成电路裸片定位于所述引线框架面板的所述装置区域上;
将所述多个集成电路裸片电连接到所述引线框架面板;
包封所述引线框架面板及所述集成电路裸片的部分以形成经模制面板;以及
单切所述经模制面板以形成多个集成电路封装,每一集成电路封装包含所述集成电路裸片中的至少一者。
4.根据权利要求1所述的方法,其中所述切割操作不涉及完全切穿所述切片胶带,且其中所述切片胶带经布置以帮助在所述切割操作之后将经单切裸片固持在一起。
5.根据权利要求1所述的方法,其中所述锚定材料由填充有导电填料或非导电填料的聚合物组成。
6.根据权利要求1所述的方法,其中所述锚定材料具有在室温下大于2400MPa的弹性模数、在室温下大于20MPa的剪切强度及等于或大于硅的硬度。
7.根据权利要求1所述的方法,其中在介于150℃与180℃之间的温度下使所述锚定材料固化达最少1小时。
8.根据权利要求1所述的方法,其中所述锚定材料应用是选自由层压、印刷或旋涂组成的群组。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/098,018 US8993412B1 (en) | 2013-12-05 | 2013-12-05 | Method for reducing backside die damage during die separation process |
US14/098,018 | 2013-12-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104701156A CN104701156A (zh) | 2015-06-10 |
CN104701156B true CN104701156B (zh) | 2019-03-19 |
Family
ID=52707805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410740485.8A Active CN104701156B (zh) | 2013-12-05 | 2014-12-05 | 用于在裸片分离过程期间减小背面裸片损坏的方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8993412B1 (zh) |
CN (1) | CN104701156B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10090177B1 (en) * | 2017-08-25 | 2018-10-02 | Micron Technology, Inc. | Cold fluid semiconductor device release during pick and place operations, and associated systems and methods |
US10991621B2 (en) * | 2019-08-05 | 2021-04-27 | Texas Instruments Incorporated | Semiconductor die singulation |
CN113206024B (zh) * | 2020-01-31 | 2024-09-20 | 台湾积体电路制造股份有限公司 | 剥离系统及剥离方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101850538A (zh) * | 2009-04-01 | 2010-10-06 | 日月光半导体制造股份有限公司 | 晶圆的支撑治具与研磨、输送及切割晶圆的方法 |
CN101859851A (zh) * | 2009-02-09 | 2010-10-13 | 株式会社迪思科 | 晶片的加工方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6908784B1 (en) * | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
TWI520269B (zh) * | 2002-12-03 | 2016-02-01 | Hamamatsu Photonics Kk | Cutting method of semiconductor substrate |
JP4933233B2 (ja) * | 2006-11-30 | 2012-05-16 | 株式会社ディスコ | ウエーハの加工方法 |
JP4944642B2 (ja) * | 2007-03-09 | 2012-06-06 | 株式会社ディスコ | デバイスの製造方法 |
JP5061694B2 (ja) * | 2007-04-05 | 2012-10-31 | 信越半導体株式会社 | 研磨パッドの製造方法及び研磨パッド並びにウエーハの研磨方法 |
US7838424B2 (en) * | 2007-07-03 | 2010-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching |
US7824962B2 (en) * | 2008-01-29 | 2010-11-02 | Infineon Technologies Ag | Method of integrated circuit fabrication |
JP5206733B2 (ja) * | 2010-05-25 | 2013-06-12 | 株式会社デンソー | ウェハの加工方法およびそれに用いられる研磨装置、切断装置 |
-
2013
- 2013-12-05 US US14/098,018 patent/US8993412B1/en active Active
-
2014
- 2014-12-05 CN CN201410740485.8A patent/CN104701156B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101859851A (zh) * | 2009-02-09 | 2010-10-13 | 株式会社迪思科 | 晶片的加工方法 |
CN101850538A (zh) * | 2009-04-01 | 2010-10-06 | 日月光半导体制造股份有限公司 | 晶圆的支撑治具与研磨、输送及切割晶圆的方法 |
Also Published As
Publication number | Publication date |
---|---|
US8993412B1 (en) | 2015-03-31 |
CN104701156A (zh) | 2015-06-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106024710B (zh) | 制造半导体器件的方法 | |
JP5798834B2 (ja) | 半導体装置の製造方法 | |
US20020125557A1 (en) | Package of a chip with beveled edges | |
CN102347251A (zh) | 嵌入式晶圆级接合方法 | |
JP2003007652A (ja) | 半導体チップの製造方法 | |
US8647966B2 (en) | Method and apparatus for dicing die attach film on a semiconductor wafer | |
US20130119538A1 (en) | Wafer level chip size package | |
JP6482865B2 (ja) | 半導体装置の製造方法 | |
CN104701156B (zh) | 用于在裸片分离过程期间减小背面裸片损坏的方法 | |
CN105190844A (zh) | 半导体装置的制造方法 | |
US20090039506A1 (en) | Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof | |
CN103426837B (zh) | 半导体封装及形成半导体封装的方法 | |
US20180233470A1 (en) | Handling thin wafer during chip manufacture | |
TWI308781B (en) | Semiconductor package structure and method for separating package of wafer level package | |
US20070190688A1 (en) | Method for manufacturing semiconductor device with protection layer | |
US11735435B2 (en) | Quad flat no lead package and method of making | |
CN103568139A (zh) | 半导体晶片切片方法 | |
TW200308035A (en) | Method for processing multiple semiconductor devices for test | |
US20090025882A1 (en) | Die molding for flip chip molded matrix array package using uv curable tape | |
US20140217613A1 (en) | Integrated device and fabrication process thereof | |
JP2019102568A (ja) | 半導体装置およびその製造方法 | |
TWI688631B (zh) | 黏著片及半導體裝置的製造方法 | |
US20160307831A1 (en) | Method of making a qfn package | |
US7470601B2 (en) | Semiconductor device with semiconductor chip and adhesive film and method for producing the same | |
JP2008159724A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |