CN103568139A - 半导体晶片切片方法 - Google Patents
半导体晶片切片方法 Download PDFInfo
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Abstract
本发明涉及一种制造半导体装置的方法,包括提供具有正面和背面并且其上制造有集成电路的阵列的半导体晶片。所述集成电路具有在晶片的正面上的有源面。从背面沿着在集成电路之间的锯道机械地切割沟槽,部分地切过晶片。接着通过如下来将集成电路单颗化:在正面沿着锯道并在锯道内扫描激光束,其从正面将晶片划片;以及燃后,通过沿着锯道机械地使晶片裂开。
Description
技术领域
本发明涉及半导体集成电路,更具体地,涉及对半导体晶片进行切片(dicing)的方法。
背景技术
制造半导体装置包括在半导体晶片中制备集成电路的阵列。晶片通常由单晶半导体材料(例如,硅)或化合物半导体材料形成。通过例如沉积金属、多晶半导体和其它材料,外延生长,蚀刻,图案化,掺杂和氧化等步骤在晶片中以及晶片上形成电路中的有源和无源元件。集成电路可以包括例如电子元件和微机电系统(MEMS)。
在制备集成电路的阵列之后,将晶片切片以制造单颗化的(singulated)半导体管芯(die)。切片操作包括沿着正交的锯道(saw street)分割半导体装置。传统的切片技术包括通常用锯、激光切割和激光划片的机械切割。半导体管芯的尺寸不断减小而集成在管芯中的电子电路具有相同或者更高的功能性和复杂性,这意味着锯道的宽度可能表示晶片中形成的管芯的密度的显著降低。将期望减小锯道的宽度,从而允许晶片上会有要多的面积用于形成电路。
简要说明
根据本公开一个方面,提供了一种分离形成在晶片上的半导体管芯的方法,包括:提供半导体晶片,所述半导体晶片具有正面和背面并且其中制造有半导体管芯的阵列,所述半导体管芯具有在所述晶片的所述正面的有源面;从所述晶片的背面沿着在所述半导体管芯之间的锯道机械地切割沟槽,部分地切过所述晶片;以及将所述半导体管芯单颗化,包括在所述晶片的正面上,沿着所述锯道并在所述锯道内扫描激光束。
根据本公开另一方面,提供了一种制造半导体装置的方法,包括:提供半导体晶片,所述半导体晶片具有正面和背面并且其中制造有半导体管芯的阵列,所述半导体管芯具有在所述晶片的所述正面的有源面;从所述晶片的背面沿着在所述半导体管芯之间的锯道机械地切割沟槽,部分地切过所述晶片;将所述半导体管芯单颗化,包括在所述晶片正面上,在所述锯道内并沿着所述锯道扫描激光束,其中单颗化的半导体管芯具有边缘,并且所述沟槽在所述边缘中在所述有源面之下形成底切,并且所述有源面具有比所述背面大的宽度;提供具有支撑表面的管芯支撑部件;以及以管芯附接材料将所述半导体管芯的所述背面附接到所述支撑表面,其中该管芯附接材料流入所述底切中并且在所述底切中形成填充物。
附图说明
下面通过示例的方式说明本发明,然而本发明并不限于附图中示出的实施例,在附图中相同的附图标记表标相以的元件。附图中的元件是出于简单清楚的目的而示出的,并不必然按比例绘制。例如,某些垂直的尺寸相对于水平的尺寸有所夸大。
图1是已封装的半导体装置的示意性截面图,其包括使用传统的单颗化技术制造的半导体管芯;
图2和3是在传统的单颗化技术的相继的多个阶段处的包含集成电路阵列的晶片的示意性截面图;
图4到8是以示例的方式给出的、根据本发明一个实施例的制造半导体管芯的方法的单颗化操作的相继的多个阶段处的包含集成电路阵列的晶片的示意性截面图;以及
图9是附图4到8中所示的半导体管芯的制造方法的流程图。
具体实施方式
图1示出了一种已封装的半导体装置100,其包括使用传统的单颗化技术制造的半导体管芯102。半导体管芯102具有有源面104、背面106和边缘108。半导体装置100还包括管芯支撑构件110(例如,引线框的导热板(flag)),其具有接合表面112。半导体管芯102在边缘108处具有沟槽114,位于有源面104中并围绕有源面104。半导体槽芯102的背面106被利用管芯附接材料接合到管芯支撑构件110的接合表面112,其中管芯附接材料的填充物(fillet)116被容纳在沟槽114中。
已封装的半导体装置100包括一组暴露的电接触元件118,其可以由引线框的一部分形成,该引线框还提供管芯支撑件110。半导体管芯102的有源面104具有多个电接触元件120,其与暴露的电接触元件118(诸如,接合引线122)电连接,这可以使用传统引线接合工艺和设备进行。模制化合物124覆盖第一表面104、填充物116和接合引线122。
如图2中所示,制造已封装的半导体装置100包括在晶片200中制备半导体装置102的阵列,它们的有源面104处在晶片200的正面,而它们的背面处在晶片200的背面。晶片200的正面承载有对准标记(未示出),其用来使用于单颗化工艺的锯道与晶片中半导体装置的阵列的结构对准,该对准标记通过在制造半导体装置阵列时使用的工序制造,并与之对准。晶片200被以半导体管芯102的背面106在背衬(backing)202(诸如,粘性支撑膜)上的方式安装。
背衬202上的晶片200被安装在图中由第一锯片(saw blade)204表示的锯中。第一锯片204用来在晶片200的正面中进行第一切割,以在半导体管芯102的有源面104中部分地切过晶片200的厚度形成沟槽206。
第一锯片204是沿着在相邻的半导体管芯102之间的一组平行的锯道和正交的一组平行的锯道移动来形成沟槽206。第一锯片204的移位由晶片200的第一表面104上的对准标记引导。沟槽206的宽度S1由第一锯片204的宽度决定。每个沟槽206将在有源面104和相邻半导体管芯102的边缘108中形成沟槽114。
参见图3,接着,使用第二锯片300来将半导体管芯102单颗化。也就是,第一锯片204被第二锯片300取代,并使用第二锯片300来沿着在相邻的半导体管芯102之间的同样的一组平行的锯道和正交的一组平行的锯道进行第二切割,再次由晶片200正面上的对准标记引导。第二锯片300的宽度S2小于第一锯片204的宽度S1。第二锯片300从与半导体管芯102的有源面104同一侧完全切穿晶片200在沟槽206中剩下的厚度,以将半导体管芯102单颗化。接着,通过管芯附接粘接剂将每一个半导体管芯102附接到管芯支撑构件110的接合表面112,管芯附接粘接剂流入到沟槽114中,形成填充物116,其背容纳在沟槽114中,如图1所示。
由于锯齿切割的定位冗余,在晶片200正面中的锯道具有比第一锯片204的切口宽度S1大的宽度。实际上,以当前可用的技术,难以把锯道的被浪费的宽度减少到40μm以下,这代表着晶片中管芯的有源面的面积的显著减少。
图4到9示出了根据本发明一个实施例的半导体管芯的制造方法。该方法包括提供半导体晶片200,其具有正面400和背面402以及在其中制备的管芯(集成电路)102的阵列。管芯(集成电路)102具有在晶片正面400的有源面104。从背面402沿着管芯(集成电路)102之间的锯道部分地切过晶片200机械地功割出沟槽604。然后,将管芯(集成电路)102单颗化,所述单颗化包括将激光束704沿着锯道并在锯道内扫描到正面400上。
沟槽604减少了晶片200在锯道内的厚度,从而使得单颗化的宽度S2和锯道的被浪费的宽度可以显著减小。沟槽604的宽度S1并不减少可用于管芯(集成电路)102的有源面104的面积,因为沟槽604是从晶片200的背面402切割的而且并不切穿到正面400。
在本发明的方法的实施方式的一个例子中,扫描激光束704从正面400对晶片200划片(scribe),并且将管芯(集成电路)102单颗化包括机械地对晶片200加以负荷以使晶片沿着锯道裂开。将管芯102单颗化包括:在切割沟槽604之后,安装晶片200,以背面402附接到背面粘性支撑元件700。机械地对晶片200加负荷包括径向地拉伸背面粘性支撑元件700,以向背面402施加径向的张应力。在对晶片200的划片操作中,由于通过沟槽604减小了晶片200的厚度,因此可以减小受激光束影响的区域的宽度S2。
在本发明的方法的实施方式的另一个例子中,扫描激光束704从正面400切割晶片200并将管芯(集成电路)102单颗化。再次地,由于通过沟槽604减小了晶片200的厚度,因此可以减小受激光束影响区域的宽度S2。
在本发明的方法的实施方式的一个例子中,激光束704在小于并且被包含在沟槽604宽度内的宽度上改变晶片200的结构。在对晶片200划片的操作中,激光束704产生在正面400之下的缺陷区域。激光束704是脉冲的,并且以分别聚焦在晶片200中的各自的深度的多个扫描来扫描每个锯道。缺陷是由在激光束的焦点处晶片200的材料迅速熔化并且再次凝固而导致的。
在本发明的方法的实施方式的一个例子中,通过图4到9示出的方法制造的半导体管芯具有边缘108,且沟槽604在有源面104下方在边缘108中形成底切。有源面104具有大于背面106的宽度,因为沟槽604是从半导体管芯102的背面106切割的。半导体管芯102的背面106被利用管芯附接材料附接到管芯支撑构件110的支撑面112。管芯时接材料流入由沟槽604形成的底切中,并且在底切中形成填充物116。填充物116被包含在该底切中,而底切并不会减少半导体管芯102的有源面104的面积。
在本发明的方法的实施方式的一个例子中,切割沟槽604包括:安装晶片200,以正面400附接到正面支撑元件500;以及从背面402部分地锯过晶片200。晶片200包括正面400上的对准标记,所述对准标记是可通过正面支撑元件500而被识别的。从背面402部分地锯过晶片是通过正面400上的对准标记引导的。在正面400上的对准标记还可以引导随后的激光束704在正面400上的扫描。
图9概述了根据本发明一个实施例的例子的半导体管芯的制造方法900的步骤。方法900从涉骤902通过提供其中制造有半导体管芯102的阵列的晶片200开始。图4示出了该晶片200,其可以由单晶半导体材料制成(诸如,硅)或者化合物半导体材料形成。通过诸如沉积金属、多晶半导体和其它材料,外延生长,蚀刻,图案化,掺杂,氧化等步骤,在晶片200上或在晶片200中,形成管芯102的有源和无源元件,在很多情况下可以从晶片的正面400开始的操作来执磁步骤。管芯102可以包括构成集成电路(IC)的电子元件和微机电系统(MEMS)。同样的制造步骤形成与半导体管芯102的结构相关地对准的对准标记(未示出)。
在步骤904中,晶片200的背面被研磨,以减小晶片的厚度。在一个例子中,晶片200在制造半导体管芯102的步骤期间是750μm厚,而在背面研磨操作之后是150μm厚。
接着,在步骤906中,安装晶片200,其正面400被附接到正面支撑元件500,如图5中所示。然后,如图6中所示,位于其支撑物500上的晶片200被安装在锯切机中,该锯切机中包括穿过支撑物500感测位于正面400上的对准标记的摄像装置(camera)602和任意卡盘。摄像装置602使得该机器的引导模块能够引导晶片200的相对运动和锯片600的旋转。
在步骤908中,使用锯片600来在晶片200的背面402中进行切割,以在该晶片的背面402和半导体管芯102的背面106中部分地切过晶片200的厚度形成沟槽604。该沟槽沿着锯道的正交的组延伸。沟槽604被示出为具有矩形的截面,但应理解,沟槽604也可以具有任何合适的截面,其通常由锯片600的截面决定。在本例子中,沟槽604的宽度为大约40μm。沟槽604的深度大约为晶片200的厚度的一半(背研磨之后)。
在切割沟槽604之后,将支撑物500从晶片200移开,接着在步骤910中,通过其背面402将晶片200附接到粘性的弹性支持撑物700。在步骤912中,图7中示出的激光器702将激光束704扫描到正面400上,在锯道内并沿着锯道,由与引导切割沟槽604的同样的对准标记引导。激光束704是脉冲的,并且以分别聚焦在晶片200中相应深度的多个扫描来扫描晶片的正面400上的每个锯道。激光束704在正面400之下产生缺陷区域,其在小于并且被包括在沟槽604的宽度内的宽度上对晶片进行划片。在本发明的实施方式的这个例子中,使用了紫外光(波长小于400nm)。在对晶片200划片的操作中,通过沟槽604减小了晶片200的厚度,在这个例子中,激光划片在硅中的深度达20μm,并且受激光扫描影响的区域的宽度S2可以实际减小到10μm以下,这减小了切片道的被浪费的宽度和在晶片中的管芯的有源面的被浪费的面积。
在步骤914中,半导体装置102被单颗化。单颗化操作包括对晶片200的背面402机械地加负荷以使晶片沿着切片道裂开。如图8所示,机械地对晶片200的背面402加负荷是通过如下进行的:急剧地径向地伸展粘生支撑元件700,如箭头800所示,来向背面402施加径向的张应力。半导体管芯102的边缘沿着由切片道所限定的裂开线分开,如802所示。
单颗化之后,在步骤916中,为半导体管芯102提供外部连接元件。外部连接元件可以是图1所示类型的暴露的电接触元件118,由也提供管芯支撑件110的引线框的一部分形成。在半导体管芯102的有源面104上的电接触元件120例如可以通过接合引线122与暴露的电接触元件118电连接。可以将半导体管芯102包封在模制化合物124中。可以将一个或多个管芯包封在同一个封装件内。
应了解,也可以采用其它方式来提供外部电接触,例如球栅阵列(BGA)或平面栅格阵列(LGA),并且可以利用或不利用再分配管芯封装(RCP),其中在有源管芯面上的内部电接触元件通过用于路由信号以及电源和接地连接的再分配面板(redistribution panel)连接到封装件表面上暴露的焊盘(pad)。还应了解,半导体管芯也可以封装在所述包封以外的其它封装内,并且替代地,也可以“裸着”(bare)提供半导体管芯以整合在装置中然后将该装置封装。
在前文的说明中,已经参考本发明的实施例的具体例子描述了本发明。然而,很明显,其中可以进行各种修改和改变,而不脱离如所附权利要求所限定的本发明的宽泛的宗旨和范围。
例如,此处描述的半导体衬底可以是任何半导体材料或材料的组合,例如砷化镓、硅锗、绝缘体上硅(SOI)、硅、单晶硅等以及上述的组合。
此外,说明书中和权利要求中的“正”、“背”、“顶”、“底”、“上”、“下”等术语(如果有的话),被用于描述的目的,并不必然描述永久性的相对位置。应理解,这样使用的术语在某些合适的情况下是可互换的,从而此处描述的本发明的实施例例如能够在此处示出或以其它方式描述的取向之外的其它取向上操作。
此外,本领域技术人员应理解,上述的操作之间的分界仅仅是说明性的。多个操作可以合并成一个操作,一个操作可以分布在额外的操作中,并且可以以在时间上至少部分重叠的方式执行多个操作。此外,替代的实施例可以包括特定操作的多个例子,并且在不同的其它实施例中操作的顺序可以改变。
在权利要求中,“包含”或“具有”的字样并不排除权利要求中所列的要素之外的其它要素或步骤的存在。此处所用的术语“一”(“a”或“an”)被定义为一个或多于一个。此外,权利要求中的引语如“至少一个”和“一个或多个”,的使用不应被理解为暗示由“一”(不定冠词“a”或“an”)所引述的另一个权利要求要素将包含这样引述的权利要求的任何特定权利要求限制到仅包含一个这样的要素的发明,即使当在同一权利要求中包含引语“一个或多个”或“至少一个”以及“一”(不定冠词“a”或“an”)时也是如此。定冠词的使用也是如此。除非另外说明,诸如“第一”和“第二”这样的术语被用来任意地区分这些术语描述的要素。因此,这些术语并不必然用来表示这些要素的在时间上的或其它的优先次序。在彼此不同的权利要求中引述了某些手段并不意味着不能有利地使用这些手段的组合。
Claims (19)
1.一种分离形成在晶片上的半导体管芯的方法,包括:
提供半导体晶片,所述半导体晶片具有正面和背面并且其中制造有半导体管芯的阵列,所述半导体管芯具有在所述晶片的所述正面的有源面;
从所述晶片的背面沿着在所述半导体管芯之间的锯道机械地切割沟槽,部分地切过所述晶片;以及
将所述半导体管芯单颗化,包括在所述晶片的正面上,沿着所述锯道并在所述锯道内扫描激光束。
2.如权利要求1所述的方法,其中扫描所述激光束,将所述晶片从所述正面划片,并且将所述半导体管芯单颗化包括对所述晶片机械地加负荷以使所述晶片沿着所述锯道裂开。
3.如权利要求2所述的方法,其中单颗化所述半导体管芯包括:切割所述沟槽之后安装所述晶片,以其背面附接到背面粘性支撑元件。
4.如权利要求3所述的方法,其中机械地时所述晶片加负荷包括:径向地拉伸所述背面粘性支撑元件以向所述背面施加径向的张应力。
5.如权利要求1所述的方法,其中所述晶片包括在所述正面上的对准标记,所述对准标记引导所述激光束的所述扫描。
6.如权利要求1所述的方法,其中所述激光束在小于并且被包含在所述沟槽的宽度内的宽度上改变所述晶片的结构。
7.如权利要求1所述的方法,其中所述激光束是脉冲的,并以分别聚焦在所述晶片中的相应深度的多个扫描来扫描每一所述锯道。
8.如权利要求1所述的方法,进一步包括:
对所述晶片进行背研磨以提供所述背面。
9.如权利要求1所述的方法,其中切割所述沟槽包括:安装所述晶片,以其所述正面附接到正面支撑元件;以及从所述背面部分地锯过所述晶片。
10.如权利要求9所述的方法,其中所述晶片包括在所述正面上的对准标记,所述对准标记穿过所述正面支撑元件而被感测,并且引导所述从所述背面部分地锯过所述晶片。
11.如权利要求10所述的方法,其中所述正面上的所述对准标记引导所述激光束的扫描。
12.一种制造半导体装置的方法,包括:
提供半导体晶片,所述半导体晶片具有正面和背面并且其中制造有半导体管芯的阵列,所述半导体管芯具有在所述晶片的所述正面的有源面;
从所述晶片的背面沿着在所述半导体管芯之间的锯道机械地切割沟槽,部分地切过所述晶片;
将所述半导体管芯单颗化,包括在所述晶片正面上,在所述锯道内并沿着所述锯道扫描激光束,其中单颗化的半导体管芯具有边缘,并且所述沟槽在所述边缘中在所述有源面之下形成底切,并且所述有源面具有比所述背面大的宽度;
提供具有支撑表面的管芯支撑部件;以及
以管芯附接材料将所述半导体管芯的所述背面附接到所述支撑表面,其中该管芯附接材料流入所述底切中并且在所述底切中形成填充物。
13.如权利要求12所述的方法,其中扫描所述激光束从所述正面将所述晶片划片,并且单颗化所述半导体管芯包括对所述晶片机械地加负荷以使所述晶片沿着所述锯道裂开。
14.如权利要求13所述的方法,其中单颗化所述半导体管芯包括:在切割所述沟槽之后,安装所述晶片,以其背面附接到背面粘性支撑元件。
15.如权利要求14所述的方法,其中机械地对所述晶片加负荷包括:径向地拉伸所述背面粘性支撑元件以向所述背面施加径向的张应力。
16.如权利要求12所述的方法,其中所述激光束在小于并且被包含在所述沟槽的宽度内的宽度改变所述晶片的结构。
17.如权利要求12所述的方法,其中所述激光束是脉冲的,并且以分别聚焦在所述晶片中相应深度的多个扫描扫描每一所述锯道。
18.如权利要求12所述的方法,进一步包括:
对所述晶片进行背研磨以提供所述背面。
19.如权利要求12所述的方法,其中切割所述沟槽包括:
安装所述晶片,以其正面附接到正面支撑元件,以及从所述背面部分地锯过所述晶片。
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Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US7727875B2 (en) * | 2007-06-21 | 2010-06-01 | Stats Chippac, Ltd. | Grooving bumped wafer pre-underfill system |
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