CN104701147B - 包括质子辐照的制造半导体器件的方法和包括电荷补偿结构的半导体器件 - Google Patents

包括质子辐照的制造半导体器件的方法和包括电荷补偿结构的半导体器件 Download PDF

Info

Publication number
CN104701147B
CN104701147B CN201410727433.7A CN201410727433A CN104701147B CN 104701147 B CN104701147 B CN 104701147B CN 201410727433 A CN201410727433 A CN 201410727433A CN 104701147 B CN104701147 B CN 104701147B
Authority
CN
China
Prior art keywords
semiconductor substrate
irradiation
annealing
charge compensation
doped regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410727433.7A
Other languages
English (en)
Other versions
CN104701147A (zh
Inventor
W.彦切尔
H-J.舒尔策
W.舒施特雷德
H.施特拉克
H.韦伯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN104701147A publication Critical patent/CN104701147A/zh
Application granted granted Critical
Publication of CN104701147B publication Critical patent/CN104701147B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及包括质子辐照的制造半导体器件的方法和包括电荷补偿结构的半导体器件。一种制造半导体器件的方法包括在半导体衬底中形成电荷补偿器件结构。所述方法还包括测量涉及电荷补偿器件的电特性的值。基于测量值调整质子辐照和退火参数中的至少一个。基于经调整的质子辐照和退火参数中的所述至少一个，利用质子辐照半导体衬底，并且此后对半导体衬底退火。

Description

包括质子辐照的制造半导体器件的方法和包括电荷补偿结构 的半导体器件
背景技术
被称为电荷补偿或超结（SJ）半导体器件（例如SJ绝缘栅场效应晶体管（SJIGFET））的半导体器件基于半导体衬底中的n和p掺杂区的相互空间电荷补偿，允许低区域专用导通状态电阻Ron x A与诸如源极和漏极之类的负载端子间的高击穿电压Vbr之间的改进的折衷。电荷补偿或SJ半导体器件的性能取决于n掺杂区和p掺杂区之间的横向或水平电荷平衡。工艺容差造成目标电荷平衡的偏差，该偏差可能导致诸如源极到漏极击穿电压的降低之类的器件性能的不合期望的下降。
期望改进区域专用导通状态电阻与半导体器件的阻断电压之间的折衷并且减小工艺容差对该折衷的影响。
发明内容
实施例涉及制造半导体器件的方法。在半导体衬底中形成电荷补偿器件结构。测量涉及电荷补偿器件的电特性的值。基于测量值调整质子辐照和退火参数中的至少一个。基于经调整的质子辐照和退火参数中的所述至少一个，用质子辐照半导体衬底，并且此后，对半导体衬底退火。
根据半导体器件的实施例，半导体器件包括电荷补偿结构，所述电荷补偿结构包括沿横向方向在半导体衬底中连续布置的p掺杂区和n掺杂区。半导体器件还包括主导p掺杂区的掺杂分布的第一掺杂剂种类和主导n掺杂区的掺杂分布的第二掺杂剂种类。半导体器件还包括p掺杂区和n掺杂区中的氢相关施主。氢相关施主不同于第二掺杂剂种类。
根据半导体器件的另一实施例，半导体器件包括电荷补偿结构，所述电荷补偿结构包括沿横向方向在半导体衬底中连续布置的p掺杂区和n掺杂区。半导体器件还包括电荷补偿结构与半导体衬底的第二侧之间的n掺杂场截止区。在n掺杂场截止区的范围内，氢相关施主的范围末端峰值分布小于n掺杂场截止区的另一n型掺杂剂种类的分布。
在阅读了以下详细描述并且查看了附图时，本领域技术人员将认识到附加的特征和优点。
附图说明
附图被包括以提供对本公开的进一步理解并被并入到本说明书中且构成本说明书的一部分。各图图示了本公开的实施例并连同描述一起用于解释本公开的原理。其它实施例和预期优点将随着它们通过参考以下详细描述变得更好理解而易于领会。
图1A至1E是关于不同工艺特征图示了半导体器件的一个实施例的示意图。
图2是图示了通过用质子辐照图1A中图示的半导体衬底后跟退火工艺而生成的氢相关施主的分布的一个示例的示意图。
图3是图示了通过用质子多次辐照图1A中图示的半导体衬底后跟退火工艺而生成的氢相关施主的分布的另一示例的示意图。
图4A是图示了沿图1B中图示的半导体衬底的线B-B'的包括氢相关施主的n型掺杂剂分布的实施例的示意图。
图4B是图示了沿图1B中图示的半导体衬底的线C-C'的包括氢相关施主的n型和p型掺杂剂分布的实施例的示意图。
图4C是图示了沿图1B中图示的半导体衬底的线D-D'的包括氢相关施主的n型掺杂剂分布的实施例的示意图。
图5是具有电荷补偿结构的横向半导体器件的一个实施例的示意性横截面视图，该电荷补偿结构包括电荷补偿结构的交替p型区和n型区二者中的氢相关施主。
具体实施方式
在以下详细描述中，对附图进行参考，附图形成该详细描述的一部分，并且在附图中通过图示的方式示出其中可实践本公开的特定实施例。应当理解，在不脱离本发明的范围的情况下，可以利用其它实施例并且可以做出结构或逻辑的改变。例如，针对一个实施例图示或描述的特征可以用在其它实施例上或者与其它实施例结合使用以产生又一实施例。意图在于本公开包括这样的修改和变型。使用不应当被理解为限制随附权利要求的范围的特定语言来描述示例。附图不是按比例绘制的且仅仅出于图示的目的。为了清楚起见，如果没有另行陈述，已经在不同图中通过对应的附图标记来指代相同的元件。
术语“具有”、“含有”、“包含”、“包括”等是开放式的，并且所述术语指示所陈述的结构、元件或特征的存在但不排除附加元件或特征的存在。冠词“一”、“一个”和“该”旨在包括复数以及单数，除非上下文以其它方式明确指示。
术语“电连接”描述电连接的元件之间的永久低欧姆连接，例如所涉及的元件之间的直接接触或经由金属和/或高掺杂半导体的低欧姆连接。术语“电耦合”包括：被适配用于信号传输的一个或多个居间元件可以存在于电耦合的元件之间，例如暂时提供第一状态中的低欧姆连接和第二状态中的高欧姆电去耦合的元件之间。
各图通过在掺杂类型“n”或“p”旁边指示“-”或“+”来图示相对掺杂浓度。例如，“n-”意指比“n”掺杂区的掺杂浓度低的掺杂浓度，而“n+”掺杂区具有比“n”掺杂区高的掺杂浓度。相同相对掺杂浓度的掺杂区不一定具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区可以具有相同或不同的绝对掺杂浓度。
图1A至1E涉及制造半导体器件的实施例。
方法包括在半导体衬底中形成电荷补偿器件结构。在图1A的示意性顶视图中，图示了半导体衬底105的部分。半导体衬底105可以是包括多个半导体管芯107的半导体晶片。每一个半导体管芯107包括电荷补偿器件结构。半导体管芯107之间的区域可以用于例如通过划线和断裂、通过机械锯切或通过激光切割完成的晶片切块。用于监视工艺稳定性的测试结构可以布置在区域108中。测试结构可以包括p掺杂区和n掺杂区中的若干或任何组合之间的pn结。此外或者作为替换方案，测试结构还可以包括用于监视p掺杂区和n掺杂区的薄层电阻的电阻器。当在区域108中布置测试结构时，可以在将晶片105切块成单颗化管芯107之前实施测试结构的测量。
图1B图示了沿图1A中图示的半导体管芯107的线A-A'的横截面视图的一个实施例。半导体管芯107包括电荷补偿器件结构，该电荷补偿器件结构包括沿横向方向x交替的交替n掺杂区和p掺杂区111、112。根据实施例，n掺杂区111和p掺杂区112平行延伸为沿与图1B的绘图平面垂直的横向方向的条带。根据另一实施例，p掺杂区112构成被关于图1B的顶视图作为连续n掺杂区的n掺杂区111围绕的分离的p掺杂柱或岛。根据另一实施例，n掺杂区111是被关于图1B的顶视图作为连续p掺杂区的p掺杂区112围绕的分离的n掺杂柱或岛。p掺杂岛或n掺杂岛的顶视图可以是例如方形的、矩形的、圆形的或多边形的。在图1B中图示的实施例中，半导体管芯107包括垂直超结（SJ）n沟道场效应晶体管（NFET）。垂直SJ NFET包括处于电荷补偿器件结构与n+掺杂漏极区115之间的可选的n掺杂场截止区114。每一个p掺杂区112邻接p掺杂体区117的底侧。p掺杂体区117经由可选的p+掺杂体接触区121在半导体衬底105的第一侧120处电耦合到源极接触118。n+掺杂源极区122邻接第一侧120且电耦合到源极接触118。包括栅电介质124和栅电极125的栅极结构布置在第一侧120处的半导体衬底105上且被配置成通过场效应来控制沟道区127中的导电性。由此，可以控制第一侧120处的源极接触118与第二侧128处的漏极接触127之间的电流流动。源极和漏极接触118、127可以包括诸如（一个或多个）金属和/或（一个或多个）高掺杂半导体材料之类的导电材料。在图1B中图示的实施例中，源极和漏极接触118、127在以下关于图1C到1E描述的后续方法特征之前存在。根据另一实施例，源极和漏极接触中的至少一个（例如，源极接触118或漏极接触127或者接触118、127二者）将被形成在以下关于图1C至1E描述的方法特征之后。
图1B中图示的垂直SJ NFET是包括电荷补偿器件结构的半导体器件的一个示例。其它实施例可以例如包括垂直SJ p沟道FET、在公共侧处包括源极和漏极接触的横向SJFET、横向或垂直绝缘栅双极型晶体管（IGBT）。
参考图1C中图示的示意图，该方法还包括测量涉及电荷补偿器件结构的电特性的值。在图1C中图示的实施例中，半导体衬底105布置在载体130上，并且经由测量装置132测量电特性。测量装置132可以包括晶片探测器。作为示例，半导体衬底可以被真空安装在晶片夹上并经由达到与半导体衬底105电接触的探测器而电连接。当已经测量管芯的电特性时，晶片探测器将半导体衬底105移动到下一管芯，并且下一管芯的电特性的测量可以开始。根据实施例，电特性例如对应于SJ FET的源极和漏极之间或者IGBT的集电极和发射极之间的击穿电压Vbd。可以在SJ半导体器件的相应电极之间或者关于布置在半导体管芯107的区域内和/或图1A中图示的区域108内的测试结构测量击穿电压Vbd。根据实施例，金属电极提供对测试结构的电接触，但是任何金属结构在电荷补偿器件结构的区域中缺失。根据又一实施例，在没有任何居间金属结构的情况下使探测器达到与半导体衬底的高掺杂半导体区接触。根据又一实施例，金属电极和/或接触支持层（例如高掺杂多晶硅层）布置在半导体衬底上以用于减小探测器和半导体衬底之间的接触电阻并可以在关于图1D描述的质子辐照之前被移除。
电特性表征电荷补偿器件结构关于目标值的电荷平衡。由于电荷平衡构成用于n和p掺杂区111、112中的总体电荷的校正的参考参数，因此可以关于具有作为用于校正的参考参数的n和p掺杂区111、112中的总体电荷的校正过程改进校正的精度。
基于涉及电荷补偿器件结构的电特性的测量值，调整质子辐照和/或退火参数。根据实施例，基于电特性的测量值调整质子辐照的数目、剂量和能量中的至少一个。根据实施例，经调整的质子辐照参数包括处于2 x 1014 cm-2和8 x 1014 cm-2的范围中的注入剂量和处于1.0 MeV和3.0 MeV的范围中的注入能量。根据实施例，经调整的质子辐照参数被配置成基于电特性的测量值将电荷补偿器件结构的电荷平衡移位朝向或到电荷补偿器件结构的目标电荷平衡。利用经调整的质子辐照参数对半导体衬底的辐照将生成氢相关施主，造成电荷补偿器件结构的p和n掺杂区111、112二者中的n掺杂的增加。
参考图1D的示意图，该方法还包括基于经调整的质子辐照参数（参看图1D中的）用质子辐照半导体衬底105。根据实施例，从第一侧（例如半导体衬底105的前侧）辐射半导体衬底105。在第一侧120处，诸如（一个或多个）栅电极之类的（一个或多个）控制电极可以被布置且电耦合到布线区域。根据另一实施例，从与第一侧120相对的第二侧128用质子辐照半导体衬底105。在第二侧128处，可以布置SJ FET的漏电极或IGBT的集电极电极。根据又一实施例，从第一和第二侧120、128用质子辐照半导体衬底105。
参考图1E的示意图，该方法还包括对半导体衬底105退火。根据实施例，在诸如腔或炉之类的退火装置中在惰性气氛或空气下实施退火。退火温度典型地在350℃和550℃之间或者在380℃和500℃之间的范围。退火的持续时间典型地在30分钟和10小时之间的范围，例如在1和5小时之间。所得到的施主浓度和垂直分布也可以通过退火温度和退火持续时间而调整。
主导地在质子注入的所谓范围末端区中且在较小程度上在被辐射穿过的区中实施掺杂。衬底105的退火造成氢到被辐照的区域中的扩散且还可以到达被辐射穿过的表面，由此包括氢原子和像例如空位之类的辐照引起的缺陷的复合体的形成导致施主（例如在该区中所谓氢相关施主）的创建。
由于质子辐照和退火参数中的至少一个基于涉及电荷补偿器件的电特性的测量值，因此可以关于电荷补偿器件结构的电压吸收量的总体深度（例如，关于电荷补偿器件的漂移区的总体深度）实施电荷补偿器件结构的n掺杂区和p掺杂区111、112中的电荷平衡的精确校正过程。根据实施例，氢相关施主在半导体衬底的第一侧和第二侧之间的漂移区的垂直延伸的至少30%上延伸。根据另一实施例，氢相关施主的浓度在5 x 1013 cm-3和8 x1014 cm-3的范围中。
如在图1E和1C之间的虚线141所指示，可以重复上述校正过程。根据实施例，如关于图1C描述的那样再次测量电特性，并且根据所测量的电特性是否在容差范围之外，可以实施如在图1D和1E中图示的质子辐照和退火以增加电荷补偿器件结构的电荷平衡中的n电荷的数目。在电特性的测量值揭示n型电荷关于电荷补偿器件结构中的目标电荷平衡的过量的情况下，如图1D中图示的质子辐照可以被免除，并且电荷补偿器件结构中的n型电荷的数目可以通过如图1E中图示的对半导体衬底105退火的附加工艺而减少。因此，根据n型电荷还是p型电荷主导电荷补偿器件结构的电荷平衡，朝向目标电荷平衡的校正过程可以免除附加的质子注入并通过半导体衬底的附加退火工艺（参看图1E）减少电荷补偿器件结构中的n型电荷的数目，或者在电荷补偿器件结构中的过量p型电荷的情况下，n型电荷的数目可以通过如图1D、1E中图示且如上文描述的附加质子注入和退火而增加。另外，根据实施例，可以利用被配置成去激活由质子辐照和退火生成的施主的至少一部分的热预算来实施对半导体衬底退火。由此，由质子辐照和退火生成的氢相关施主的浓度也可以减小。
图2图示了氢相关施主的浓度c1相对于半导体衬底的深度d的测量分布。质子辐照从第一侧发生，例如沿可对应于例如图1B中图示的方向y的增加深度d的值的方向。归因于通过热处理在范围末端区域151中氢/空位-复合体的创建而引起的氢的扩散和施主的形成造成区域152中的利用氢相关施主的几乎均质的掺杂。通过适当调整诸如质子辐照剂量、质子辐照能量、退火温度和退火持续时间之类的参数，可以将范围末端区域151调整成落在电荷补偿器件的场截止区内，并且可以将利用氢相关施主的几乎均质的掺杂的区域152调整成落在电压吸收区（例如电荷补偿器件的电荷补偿器件结构的漂移区）内。
图3图示了氢相关施主的浓度c2相对于半导体衬底的深度d的测量分布。多个质子辐照从第一侧发生，例如沿可对应于例如图1B中图示的方向y的增加深度d的值的方向。归因于通过热处理在范围末端区域中和之间氢/空位-复合体的创建而引起的氢的扩散和施主的形成造成氢相关施主的重叠分布，而峰值区域1530、1531、1532、1533中的每一个与分离的质子注入过程相关联。关于峰值区域在图3中图示的质子注入的序列是例如1530、1531、1532、1533。分布1530的展宽大于在峰值区域1531、1532、1533中。同样地，峰值区域1531中的分布的展宽大于在峰值区域1532、1533中，并且峰值区域1532中的分布的展宽大于在峰值区域1533中，这是由于导致范围末端峰值的增加的宽度的更大辐照能量。
通过适当调整诸如质子辐照剂量、质子辐照能量、退火温度和退火持续时间之类的参数，可以关于例如峰值高度、展宽、峰值深度、与相邻峰值区域的重叠调整峰值区域1530、1531、1532、1533。
根据其它实施例，可以从诸如图1B中图示的第一和第二侧120、128之类的相对侧实施质子辐照。
图4A是图示了沿图1B中图示的半导体衬底105的线B-B'的n型掺杂剂分布的实施例的示意图。
所图示的掺杂剂分布涉及n型区111。n型区111包括第一浓度N1的n型掺杂剂。掺杂剂浓度N1可以是通过在制造电荷补偿器件结构时原位掺杂（例如在外延生长或沉积期间原位掺杂）来形成的。此外或者作为替换方案，浓度N1可以是通过n型掺杂剂的离子注入来形成的，例如在通过例如所谓多外延技术制造电荷补偿器件结构时。根据实施例，掺杂剂浓度N1的掺杂剂种类可以包括磷（P）、锑（Sb）和砷（As）中的一个或多个。n型掺杂剂的第一浓度N1的分布可以几乎是恒定的或者包括可能由多外延技术中的n型掺杂剂的多个离子注入过程所致的波动。
除n型掺杂剂的第一浓度N1之外，根据实施例，n型区111还包括氢相关施主的第二浓度N20，其几乎是均质的且通过如例如在图2中图示的单个质子注入而形成。
第二浓度N20可以是结合如图1C至1D中图示校正电荷补偿器件结构中的电荷平衡来形成的，即，在测量涉及电荷补偿器件结构的电特性、基于测量值调整质子辐照和退火参数、基于经调整的质子辐照和退火参数用质子辐照半导体衬底并且对半导体衬底退火之后。
根据另一实施例，氢相关施主的第二浓度N21可以包括归因于由如例如在图3中图示的不同能量处的多个质子辐照所致的氢相关施主的重叠分布而引起的多个峰值。
类似于图4A中图示的第二浓度N20，第二浓度N21也可以是结合如图1C至1D中图示校正电荷补偿器件结构中的电荷平衡来形成的，即，在测量涉及电荷补偿器件结构的电特性、基于测量值调整质子辐照和退火参数、基于经调整的质子辐照和退火参数用质子辐照半导体衬底并且对半导体衬底退火之后。
图4B是图示了沿图1B中图示的半导体衬底105的线C-C'的p型和n型掺杂剂分布的实施例的示意图。沿线C-C'的净掺杂是p型的且涉及p型区112。p型区112包括第一浓度P1的p型掺杂剂。掺杂剂浓度P1可以归因于在制造电荷补偿器件结构时的原位掺杂，例如在外延生长或沉积期间的原位掺杂。此外或者作为替换方案，浓度P1可以归因于p型掺杂剂的离子注入，例如在通过所谓多外延技术制造电荷补偿器件结构时。根据实施例，掺杂剂浓度P1的掺杂剂种类可以包括硼（B）、铟（In）、铝（Al）、镓（Ga）中的一个或多个。p型掺杂剂的第一浓度P1的分布可以几乎是恒定的或者包括可能由多外延技术中的p型掺杂剂的多个离子注入过程所致的波动。除p型掺杂剂的第一浓度P1之外，根据实施例，p型区112还包括通过氢相关施主的第二浓度N20进行的反向掺杂，第二浓度N20几乎是均质的且由如例如在图2中图示的单个质子注入所致。构成第二浓度N20的氢相关施主可以同时在n型区和p型区111、112中形成以用于例如电荷平衡校正的相同目的。
根据另一实施例，p型区112还包括第二浓度N21的氢相关施主，第二浓度N21具有由如例如在图3中图示的不同能量处的多个质子辐照引起的氢相关施主的重叠分布所致的多个峰值。
图4C是图示了沿图1B中图示的半导体衬底105的线D-D'的n型掺杂剂分布的实施例的示意图。沿线D-D'的分布是沿线C-C'的分布到可选的场截止区114中的延伸。
根据实施例，氢相关施主的第一浓度N20、N21的范围末端峰值位于可选的场截止区114内。
图1A至1E中图示的电荷平衡校正的方法涉及包括负载端子（例如半导体衬底105的相对的第一和第二侧120、128处的源极和漏极）的垂直电荷补偿器件。
该方法还可以适用于其它器件布局。另一器件布局的一个示例是图5中图示的横向电荷补偿或SJ FET 500。横向电荷补偿FET 500包括电荷补偿器件结构，电荷补偿器件结构包括n型区和p型区511、512。n型区和p型区511、512构成布置在n+型源极区522和n+型漏极区515之间的阻断电压吸收漂移区。n+型源极区522布置在p阱517中。源电极518经由可选的p+型接触区521电耦合到p阱517，并且电耦合到n+型源极区522。漏电极527电耦合到n+型源极区515。n型区511经由可选的n-型漏极延伸区545电耦合到n+型漏极区515。
包括栅电介质524和栅电极525的平面栅结构布置在n+型源极区522与n型区和p型区511、512之间p阱517上。栅电极接触546电耦合到栅电极525。在图5的所图示的实施例中，电荷补偿FET 500布置在p型衬底505上。n型区和p型区511、512中的电荷平衡校正可以如图1C至1D中所图示和上文所描述的那样实施。
尽管已经在本文中图示和描述了特定实施例，但是本领域普通技术人员将领会到，在不脱离本发明的范围的情况下，可以用各种替换和/或等同实现替代所示出和描述的特定实施例。本申请旨在覆盖本文所讨论的特定实施例的任何改编和变型。因此，意图在于本发明仅受限于权利要求及其等同物。

Claims (19)

1.一种制造半导体器件的方法，所述方法包括：
在半导体衬底中形成电荷补偿器件结构，其中所述电荷补偿器件结构包括沿横向方向连续布置的p掺杂区和n掺杂区；
测量涉及电荷补偿器件的电特性的值；
基于测量值调整质子辐照和退火参数中的至少一个；
利用质子辐照半导体衬底，以及此后；
基于经调整的质子辐照和退火参数中的所述至少一个来对半导体衬底退火。
2.权利要求1的方法，其中测量涉及电荷补偿器件的电特性的值包括测量电击穿电压。
3.权利要求2的方法，其中所述电击穿电压是关于半导体衬底中的测试结构测量的。
4.权利要求2的方法，其中所述电击穿电压基于关于跨半导体衬底的多个测试结构测量电击穿电压。
5.权利要求1的方法，其中对半导体衬底退火在350℃和550℃的温度范围中实施达30分钟和10小时之间的持续时间。
6.权利要求1的方法，其中基于经调整的质子辐照和退火参数中的所述至少一个利用质子辐照半导体衬底是从电荷补偿器件结构的控制端子位于其中的半导体衬底的第一侧实施的。
7.权利要求1的方法，其中基于经调整的辐照和退火参数中的所述至少一个利用质子辐照半导体衬底被实施一次。
8.权利要求7的方法，其中基于经调整的辐照参数利用质子辐照半导体衬底包括处于2x 1014 cm-2和8 x 1014 cm-2的范围中的注入剂量、处于1.0 MeV和3.0 MeV的范围中的注入能量以及处于380℃和500℃的范围中的退火温度。
9.权利要求7的方法，其中基于经调整的辐照和退火参数中的所述至少一个利用质子辐照半导体衬底将范围末端峰值置于场截止区内。
10.权利要求1的方法，其中基于经调整的辐照和退火参数中的所述至少一个利用质子辐照半导体衬底在不同注入能量和/或注入剂量处实施多次。
11.权利要求10的方法，其中基于经调整的辐照和退火参数中的所述至少一个利用质子辐照半导体衬底包括处于5 x 1013 cm-2和2 x 1014 cm-2范围中的注入剂量以及处于380℃和430℃的范围中的退火温度。
12.权利要求10的方法，其中基于经调整的辐照和退火参数中的所述至少一个利用质子辐照半导体衬底被实施两次和六次之间的次数。
13.权利要求1的方法，还包括：在半导体衬底的质子辐照之后，
在电荷补偿器件结构的控制端子位于其中的半导体衬底的第一侧处形成金属化物；以及此后
在350℃和550℃的温度范围中对半导体衬底退火。
14.权利要求1的方法，还包括：
在电荷补偿器件结构的控制端子位于其中的半导体衬底的第一侧处形成金属化物；此后
利用质子辐照半导体衬底；以及此后
在350℃和550℃的温度范围中对半导体衬底退火。
15.权利要求1的方法，还包括以被配置成去激活由质子辐照和退火生成的施主的至少一部分的热预算对半导体衬底退火。
16.一种半导体器件，包括：
电荷补偿结构，其包括沿横向方向在半导体衬底中连续布置的p掺杂区和n掺杂区；
主导p掺杂区的掺杂分布的第一掺杂剂种类；
主导n掺杂区的掺杂分布的第二掺杂剂种类；
p掺杂区和n掺杂区中的氢相关施主，其中氢相关施主不同于第二掺杂剂种类；以及
电荷补偿结构与半导体衬底的第二侧之间的n掺杂场截止区，其中，在n掺杂场截止区的范围内，氢相关施主的范围末端峰值分布小于n掺杂场截止区的另一n型掺杂剂种类的分布。
17.权利要求16的半导体器件，其中氢相关施主在半导体衬底的第一侧和第二侧之间的漂移区的垂直延伸的至少30%上延伸。
18.权利要求16的半导体器件，其中氢相关施主的浓度处于5 x 1013 cm-3和8 x 1014cm-3的范围中。
19.一种半导体器件，包括：
电荷补偿结构，其包括沿横向方向在半导体衬底中连续布置的p掺杂区和n掺杂区；以及
电荷补偿结构与半导体衬底的第二侧之间的n掺杂场截止区，
其中，在n掺杂场截止区的范围内，氢相关施主的范围末端峰值分布小于n掺杂场截止区的另一n型掺杂剂种类的分布。
CN201410727433.7A 2013-12-04 2014-12-04 包括质子辐照的制造半导体器件的方法和包括电荷补偿结构的半导体器件 Active CN104701147B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/096,804 US9012980B1 (en) 2013-12-04 2013-12-04 Method of manufacturing a semiconductor device including proton irradiation and semiconductor device including charge compensation structure
US14/096804 2013-12-04

Publications (2)

Publication Number Publication Date
CN104701147A CN104701147A (zh) 2015-06-10
CN104701147B true CN104701147B (zh) 2018-04-24

Family

ID=52822550

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410727433.7A Active CN104701147B (zh) 2013-12-04 2014-12-04 包括质子辐照的制造半导体器件的方法和包括电荷补偿结构的半导体器件

Country Status (3)

Country Link
US (1) US9012980B1 (zh)
CN (1) CN104701147B (zh)
DE (1) DE102014117700B4 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015106979B4 (de) * 2015-05-05 2023-01-12 Infineon Technologies Austria Ag Halbleiterwafer und Verfahren zum Herstellen von Halbleitervorrichtungen in einem Halbleiterwafer
DE112016000170T5 (de) 2015-06-17 2017-08-03 Fuji Electric Co., Ltd. Halbleitervorrichtung und Verfahren zur Hestellung einer Halbleitervorrichtung
DE102015115173A1 (de) 2015-09-09 2017-03-09 Infineon Technologies Austria Ag Ein Halbleiterwafer, eine Implantationsvorrichtung zum Implantieren von Protonen und ein Verfahren zum Bilden eines Halbleiterbauelements
DE102016118012A1 (de) 2016-09-23 2018-03-29 Infineon Technologies Ag Halbleiterbauelement und Verfahren zum Bilden eines Halbleiterbauelements

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101083282A (zh) * 2006-05-30 2007-12-05 半导体元件工业有限责任公司 具有下表面沟道电荷补偿区域的半导体器件及方法
US7554137B2 (en) * 2005-10-25 2009-06-30 Infineon Technologies Austria Ag Power semiconductor component with charge compensation structure and method for the fabrication thereof
CN102005383A (zh) * 2009-09-03 2011-04-06 复旦大学 一种赝反铁电薄膜的制备方法
CN102306659A (zh) * 2011-09-08 2012-01-04 浙江大学 一种基于体电场调制的ldmos器件
CN103137688A (zh) * 2011-11-25 2013-06-05 朱江 一种沟槽mos结构半导体装置及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10132136C1 (de) * 2001-07-03 2003-02-13 Infineon Technologies Ag Halbleiterbauelement mit Ladungskompensationsstruktur sowie zugehöriges Herstellungsverfahren
US6566201B1 (en) 2001-12-31 2003-05-20 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
DE102004047749B4 (de) 2004-09-30 2008-12-04 Infineon Technologies Austria Ag Halbleiterbauteil Diode und IGBT sowie dafür geeignetes Herstellungsverfahren
JP5358189B2 (ja) 2006-01-20 2013-12-04 インフィネオン テクノロジーズ オーストリア アクチエンゲゼルシャフト 酸素含有半導体ウェハの処理方法
JP5532758B2 (ja) 2009-08-31 2014-06-25 富士電機株式会社 半導体装置の製造方法および半導体装置
US8421196B2 (en) 2009-11-25 2013-04-16 Infineon Technologies Austria Ag Semiconductor device and manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554137B2 (en) * 2005-10-25 2009-06-30 Infineon Technologies Austria Ag Power semiconductor component with charge compensation structure and method for the fabrication thereof
CN101083282A (zh) * 2006-05-30 2007-12-05 半导体元件工业有限责任公司 具有下表面沟道电荷补偿区域的半导体器件及方法
CN102005383A (zh) * 2009-09-03 2011-04-06 复旦大学 一种赝反铁电薄膜的制备方法
CN102306659A (zh) * 2011-09-08 2012-01-04 浙江大学 一种基于体电场调制的ldmos器件
CN103137688A (zh) * 2011-11-25 2013-06-05 朱江 一种沟槽mos结构半导体装置及其制造方法

Also Published As

Publication number Publication date
CN104701147A (zh) 2015-06-10
DE102014117700A1 (de) 2015-06-11
US9012980B1 (en) 2015-04-21
DE102014117700B4 (de) 2023-09-28

Similar Documents

Publication Publication Date Title
CN107482061B (zh) 超结器件及其制造方法
JP2017139440A (ja) 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
CN105280485B (zh) 制造包括场停止区的半导体器件的方法
CN104701147B (zh) 包括质子辐照的制造半导体器件的方法和包括电荷补偿结构的半导体器件
US10074715B2 (en) Semiconductor wafer, implantation apparatus for implanting protons and method for forming a semiconductor device
CN103050532B (zh) Rf ldmos器件及制造方法
CN106128967B (zh) 半导体晶片及在半导体晶片中制造半导体装置的方法
KR20170105427A (ko) 반도체 장치 형성 방법
CN104518007B (zh) 半导体装置
JPWO2020149354A1 (ja) 半導体装置および半導体装置の製造方法
US20220285501A1 (en) Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
US6969657B2 (en) Superjunction device and method of manufacture therefor
CN107819025A (zh) 半导体装置和半导体装置的制造方法
JP6989061B2 (ja) 半導体装置および製造方法
CN103035731A (zh) 射频横向双扩散场效应晶体管及其制造方法
JP6766522B2 (ja) 半導体装置および半導体装置の製造方法
CN111293040A (zh) 一种n型掺杂离子注入准确度的提升方法
KR101838829B1 (ko) 반도체 장치의 제조 방법
US9786763B2 (en) Semiconductor device and manufacturing method thereof
CN105321809B (zh) 降低杂质浓度的方法、半导体器件及制造其的方法
KR102215042B1 (ko) 낮은 결함 밀도 및 저저항을 갖는 SiC 금속 산화물 반도체 소자의 제조 방법
EP4231358B1 (en) Transistor, power electronic switching device and method for manufacturing a transistor
US9831320B2 (en) High voltage lateral DMOS transistor with optimized source-side blocking capability
CN105493289A (zh) 用于制造绝缘栅双极晶体管的方法
CN104701371B (zh) 射频ldmos器件及制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant