CN104701143A - 用于鲁棒金属化剖面的双层硬掩模 - Google Patents

用于鲁棒金属化剖面的双层硬掩模 Download PDF

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CN104701143A
CN104701143A CN201410756796.3A CN201410756796A CN104701143A CN 104701143 A CN104701143 A CN 104701143A CN 201410756796 A CN201410756796 A CN 201410756796A CN 104701143 A CN104701143 A CN 104701143A
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hard mask
density
mask layer
layer
dielectric layer
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CN104701143B (zh
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潘兴强
谢静华
许宏辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了用于鲁棒金属化剖面的双层硬掩模。通过形成具有不同密度的两个或多个硬掩模的层形成鲁棒金属化剖面。多层金属硬掩模在例如50nm及以下的小部件尺寸工艺中尤其有用。下层具有较高密度。通过这种方式，由下层提供足够的工艺窗口并且同时，由上层提供圆形硬掩模剖面。

Description

用于鲁棒金属化剖面的双层硬掩模
技术领域
本发明涉及用于鲁棒金属化剖面的双层硬掩模。
背景技术
由于按比例减小半导体集成电路的尺寸，所以在工艺中利用硬掩模。硬掩模具有高蚀刻选择性且有助于获得转移图案的高质量各向异性蚀刻。
提高硬掩模的性能的一些方法已经得以发展。其中，这些方法是去除硬掩模且具有较少损坏的技术、去除硬掩模之后清洁残渣的技术、以及调整硬掩模中应力的技术。
发明内容
为克服现有技术中存在的问题，根据本发明的一方面，提供了一种集成电路(IC)结构，包括：衬底；介电层，位于衬底的上方；具有第一密度的第一硬掩模层，位于介电层的上方；具有第二密度的第二硬掩模层，位于第一硬掩模层上；以及开口，延伸穿过第一硬掩模层、第二硬掩模层和介电层；以及导电材料，填充在开口中，其中，第二硬掩模层的第二密度小于第一硬掩模层的第一密度。
根据本发明的一个实施例，部件尺寸为50nm或更小。
根据本发明的一个实施例，还包括位于第二硬掩模层上的具有第三密度的第三硬掩模层，第三密度小于第一密度和第二密度。
根据本发明的一个实施例，第一密度大于约4.8g/cm3并且第二密度小于约4.8g/cm3。
根据本发明的一个实施例，第二密度和第一密度的比小于约0.94。
根据本发明的一个实施例，第二硬掩模层的第二厚度大于第一硬掩模层的第一厚度。
根据本发明的一个实施例，第一硬掩模层或第二硬掩模层是TiN。
根据本发明的另一方面，提供了一种双镶嵌结构，包括：衬底；介电层，位于衬底的上方；通孔结构和沟槽结构，位于介电层中；抗反射涂(ARC)层，位于介电层的上方；具有第一密度的第一硬掩模层，位于ARC层的上方；具有第二密度的第二硬掩模层，位于第一硬掩模层上；以及导电层，填充通孔和沟槽，其中，第二硬掩模层的第二密度小于第一硬掩模层的第一密度。
根据本发明的一个实施例，第一密度大于约4.8g/cm3并且第二密度小于约4.8g/cm3或者第二密度和第一密度的比小于约0.94。
根据本发明的一个实施例，第一硬掩模层和第二硬掩模层包括TiN、氧化物-氮化物-氧化物(ONO)、或氮氧化硅(SiON)。
根据本发明的又一发明，提供了一种形成鲁棒金属化剖面的方法，包括：在衬底上方应用第一介电层；在第一介电层上方接连地应用具有第一密度的第一硬掩模层和具有第二密度的第二硬掩模层；图案化和蚀刻开口穿过第二硬掩模、第一硬掩模和第一介电层；以及在开口中提供导电材料以形成互连结构，其中，第一硬掩模层的第一密度大于第二硬掩模层的第二密度。
根据本发明的一个实施例，还包括：接连地在第一硬掩模层和第二硬掩模层中图案化通孔结构、在第一介电层、第一硬掩模层和第二硬掩模层上方形成第二介电层以及在第二介电层上方形成第三硬掩模层；在第三硬掩模层中图案化沟槽结构；蚀刻通孔结构和沟槽结构；以及在通孔和沟槽中提供导电材料以形成互连结构。
根据本发明的一个实施例，第一介电层是多孔低k材料。
根据本发明的一个实施例，还包括在应用第一硬掩模层之前，将抗反射涂(ARC)层应用在第一介电层上方。
根据本发明的一个实施例，还包括将具有第四密度的第四硬掩模层应用在第二硬掩模层上，第四密度小于第一密度和第二密度。
根据本发明的一个实施例，还包括先图案化和蚀刻通孔然后沟槽、先图案化和蚀刻沟槽然后通孔或自对准通孔(SAV)工艺的方案。
根据本发明的一个实施例，应用具有介于约700A/min至约2000A/min之间的各向异性蚀刻率的干蚀刻以蚀刻通孔结构和沟槽结构。
根据本发明的一个实施例，还包括应用化学机械抛光(CMP)。
根据本发明的一个实施例，导电材料是铜。
根据本发明的一个实施例，通过沉积晶种层和电镀金属形成互连件。
附图说明
图1示出了根据一些实施例的互连结构的截面图。
图2示出了根据一些实施例的双镶嵌互连结构的截面图。
图3示出了形成鲁棒金属化剖面的方法的一些实施例的流程图。
图4a-4h示出了形成鲁棒金属化剖面的方法的一些实施例的截面图。
具体实施方式
参照附图进行本文的描述，其中，在通篇中，相同的参考标号通常用于指代相同的元件，并且其中，各种结构不必按比例绘制。在以下描述中，为了解释的目的，提供了许多具体的细节以便于理解。应当理解，附图的细节不旨在限制本公开，而是非限制性实施例。然而，例如，使用较少程度的这些具体细节可实践本文描述的一个或多个方面对于本领域的技术人员来说是显而易见的。在其他情况下，为了便于理解，以框图形式示出了已知结构和器件。
硬掩模层的使用引入了有助于传递图案的高蚀刻选择性。如图1中虚线109所示，高密度硬掩模在开口蚀刻之后导致相对正方形，这对下列导电材料的填充性能产生负面影响。如图1中点划线111所示，低密度硬掩模在开口蚀刻之后导致相对圆形。然而，低密度硬掩模具有快速的蚀刻率，该蚀刻率在实施蚀刻时降低了工艺窗口。这些问题在例如50nm及以下的小部件尺寸工艺中至关重要。由于减小了部件尺寸，所以提高了对平滑且精确掩模和图案的要求，这样使得导电晶种层和导电晶种层上方的导电层将顺利地形成互连件。通过形成具有逐渐不同密度的多硬掩膜层实现具有相对较圆的外部曲线和精确图案的硬掩模。因此，为形成导电互连件实现了更好的间隙填充和精确的图案化。
图1示出了根据一些实施例的互连结构100的截面图。多孔低k介电层104形成在诸如硅衬底的衬底102上方。抗反射涂(ARC)层106形成在多孔低k介电层104上方。具有第一密度的第一硬掩模层108设置在ARC层106上方。具有第二密度的第二硬掩模层110设置在第一硬掩模层108上。图案化第一和第二硬掩模108和110、ARC层106和介电层104之后，导电层114填充在开口112中以形成对下面的衬底102的连接。
第一硬掩模层108或第二硬掩模层110可以是金属硬掩模层，例如，TiN。第二硬掩模层110的第二密度小于第一硬掩模层108的第一密度。例如，第一密度大于约4.8g/cm3并且第二密度小于约4.8g/cm3。在一些实施例中，第二密度和第一密度的比小于约0.94。在一些实施例中，第二硬掩模层110的第二厚度大于第一硬掩模层108的第一厚度。不同的密度导致不同的各自蚀刻率，其中，密度越低，层的蚀刻率越大。图案化和蚀刻之后，具有相对较低蚀刻率的第一硬掩模层108具有保持图案化精确度的正方形外部曲线，同时具有相对较高蚀刻率的第二硬掩模层110具有有助于后续沉积的导电材料平滑地填充接触件或通孔的圆形外部曲线。在一些实施例中，具有比第二硬掩模层的密度小的密度的第三硬掩模层可进一步地设置在第二硬掩模层上。同样地，可接连地设置具有不同密度的更多硬掩模层。
图2示出了根据一些实施例的双镶嵌互连结构200的截面图。与图1的互连结构100相似，具有相对较小密度的第二硬掩模层210设置在具有相对较大密度的第一硬掩模层208上。第一硬掩膜层比第二硬掩模层薄。在一些实施例中，第一硬掩模层和第二硬掩模层的厚度在约至约的范围内。第二硬掩模层210具有相对较圆的外部曲线，而第一硬掩模层208具有相对较正方形的外部曲线。阻挡层和晶种层(未示出)设置在多孔低k介电层204和导电层214之间。阻挡层和晶种层有助于形成导电层和降低导电材料扩散进介电层204中。沟槽结构205和沟槽下面的通孔结构203形成在多孔低k介电层204中。在一些实施例中，第一蚀刻停止层216可形成在沟槽205的底面附近并且第二蚀刻停止层218可形成在多孔低k介电层204中的通孔203的底面附近以有助于形成沟槽和通孔。
图3示出了形成鲁棒金属化剖面的方法的一些实施例的流程图300。尽管下文以一系列动作或事件示出和描述了本公开的方法(例如，图3的方法300)，但是应当理解，这些动作或事件的所示顺序不应解释为限制意义。例如，一些动作可以不同顺序发生和/或可与除了本文示出和/或描述的这些动作或事件以外的其他动作或事件同时发生。此外，并不需要所有示出的动作用于实施本文描述的一个或多个方面或实施例。此外，在一个或多个单独动作和/或阶段中可进行本文描述的这些动作中的一个或多个。
在步骤302中，在衬底上形成第一介电层。介电层可以是多孔低k材料。
在步骤304中，在第一介电层的上方形成具有第一密度的第一硬掩模层和具有第二密度的第二硬掩模层。在一些实施例中，下面的第一硬掩模层的第一密度大于第二硬掩模层的下面的第二密度。
在步骤306中，在第一硬掩模层和第二硬掩模层中图案化通孔结构。
在步骤308中，在第一介电层、图案化的第一硬掩模层和图案化的第二硬掩模层的上方接连地形成第二介电层和第三硬掩模层。
在步骤310中，在第三硬掩模层中图案化沟槽结构。
在步骤312中，在第一介电层和第二介电层中蚀刻通孔结构和沟槽结构。
在步骤314中，例如铜的导电材料填充在通孔和沟槽中以形成互连结构。
在步骤316中，形成化学机械抛光(CMP)以平坦化互连结构的上区域。
显然地，在一些实施例中，通孔结构和沟槽结构是形成鲁棒金属化剖面的自对准通孔(SAV)工艺双镶嵌结构实例。通过首先图案化和蚀刻通孔然后沟槽、首先图案化和蚀刻沟槽然后通孔、或自对准通孔(SAV)工艺的方案可形成本公开的通孔结构和沟槽结构。在第一介电层中可图案化和蚀刻其他合适的开口结构以形成连接。方法300可进一步包括将具有第四密度的第四硬掩模层应用至第一硬掩模层和第二硬掩模层上，第四密度小于第一密度和第二密度。
现参照图4a至图4h所示的一系列截面图描述图3的方法的一个实例。尽管涉及方法300描述了图4a至图4h，但是应当理解，图4a至图4h中公开的结构不限于这一种方法，但替代地其可独立作为一个结构。
在图4a中，第一介电层404形成在衬底402上。第一介电层404可以是多孔低k材料层并且衬底402可包括任意类型的半导体材料，这包括块体硅晶圆、二元化合物衬底(例如，GaAs晶圆)、或较高阶化合物衬底，此外，有或没有额外的绝缘层或导电层形成在任意类型的半导体材料的上方。
在图4b中，具有第一密度的第一硬掩模层408和具有第二密度的第二硬掩模层410接连地形成在第一介电层404的上方。第一硬掩模层和第二硬掩模层可以是TiN、氧化物-氮化物-氧化物(ONO)、或氮氧化硅(SiON)。第一密度大于第二密度。在一些实施例中，在制造工艺期间通过利用不同的功率和压力使相同的化合物实现不同的密度。
在图4c中，在第一硬掩模层408和第二硬掩模层410中图案化通孔结构403。
在图4d中，第二介电层416形成在第一介电层404、第一硬掩模层408和第二硬掩模层410的上方。第三硬掩模层418接连地形成在第二介电层416的上方。第三硬掩模层具有较大的密度，并且具有比第一硬掩模层和第二硬掩模层低的蚀刻率。
在图4e中，在第三硬掩模层418中图案化沟槽结构405。
在图4f中，蚀刻通孔结构403和沟槽结构405。在一些实施例中，使用具有约1500A/min的各向异性蚀刻率的干蚀刻用于蚀刻。
在图4g中，例如铜的导电材料填充在通孔和沟槽中以形成互连结构414。通过先沉积晶种层然后电镀铜可形成互连结构414。
在图4h中，形成化学机械抛光(CMP)以平坦化互连结构的上区域420。
因此，一些实施例涉及集成电路结构。集成电路结构包括硅衬底、硅衬底上方的多孔低k介电层、具有比上面的第二硬掩模层的密度大的密度的第一硬掩模层。集成电路结构还包括开口和填充开口内以形成连接的导电层。
其他实施例涉及双镶嵌结构。双镶嵌结构包括硅衬底、硅衬底上方的多孔低k介电层、多孔低k介电层上方的抗反射涂层和具有比上面的第二硬掩模层的密度大的密度的第一硬掩模层。双镶嵌结构还包括多孔低k介电层中的由导电层填充的通孔结构和沟槽结构。
另一个实施例涉及形成鲁棒金属化剖面的方法。在该方法中，在衬底上形成第一介电层。介电层可以是多孔低k材料。然后，具有第一密度的第一硬掩模层和具有第二密度的第二硬掩模层接连地形成在第一介电层的上方。第一密度大于第二密度。图案化和蚀刻开口穿过第一和第二硬掩模层，并且然后穿过介电层。导电材料填充在开口中以形成互连结构。
应当理解，尽管在通篇文件中在讨论本文描述的方法的方面提及了示例性结构(例如，图4a至图4h中呈现的结构，同时讨论图3中提出的方法)，但是这些方法不应受所呈现的相应结构的限制。但是，要相互独立地考虑方法(和结构)以及方法(和结构)能够在无需附图中描述的任何特定方面单独存在和实践。此外，可以任意合适的方式，诸如旋转、溅射、生长和/或沉积技术等形成本文描述的层。
并且，基于阅读和/或理解说明书和附图，对本领域的技术人员来说可发生等同的改变和/或修改。本文的公开包括所有这样的修改和改变并且通常不旨在由这样的修改和改变所限制。例如，尽管示出和描述本文提供的附图以具有特定的掺杂类型，但是应当理解，可以使用本领域的技术人员能够想到的替代掺杂类型。
此外，尽管仅参照若干实施方式中的一个已经公开了特定部件或方面，但是，这种部件或方面可与期望的其他实施方式中的一个或多个其他部件和/或方面结合在一起。而且，在某种程度上，本文使用了术语“包括”、“具有”、“具有”、“带有”和/或派生词，这些术语的意义旨在包含，好比“包括”。并且，“示例性”仅指一个实例，而不是最佳实例。还应当理解，为了简化和容易理解的目的，本文描述的部件、层和/或元件示出有彼此相对的特定尺寸和/或定向，并且还应当理解，实际尺寸和/或定向可大致不同于本文示出的尺寸和/或定向。

Claims (10)

1.一种集成电路(IC)结构，包括：
衬底；
介电层，位于所述衬底的上方；
具有第一密度的第一硬掩模层，位于所述介电层的上方；
具有第二密度的第二硬掩模层，位于所述第一硬掩模层上；以及
开口，延伸穿过所述第一硬掩模层、所述第二硬掩模层和所述介电层；以及
导电材料，填充在所述开口中，
其中，所述第二硬掩模层的所述第二密度小于所述第一硬掩模层的所述第一密度。
2.根据权利要求1所述的集成电路(IC)结构，其中，部件尺寸为50nm或更小。
3.根据权利要求1所述的集成电路(IC)结构，还包括位于所述第二硬掩模层上的具有第三密度的第三硬掩模层，所述第三密度小于所述第一密度和所述第二密度。
4.根据权利要求1所述的集成电路(IC)结构，其中，所述第一密度大于约4.8g/cm3并且所述第二密度小于约4.8g/cm3。
5.根据权利要求1所述的集成电路(IC)结构，其中，所述第二密度和所述第一密度的比小于约0.94。
6.根据权利要求1所述的集成电路(IC)结构，其中，所述第二硬掩模层的第二厚度大于所述第一硬掩模层的第一厚度。
7.根据权利要求1所述的集成电路(IC)结构，其中，所述第一硬掩模层或所述第二硬掩模层是TiN。
8.一种双镶嵌结构，包括：
衬底；
介电层，位于所述衬底的上方；
通孔结构和沟槽结构，位于所述介电层中；
抗反射涂(ARC)层，位于所述介电层的上方；
具有第一密度的第一硬掩模层，位于所述ARC层的上方；
具有第二密度的第二硬掩模层，位于所述第一硬掩模层上；以及
导电层，填充所述通孔和所述沟槽，
其中，所述第二硬掩模层的所述第二密度小于所述第一硬掩模层的所述第一密度。
9.根据权利要求8所述的双镶嵌结构，其中，所述第一密度大于约4.8g/cm3并且所述第二密度小于约4.8g/cm3或者所述第二密度和所述第一密度的比小于约0.94。
10.一种形成鲁棒金属化剖面的方法，包括：
在衬底上方应用第一介电层；
在所述第一介电层上方接连地应用具有第一密度的第一硬掩模层和具有第二密度的第二硬掩模层；
图案化和蚀刻开口穿过所述第二硬掩模、所述第一硬掩模和所述第一介电层；以及
在所述开口中提供导电材料以形成互连结构，其中，所述第一硬掩模层的所述第一密度大于所述第二硬掩模层的所述第二密度。
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