CN104681674A - GaN-based high-voltage direct-current LED insulation isolating process - Google Patents
GaN-based high-voltage direct-current LED insulation isolating process Download PDFInfo
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- 238000009413 insulation Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 67
- 238000002679 ablation Methods 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000010980 sapphire Substances 0.000 claims abstract description 23
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 23
- 238000001312 dry etching Methods 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims description 37
- 238000005516 engineering process Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 239000012535 impurity Substances 0.000 abstract 1
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 238000000608 laser ablation Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Led Devices (AREA)
Abstract
The invention relates to a GaN-based high-voltage direct-current LED insulation isolating process. The process comprises the following steps: a, providing a sapphire substrate on which an epitaxial layer grows, and defining MESA patterns of LED subunits on the epitaxial layer; b, performing dry etching on the epitaxial layer by utilizing the MESA patterns to obtain MESA table boards of the LED subunits; c, depositing etching mask layers, wherein the etching mask layers cover the MESA table boards; d, ablating the epitaxial layer between the MESA table boards of every adjacent two LED subunits and the etching mask layers by utilizing pulse laser spots of a laser so as to form an isolation groove between every adjacent two MESA table boards of the LED subunits, and isolate every adjacent two LED subunits each other through the corresponding isolation groove; e, removing impurities generated by the ablation of the pulse laser spots in each isolation groove so as to smoothen the side wall surface of each isolation groove; f, removing the etching mask layers. According to the process, the insulation isolating performance between adjacent two LED subunits can be effectively improved; the production efficiency is greatly improved; the yield is ensured; the performance of a high-voltage direct-current LED is improved; the process is safe and reliable.
Description
Technical field
The present invention relates to a kind of isolation technology, especially a kind of GaN base high voltage direct current LED insulation isolation technology, belongs to the technical field of high direct voltage LED manufacturing process.
Background technology
The key that LED illumination is popularized is the device architecture developing specular removal, low cost.The integration packaging (COB-LED) occurred in recent years wherein a kind of rich potential device architecture just, COB-LED is connect by many mutual connection in series-parallel of LED be fixed on large area heat-radiating substrate (heat sink) to form.COB-LED significantly can improve heat dissipation problem, uses small current driving to give full play to the specular removal advantage of LED, compares the encapsulation of single LEDs and greatly saves packaging cost.Consider that the COB-LED of current main flow is made up of single LEDs chip, self also has the following disadvantages: 1), each LED needs die bond and routing one by one interconnected, and production efficiency is relatively low, increase equipment cost, affect product yield; 2), LED grain arrangement can not be too compact, is unfavorable for compression encapsulating material cost.For above-mentioned shortcoming, GaN base high voltage direct current LED arises at the historic moment.
Be different from COB-LED integrated in encapsulation procedure, GaN base high voltage direct current LED is made up of multiple LED subelement, the insulation isolation of each unit and electrode is interconnected all completes in chip processing procedure, significantly improves production efficiency and yield; Arrange between each subelement very compact (~ 10-20 μm), can keep the advantage of COB-LED, again can the existing various encapsulation specification of flexible adaptation, reaches the object of cost optimization.
Compare traditional LED, the technique making GaN base high voltage direct current LED is more complicated, and the insulation isolation of LED subelement is its where the shoe pinches.Usual way removes unnecessary epitaxial loayer between subelement with dry etching, although the method can obtain insulation isolation, but consider from the angle of actual production, it is not a kind of desirable method, this is because whole GaN base LED epitaxy layer thickness is general all about 6-10 μm (μ-GaN needing growth thicker is to obtain good growth quality), significantly will certainly increase etch period, need additional deposition SiO
2thick mask, greatly takies ICP and PECVD device production capacity; In addition, it is uncertain to there is certain technique in deep dry etch GaN base epitaxial loayer, and such as sidewall profile is coarse, easily causes interconnecting electrode adhesion failure; Conductive materials may be had in etched trench to remain, cause device photoelectric characteristic abnormal.In order to avoid above-mentioned potential problems generally can relax groove width as far as possible, device is made to lose part light-emitting area, therefore, in the urgent need to developing a kind of brand-new GaN base high voltage direct current LED insulation isolation processing method.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of GaN base high voltage direct current LED insulation isolation technology is provided, it effectively can improve the insulation isolation performance between multiple LED subelement, significantly improving production efficiency, guarantee to produce yield, improve the performance of high voltage direct current LED, safe and reliable.
According to technical scheme provided by the invention, described GaN base high voltage direct current LED insulation isolation technology, described insulation isolation technology comprises the steps:
A, provide growth to have the Sapphire Substrate of epitaxial loayer, and define the MESA figure of LED subelement on said epitaxial layer there;
B, above-mentioned MESA figure is utilized to carry out dry etching to epitaxial loayer, to obtain the MESA table top of LED subelement;
C, on the MESA table top forming LED subelement deposition-etch mask layer, described etching mask layer covers on MESA table top;
D, utilize laser pulsed laser spot ablation LED subelement MESA table top between epitaxial loayer and etching mask layer, to form isolated groove between the MESA table top of LED subelement, with by isolated groove by mutually isolated for LED subelement;
By foreign material after pulsed laser spot ablation in e, removal isolated groove, with the sidewall surfaces of level and smooth isolated groove;
F, remove above-mentioned etching mask layer.
Described epitaxial loayer comprises the μ-GaN layer be grown in Sapphire Substrate, the N-GaN layer grown in described μ-GaN layer, grow Multiple Quantum Well on described N-GaN layer and the P-GaN layer of growth in described Multiple Quantum Well.
The MESA table top forming isolated groove arranges ito transparent electrode, P type metal electrode and passivation layer, ito transparent electrode covers on P-GaN layer, passivation layer covers on ito transparent electrode, and surround the outer wall of epitaxial loayer, P type metal electrode is electrically connected with ito transparent electrode through passivation layer, and N-type metal electrode is through passivation layer and N-GaN layer ohmic contact; In Sapphire Substrate, adjacent LED subelement is connected by series connection metal electrode, series connection metal electrode is filled in isolated groove, one end of series connection metal electrode is electrically connected with the N-type metal electrode of a LED subelement, the series connection other end of metal electrode is electrically connected with the P type metal electrode of another LED subelement, and series connection metal electrode is insulated by passivation layer and epitaxial loayer and isolates.
In described step a, epitaxial loayer arranges graphic mask layer, and the etching window of through graphic mask layer is set on described graphic mask layer, utilize etching window and graphic mask layer to define the MESA figure of LED subelement.
Described graphic mask layer comprises photoresist mask.
In described step b, dry etching is ICP etching or RIE etching, dry etching epitaxial loayer obtains etching groove, and described etching groove extends downward in N-GaN layer from P-GaN layer, in Sapphire Substrate LED subelement MESA table top between by etching groove mutually isolated.
Described etching mask layer is the silicon dioxide layer through PECVD deposition, and the thickness of described etching mask layer is 150nm ~ 200nm.
In described steps d, the wavelength of the pulsed laser spot of laser is 266nm or 355nm.
The present invention has following advantage:
1, dry etching is only for making the N-type electrode table top of MESA table top, substantially identical with the MESA etch process of conventional LED, can not obviously take Dry etching equipment (ICP, RIE) production capacity.
2, do not need significantly to take PECVD production capacity, the etching mask layer that additional deposition is thicker, only need can remove with hot acidizing after deposition-etch mask layer.
3, laser ablation forms isolated groove, rapidly and efficiently, is easy to control; And zanjon width is narrower, is conducive to reducing the loss of device light-emitting area, reduces injected current density.
4, the isolated groove that formed of hot acidizing laser ablation, can remove residual ablation foreign material and damage epitaxial loayer completely, ensure that zanjon exists without leak channel, simultaneously can smooth trench sidewall surfaces, is conducive to reducing the interconnected failure probability of electrode.
Accompanying drawing explanation
Fig. 1 is the structure that the present invention obtains GaN high voltage direct current LED.
Fig. 2 is the schematic diagram that laser facula of the present invention carries out ablation.
Fig. 3 ~ Figure 10 is the concrete implementation step cutaway view that the present invention carries out insulation isolation technology, wherein
Fig. 3 is the cutaway view of the present invention on a sapphire substrate after grown epitaxial layer.
Fig. 4 is the cutaway view that the present invention obtains defining after the MESA figure of LED subelement.
Fig. 5 is the cutaway view after the present invention obtains etching groove.
Fig. 6 is the cutaway view after the present invention obtains etching mask layer.
Fig. 7 is that the present invention is by the cutaway view after laser facula ablation.
Fig. 8 is that after the present invention removes ablation, foreign material obtain the cutaway view after damaging epitaxial loayer.
Fig. 9 is the cutaway view after the present invention removes damage epitaxial loayer.
Figure 10 is the cutaway view after the present invention obtains isolated groove.
Figure 11 is the schematic diagram of the present invention when carrying out Laser Focusing ablation.
Figure 12 is the schematic diagram after the present invention carries out the ablation of laser defocusing.
Description of reference numerals: 1-P-GaN layer, 2-Multiple Quantum Well, 3-N-GaN layer, 4-μ-GaN layer, 5-Sapphire Substrate, 6-P type metal electrode, 7-passivation layer, 8-ITO transparency electrode, 9-N type metal electrode, 10-series connection metal electrode, 11-LED subelement, 12-ablation foreign material, 13-damage epitaxial loayer, 14-graphic mask layer, 15-etching window, 16-etching groove, 17-etching mask layer, 18-isolated groove, 19-N electrode table top and 20-epitaxial loayer.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
In order to effectively improve the insulation isolation performance between multiple LED subelement, significantly improving production efficiency, guarantee to produce yield, improve the performance of high voltage direct current LED, the present invention's isolation technology that insulate comprises the steps:
A, provide growth to have the Sapphire Substrate 5 of epitaxial loayer 20, and on described epitaxial loayer 20, define the MESA figure of LED subelement 11;
As shown in Figure 3 and Figure 4, described epitaxial loayer 20 comprises the μ-GaN layer 4 be grown in Sapphire Substrate 5, the N-GaN layer 3 grown in described μ-GaN layer 4, grows Multiple Quantum Well 2 on described N-GaN layer 3 and the P-GaN layer 1 of growth in described Multiple Quantum Well 2.
In order to define the MESA figure of LED subelement 11 on epitaxial loayer 20, epitaxial loayer 20 arranges graphic mask layer 14, described graphic mask layer 14 comprises photoresist mask.Described graphic mask layer 14 is arranged the etching window 15 of through graphic mask layer 14, utilize etching window 15 and graphic mask layer 14 to define the MESA figure of LED subelement 11, i.e. spin coating photoresist on epitaxial loayer 20, according to Sapphire Substrate 5 needing the position forming LED subelement 11, etching window 15 is set, the through graphic mask layer 14 of etching window 15, can by the surface exposure of epitaxial loayer 20 to pass through etching window 15.
B, above-mentioned MESA figure is utilized to carry out dry etching to epitaxial loayer 20, to obtain the MESA table top of LED subelement 11;
As shown in Figure 5, dry etching is ICP(Inductively Coupled Plasma) etch or RIE(reactive ion etching) etching, dry etching epitaxial loayer 20 obtains etching groove 16, described etching groove 16 extends downward in N-GaN layer 3 from P-GaN layer 1, in Sapphire Substrate 5 LED subelement 11 MESA table top between by etching groove 16 mutually isolated.In the embodiment of the present invention, epitaxial loayer 20 exposed for etching window 15 is passed through dry etching, to obtain etching groove 16 at the regional location of etching window 15, the N-GaN layer 3 of the through P-GaN layer 1 of etching groove 16, Multiple Quantum Well 2 and part, photoresist is utilized to obtain etching groove 16 for mask carries out etching, with the technological means that the MESA table top obtaining LED subelement 11 is commonly used for the art, graphic mask layer 14 is removed after obtaining etching groove 16, to carry out follow-up processing step, specifically repeat no more.
C, on the MESA table top forming LED subelement 11 deposition-etch mask layer 17, described etching mask layer 17 covers on MESA table top;
As shown in Figure 6, described etching mask layer 17 is through PECVD(Plasma Enhanced Chemical Vapor Deposition) silicon dioxide layer that deposits, the thickness of described etching mask layer 17 is 150nm ~ 200nm.The etching mask layer 17 of deposition can be filled in etching groove 16.
D, utilize laser pulsed laser spot ablation LED subelement 11MESA table top between epitaxial loayer 20 and etching mask layer 17, to form isolated groove 18 between the MESA table top of LED subelement 11, to pass through isolated groove 18 by mutually isolated for LED subelement 11;
As shown in Fig. 7, Figure 11 and Figure 12, laser can be solid-state nanosecond laser, and the wavelength of the pulsed laser spot of laser is 266nm or 355nm.For the pulsed laser spot adopting wavelength to be 355nm, by pulsed laser spot ablation epitaxial loayer 20 and etching mask layer 17, until by epitaxial loayer 20 ablation to Sapphire Substrate 5, defocusing amount, pulse energy, pulse frequency and translational speed remain on respectively-450 μm, 23 μ J, 5kHz, 25 μm/s.Laser processing is as a kind of emerging rapid mass process technology, and the GaN base material and Sapphire Substrate 5 of processing difficulties obtain good result, and oneself has been widely applied in the manufacture craft of GaN base LED component.As shown in figure 11, in the in-focus situation, focusing laser energy is in sample surfaces, and hot spot is enough to ablation and wears epitaxial loayer 20 and Sapphire Substrate 5.This is that conventional LED wafer splits the laser processing pattern adopted, and usually wishes the Sapphire Substrate 5 of ablation certain depth.In defocusing situation, laser is loose large at sample surfaces hot spot, thus reduces laser energy density, simultaneously in conjunction with the careful adjustment of other parameters, can realize the selectivity ablation to extension 20 layers, and not injure Sapphire Substrate 5.During concrete enforcement, the operating state of laser is controlled, ablation is carried out to etching mask layer 17 and epitaxial loayer 20 and the detailed process that do not injure Sapphire Substrate 5 is different and different according to the running parameter of various lasers, specifically be chosen as known by the art personnel, repeat no more herein.
By foreign material after pulsed laser spot ablation in e, removal isolated groove 18, with the sidewall surfaces of level and smooth isolated groove 18;
As shown in Figure 7 and Figure 8, when utilizing pulsed laser spot to carry out ablation to etching mask layer 17 and epitaxial loayer 20, ablation foreign material 12 and damage epitaxial loayer 13 will certainly be produced, due to pulsed laser spot etching mask layer 17 and epitaxial loayer 20 etched logical after, isolated groove 18 can be obtained in Sapphire Substrate 5, ablation foreign material 12 are attached on damage epitaxial loayer 13, in order to ensure the stable performance between LED subelement 11, ablation foreign material 12 and damage epitaxial loayer 13 are needed to remove, obtain the sidewall of level and smooth isolated groove 18, as shown in Figure 9.
In the embodiment of the present invention, pulsed laser spot acts on epitaxial loayer 20 and causes GaN material pyrolysis, produces ablation foreign material 12 simultaneously, such as metal residual and the metal oxide of amorphous formed in air ambient and metal nitride etc.The detailed process removing ablation foreign material 12 and damage epitaxial loayer 13 is: wafer after laser ablation being put into temperature is 200 DEG C, volume ratio H
3pO
4: H
2sO
4etch 10mins in the mixed acid solution of=1:3 and remove laser ablation accessory substance and damage epitaxial loayer, wherein H
2sO
4, H
3pO
4the concentration of solution is respectively 98%, 85%.The etch-rate of etching mask layer 17 in mixed acid solution is very low, is enough to protect the epitaxial loayer 20 covered under it.Hot acid etching can remove above-mentioned product completely, and eliminating electric leakage may.In addition, it is uneven that ablation forms isolated groove 18 surface topography, and the epitaxial film materials near its sidewall surfaces exists damage, and hot acid solution also can be utilized to carry out selective etch to damaged material, smooth trench sidewall, reduces surface leakage.
F, remove above-mentioned etching mask layer 17.
As shown in Figure 10, because etching mask layer 17 is silicon dioxide layer, utilize HF solution or BOE solution to be removed by etching mask layer 17, utilize the method for HF solution and BOE solution removal etching mask layer 17 and process to be known by the art personnel, repeat no more herein.
In order to complete LED subelement 11 will be formed, also need after completing insulation isolation technology, the operation such as electrode and interconnection is set again, the mode that the detailed process arranging electrode and interconnection can adopt the art conventional, detailed process is known by the art personnel, and the structure of the GaN high voltage direct current LED formed as shown in Figure 1.
As shown in Figure 1, the MESA table top forming isolated groove 18 arranges ito transparent electrode 8, P type metal electrode 6, N-type metal electrode 8 and passivation layer 7, ito transparent electrode 8 covers on P-GaN layer 1, passivation layer 7 covers on P-GaN layer 1, and surround the outer wall of epitaxial loayer 20, P type metal electrode 6 is electrically connected with ito transparent electrode 8 through passivation layer 7, and N-type metal electrode 9 is through passivation layer 7 and N-GaN layer 3 ohmic contact; In Sapphire Substrate 5, adjacent LED subelement 11 is connected by series connection metal electrode 10, series connection metal electrode 10 is filled in isolated groove 18, one end of series connection metal electrode 10 is electrically connected with the N-type metal electrode 9 of a LED subelement 11, the series connection other end of metal electrode 10 is electrically connected with the P type metal electrode 6 of another LED subelement 11, and series connection metal electrode 10 is insulated by passivation layer 7 and epitaxial loayer 20 and isolates.N-type metal electrode 9 is supported on N electrode table top 19, and N electrode table top 19 is the surface of N-GaN layer 3.
Dry etching of the present invention is only for making the N-type electrode table top 19 of MESA table top, substantially identical with the MESA etch process of conventional LED, can not obviously take Dry etching equipment (ICP, RIE) production capacity.Do not need significantly to take PECVD production capacity, the etching mask layer 17 that additional deposition is thicker, only need can remove with hot acidizing after deposition-etch mask layer 17.Laser ablation forms isolated groove 18, rapidly and efficiently, is easy to control; And zanjon width is narrower, is conducive to reducing the loss of device light-emitting area, reduces injected current density.The isolated groove 18 that hot acidizing laser ablation is formed, can remove residual ablation foreign material 12 and damage epitaxial loayer 13 completely, ensure that zanjon exists without leak channel, simultaneously can smooth trench sidewall surfaces, is conducive to reducing the interconnected failure probability of electrode.
Claims (8)
1. a GaN base high voltage direct current LED insulation isolation technology, it is characterized in that, described insulation isolation technology comprises the steps:
(a), the Sapphire Substrate (5) providing growth to have epitaxial loayer (20), and at the upper MESA figure defining LED subelement (11) of described epitaxial loayer (20);
(b), utilize above-mentioned MESA figure to carry out dry etching to epitaxial loayer (20), to obtain the MESA table top of LED subelement (11);
(c), formed LED subelement (11) MESA table top on deposition-etch mask layer (17), described etching mask layer (17) covers on MESA table top;
(d), utilize laser pulsed laser spot ablation LED subelement (11) MESA table top between epitaxial loayer (20) and etching mask layer (17), to form isolated groove (18) between the MESA table top of LED subelement (11), to pass through isolated groove (18) by mutually isolated for LED subelement (11);
By foreign material after pulsed laser spot ablation in (e), removal isolated groove (18), with the sidewall surfaces of level and smooth isolated groove (18);
(f), remove above-mentioned etching mask layer (17).
2. GaN base high voltage direct current LED according to claim 1 insulate isolation technology, it is characterized in that: described epitaxial loayer (20) comprises the μ-GaN layer (4) be grown in Sapphire Substrate (5), the N-GaN layer (3) grown on described μ-GaN layer (4), grow Multiple Quantum Well (2) on described N-GaN layer (3) and the P-GaN layer (1) of growth in described Multiple Quantum Well (2).
3. GaN base high voltage direct current LED insulation isolation technology according to claim 2, it is characterized in that: on the MESA table top forming isolated groove (18), ito transparent electrode (8) is set, P type metal electrode (6) and passivation layer (7), ito transparent electrode (8) covers on P-GaN layer (1), passivation layer (7) covers on ito transparent electrode (8), and surround the outer wall of epitaxial loayer (20), P type metal electrode (6) is electrically connected with ito transparent electrode (8) through passivation layer (7), N-type metal electrode (9) is through passivation layer (7) and N-GaN layer (3) ohmic contact, the upper adjacent LED subelement (11) of Sapphire Substrate (5) is connected by series connection metal electrode (10), series connection metal electrode (10) is filled in isolated groove (18), one end of series connection metal electrode (10) is electrically connected with the N-type metal electrode (9) of a LED subelement (11), the other end of series connection metal electrode (10) is electrically connected with the P type metal electrode (6) of another LED subelement (11), and series connection metal electrode (10) is insulated by passivation layer (7) and epitaxial loayer (20) and isolated.
4. GaN base high voltage direct current LED insulation isolation technology according to claim 1, it is characterized in that: in described step (a), epitaxial loayer (20) arranges graphic mask layer (14), and the etching window (15) of through graphic mask layer (14) is set on described graphic mask layer (14), utilize etching window (15) and graphic mask layer (14) to define the MESA figure of LED subelement (11).
5. GaN base high voltage direct current LED insulation isolation technology according to claim 4, is characterized in that: described graphic mask layer (14) comprises photoresist mask.
6. GaN base high voltage direct current LED insulation isolation technology according to claim 2, it is characterized in that: in described step (b), dry etching is ICP etching or RIE etching, dry etching epitaxial loayer (20) obtains etching groove (16), described etching groove (16) extends downward in N-GaN layer (3) from P-GaN layer (1), mutually isolated by etching groove (16) between the MESA table top of the upper LED subelement (11) of Sapphire Substrate (5).
7. GaN base high voltage direct current LED insulation isolation technology according to claim 1, is characterized in that: described etching mask layer (17) is the silicon dioxide layer through PECVD deposition, and the thickness of described etching mask layer (17) is 150nm ~ 200nm.
8. GaN base high voltage direct current LED insulation isolation technology according to claim 1, it is characterized in that: in described step (d), the wavelength of the pulsed laser spot of laser is 266nm or 355nm.
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