WO2020062379A1 - Floating p-n junction quantum well-based series array energy system and preparation method - Google Patents

Floating p-n junction quantum well-based series array energy system and preparation method Download PDF

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WO2020062379A1
WO2020062379A1 PCT/CN2018/111788 CN2018111788W WO2020062379A1 WO 2020062379 A1 WO2020062379 A1 WO 2020062379A1 CN 2018111788 W CN2018111788 W CN 2018111788W WO 2020062379 A1 WO2020062379 A1 WO 2020062379A1
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gan
electrode
quantum well
junction quantum
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王永进
吴凡
高绪敏
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南京邮电大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035236—Superlattices; Multiple quantum well structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
    • H01L31/1848—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P comprising nitride compounds, e.g. InGaN, InGaAlN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1852—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising a growth substrate not being an AIIIBV compound
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention belongs to the field of information materials and devices, and relates to a suspended p-n junction quantum well-based series array energy system and a preparation method thereof.
  • LED is a light-emitting diode, which is an electronic device that converts electrical energy into light energy.
  • Photodetectors which are photodiodes, can convert light signals into electrical signals. The core part of both is a PN junction.
  • Nitride materials especially GaN materials, have a wide direct band gap, strong atomic bonds, high thermal conductivity, and good chemical stability. They are an ideal short-wavelength light-emitting device material.
  • Optical waveguide devices with large refractive index differences from air can achieve high light field confinement; silicon substrates are removed to reduce absorption losses, and the luminous intensity of suspended pn junction quantum well devices is enhanced, whether used as LED light sources or photodetectors, Performance will be further improved. Therefore, it is possible to develop a monolithic highly integrated planar photonic integrated system based on silicon substrate nitride materials, laying a foundation for the development of nitride photons and optical micro-electromechanical devices for optical communication and light sensing.
  • the present invention provides a suspended p-n junction quantum well-based tandem array energy system that realizes micro-level device series, which can greatly improve energy conversion efficiency and achieve energy self-sufficiency.
  • the invention also provides a method for preparing the system.
  • the suspended pn junction quantum well-based tandem array energy system of the present invention uses a silicon-based nitride wafer as a carrier, and includes a silicon substrate layer, an epitaxial buffer layer provided on the silicon substrate layer, and the epitaxial buffer.
  • a groove etched to the u-GaN layer is provided therebetween, and the n-electrode of the pn junction quantum well device and the p-electrode of the adjacent pn junction quantum well device are connected by a metal layer, and a metal layer is provided below A SiO 2 layer that isolates it from an InGaN / GaN quantum well, an n-GaN layer, a u-GaN layer, and a p-GaN layer.
  • a plurality of p-n junction quantum well devices are connected in series through a metal layer.
  • the p-electrode and n-electrode are both Ni / Au electrodes, that is, the deposited metal material is Ni / Au.
  • the n-GaN lower mesa and the u-GaN layer groove are generated.
  • the p-GaN layer, quantum well, and n-GaN layer of the device are separated.
  • a part of the n-GaN layer, the u-GaN layer, and the p-GaN layer is covered with a layer of SiO 2 as an isolation layer.
  • the method for preparing the above-mentioned suspended p-n junction quantum well-based tandem array energy system includes the following steps:
  • Step (1) thinning and polishing the silicon substrate layer behind the silicon-based nitride wafer
  • Step (2) uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and using photolithography alignment technology to define a required first n-GaN pattern area on the photoresist layer;
  • Step (3) etching the first n-GaN pattern region; removing the residual photoresist to obtain a stepped mesa, an InGaN / GaN quantum well layer and a p-GaN layer of the p-n junction quantum well device located on the upper mesa;
  • Step (4) uniformly coat a layer of photoresist on the upper surface of the silicon-based nitride wafer, and use photo-alignment technology to define the p-electrode window area on the p-GaN layer and the n-electrode window area;
  • Step (5) depositing a layer of Ni / Au on the p-electrode window area and the n-electrode window area respectively to form an ohmic contact to realize the p-electrode and the n-electrode. After removing the residual photoresist, pn is obtained.
  • Junction quantum well device
  • Step (6) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and a second n-GaN pattern area is defined on the photoresist layer by using a photolithography alignment technique.
  • the second n- The GaN pattern region is located in the first n-GaN pattern region, between the n-electrode and the p-electrode of an adjacent pn junction quantum well device;
  • Step (7) etching the second n-GaN pattern region; removing the residual photoresist, and forming a recessed region between the p-electrode and the n-electrode on the n-GaN layer;
  • Step (8) uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and defining a u-GaN layer pattern region in the recessed region on the photoresist layer by using a photolithography alignment technique;
  • Step (9) Etching the n-GaN layer to the u-GaN layer, removing the residual photoresist, and obtaining a groove and a u-GaN layer located under the groove;
  • Step (10) deposit a continuous SiO 2 layer on the upper surface of the silicon-based nitride wafer
  • Step (11) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the first n-GaN pattern region and the second n-GaN pattern region on the n-electrode layer are aligned by using a photolithography alignment technique. , U-GaN layer pattern region and p-electrode region p-GaN layer pattern region;
  • Step (12) use BOE solution to wet etch away excess SiO 2 ;
  • Step (13) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the n-electrode window region, the first n-GaN pattern region, and the second n-GaN pattern region are aligned using a photolithography alignment technique. , U-GaN layer pattern area, p-electrode window pattern area;
  • Step (14) A continuous layer of Ni is deposited on the n-electrode window region, the first n-GaN layer pattern region, the second n-GaN layer pattern region, the u-GaN layer pattern region, and the p-electrode window region. / Au to connect the p-electrode and the n-electrode;
  • the epitaxial buffer layer is used as an etching barrier layer.
  • the deep silicon etching technology behind the substrate is used to etch the substrate through the back etching window.
  • the silicon substrate layer is etched through to the lower surface of the epitaxial buffer layer to form a cavity;
  • Step (16) After removing the residual photoresist, an integrated array of suspended p-n junction quantum well devices and serial devices is obtained, the p-electrode and the n-electrode are connected, and the devices are connected in series.
  • the vapor deposition Ni / Au in steps (5) and (14) adopts a stripping process and a temperature controlled at 5005 ° C. Nitrogen annealing technology.
  • the etching in steps (3), (7), and (9) is ion beam bombardment or reactive ion beam etching. Eclipse technology.
  • a layer of SiO 2 is deposited using a plasma enhanced chemical vapor deposition method.
  • each device in the steps (3) and (7), is isolated by etching to a u-GaN layer multiple times, and In the step (10) and the step (14), successively deposited SiO 2 layers and metal layers connect the n-electrode and p-electrode of each device in series.
  • multiple devices are integrated on the same chip in the form of a series array, and electrodes are connected in series inside the chip, so that micro-level devices can be connected in series.
  • a suspended p-n junction quantum well device as a photodetector can convert light energy into electrical energy as a kind of renewable energy, and the device in series can greatly improve energy conversion efficiency.
  • the floating p-n junction quantum well device is used as the LED light source, and the converted energy is supplied to light itself to achieve self-sufficiency of energy.
  • the present invention has the following advantages:
  • the suspended p-n junction quantum well-based tandem array energy system and the preparation method of the invention can realize various functions:
  • a series of micro-level devices are realized. Multiple devices are integrated in the same chip in series to realize the array arrangement of devices.
  • the integrated system chip can convert light energy into electrical energy, which can be used as a large-scale production of renewable new energy to solve the problem of energy regeneration;
  • This integrated system chip can run under severe conditions such as high temperature, which can solve the problem of energy regeneration under severe conditions.
  • FIG. 1 is a schematic structural diagram of an energy system of a suspended p-n junction quantum well-based series array of a silicon substrate according to the present invention.
  • FIG. 2 is a top view of a p-n junction quantum well-based tandem array energy system of a silicon substrate of the present invention.
  • FIG. 3 is a process flow chart of a p-n junction quantum well-based tandem array energy system of a silicon substrate of the present invention.
  • FIG. 1 is a schematic diagram showing a structure of an energy system of a quantum well-based tandem array of a suspended pn junction of a silicon substrate of the present invention.
  • FIG. 2 shows a top view of a pn junction quantum well-based tandem array energy system of a silicon substrate according to the present invention.
  • the n-electrode 7, n-GaN layer 4, u-GaN layer 3, and p-electrode 9 are covered with a A metal layer 10 connects the n-electrode 7 of the previous device and the p-electrode 9 of the next device in series.
  • the integrated system uses a silicon-based nitride wafer as a carrier, and includes a silicon substrate layer 1, an epitaxial buffer layer provided on the silicon substrate layer 1, a u-GaN layer 3 provided on the epitaxial buffer layer 2, and a set A plurality of pn-junction quantum well devices on the u-GaN layer 3, the pn-junction quantum well device including an n-GaN layer 4 provided with a stepped mesa, and the upper mesa of the stepped mesa is arranged in order from bottom to top InGaN / GaN quantum well layer 5, p-GaN layer 8, and p-electrode 9, and an n-electrode 7 disposed on the lower mesa of the stepped mesa are disposed between two adjacent pn junction quantum well devices There is a groove etched into the u-GaN layer 3, the n-electrode 7 of the pn junction quantum well device and the p-electrode 9 of its
  • FIG. 3 shows a flow of a method for preparing a silicon substrate suspended p-n junction quantum well-based tandem array energy system according to the present invention.
  • An embodiment of the method of the present invention includes the following steps:
  • Step (1) thinning and polishing the silicon substrate layer 1 behind the silicon-based nitride wafer;
  • Step (2) uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and defining a first n-GaN pattern region on the photoresist layer by using a photolithography alignment technique;
  • Step (3) The first n-GaN pattern region is etched by using a reactive ion beam; the residual photoresist is removed to obtain a stepped mesa, an InGaN / GaN quantum well layer 5 and a p-GaN on the upper mesa pn junction quantum well device.
  • Step (4) uniformly coat a layer of photoresist on the upper surface of the silicon-based nitride wafer, and use photo-alignment technology to define two p-electrode window regions of the pn junction quantum well device on the p-GaN layer 8, An n-electrode window region located on the lower mesa of the n-GaN layer 4, wherein two p-electrode window regions are located on both sides of the first n-GaN pattern region;
  • Step (5) vapor-deposit a layer of Ni / Au in the p-electrode window area and the n-electrode window area to form an ohmic contact, and realize the p-electrode 9 and the n-electrode 7, after removing the residual photoresist, that is, Obtaining a pn junction quantum well device;
  • Step (6) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and a second n-GaN pattern area is defined on the photoresist layer by using a photolithography alignment technique.
  • the second n- The GaN pattern region is located in the first n-GaN pattern region, between the n-electrode 7 and the p-electrode 9 of the next pn junction quantum well device;
  • step (7) the second n-GaN pattern region is etched by using a reactive ion beam; the remaining photoresist is removed, and a recessed region between the p-electrode 9 and the n-electrode 7 is formed on the n-GaN layer 4;
  • Step (8) uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and defining a u-GaN layer pattern region in the recessed region on the photoresist layer by using a photolithography alignment technique;
  • Step (9) Etching the n-GaN layer 4 to the u-GaN layer 3 by using a reactive ion beam; removing the residual photoresist to obtain a groove and a u-GaN layer located under the groove;
  • Step (10) deposit a continuous SiO 2 layer 6 on the upper surface of the silicon-based nitride wafer
  • Step (11) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the first n-GaN pattern region and the second n-GaN pattern region on the n-electrode layer are aligned by using a photolithography alignment technique. , U-GaN layer pattern region and p-GaN layer region of p-electrode region;
  • Step (12) use BOE solution to wet etch away excess SiO 2 ;
  • Step (13) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the n-electrode window region, the first n-GaN pattern region, and the second n-GaN pattern region are aligned using a photolithography alignment technique. , U-GaN layer pattern area, p-electrode window area;
  • Step (14) A continuous layer of Ni / Au is deposited on the n-electrode window region, the first n-GaN pattern region, the second n-GaN pattern region, the u-GaN layer pattern region, and the p-electrode window region. Layer to connect the p-electrode 9 and the n-electrode 7;
  • the silicon substrate layer 1 is etched through to the lower surface of the epitaxial buffer layer 2 to form a cavity;
  • Step (16) After removing the residual photoresist, an integrated array of suspended p-n junction quantum well devices and serial devices is obtained, the p-electrode and the n-electrode are connected, and the devices are connected in series.

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Abstract

A floating p-n junction quantum well-based series array energy system and a preparation method. A system implementation carrier is a silicon-based nitride wafer, and a silicon substrate layer (1) under a device structure is stripped off and removed by using the back deep silicon etching technology to obtain floating p-n junction quantum well devices; a SiO2 layer (6) is used as an isolation layer, and multiple devices are integrated in a series array form. According to the system, multiple devices are integrated on the same chip in a series array form, electrodes are connected in series by means of vapor plating of a metal layer (10) inside the chip, and the devices can be connected in series in the microscopic level. The floating p-n junction quantum well device is taken as a photo detector, where light energy can be converted into electric energy and is taken as one kind of renewable energy, and the form of connecting the devices in series can greatly improve the energy conversion rate. The floating p-n junction quantum well device can be taken as an LED light source, and converted energy is supplied for self-lightening, thereby achieving self-sufficiency of energy.

Description

悬空p-n结量子阱基串联阵列能量系统及制备方法Suspended P-N junction quantum well-based series array energy system and preparation method 技术领域Technical field
本发明属于信息材料与器件领域，涉及一种悬空p-n结量子阱基串联阵列能量系统及制备方法。The invention belongs to the field of information materials and devices, and relates to a suspended p-n junction quantum well-based series array energy system and a preparation method thereof.
背景技术Background technique
LED即发光二极管，是一种将电能转化为光能的电子器件；光电探测器即光电二极管，能够把光信号转化为电信号；二者核心部分均为PN结。LED is a light-emitting diode, which is an electronic device that converts electrical energy into light energy. Photodetectors, which are photodiodes, can convert light signals into electrical signals. The core part of both is a PN junction.
氮化物材料特别是GaN材料，具有宽的直接带隙、强的原子键、高的热导率、化学稳定性好，是一种理想的短波长发光器件材料。生长在高阻硅衬底上的氮化物材料，利用深硅刻蚀技术能够解决硅衬底与氮化物材料的剥离问题，实现悬空直至超薄的厚度可控的氮化物薄膜器件；利用氮化物与空气较大的折射率差异，可以实现高光场限制作用的光波导器件；去除硅衬底，降低吸收损耗，悬空p-n结量子阱器件的发光强度增强，不论是作为LED光源还是光电探测器，性能将进一步提升。因此，基于硅衬底氮化物材料发展单片高度集成的平面光子集成系统成为一种可能，为发展面向光通信、光传感的氮化物光子及光学微机电器件奠定了基础。Nitride materials, especially GaN materials, have a wide direct band gap, strong atomic bonds, high thermal conductivity, and good chemical stability. They are an ideal short-wavelength light-emitting device material. The nitride material growing on the high-resistance silicon substrate. The use of deep silicon etching technology can solve the problem of the separation between the silicon substrate and the nitride material, and achieve a controllable thickness of the nitride thin film device that is suspended to an ultra-thin thickness. Optical waveguide devices with large refractive index differences from air can achieve high light field confinement; silicon substrates are removed to reduce absorption losses, and the luminous intensity of suspended pn junction quantum well devices is enhanced, whether used as LED light sources or photodetectors, Performance will be further improved. Therefore, it is possible to develop a monolithic highly integrated planar photonic integrated system based on silicon substrate nitride materials, laying a foundation for the development of nitride photons and optical micro-electromechanical devices for optical communication and light sensing.
发明内容Summary of the Invention
技术问题：本发明提供了一种实现微观级别的器件串联，可大大提高能量转换效率，实现能源自给自足的悬空p-n结量子阱基串联阵列能量系统。本发明同时提供了一种制备该系统的方法。Technical problem: The present invention provides a suspended p-n junction quantum well-based tandem array energy system that realizes micro-level device series, which can greatly improve energy conversion efficiency and achieve energy self-sufficiency. The invention also provides a method for preparing the system.
技术方案：本发明的悬空p-n结量子阱基串联阵列能量系统，以硅基氮化物晶片为载体，包括硅衬底层、设置在所述硅衬底层上的外延缓冲层、设置在所述外延缓冲层上的u-GaN层、设置在u-GaN层上的多个p-n结量子阱器件，所述p-n结量子阱器件包括设置有阶梯状台面的n-GaN层、在所述阶梯状台面的上台面从下至上依次设置的InGaN/GaN量子阱层、p-GaN层和p-电极、设置在所述阶梯状台面的下台面上的n-电极，在两相邻的p-n结量子阱器件之间设置有刻蚀至u-GaN层的凹槽，p-n结量子阱器件的n-电极与其相邻p-n结量子阱器件的p-电极之间通过金属层连接，所述金属层下设置有将其与InGaN/GaN量子阱、n-GaN层、u-GaN层、p-GaN层隔离的SiO 2层。 Technical solution: The suspended pn junction quantum well-based tandem array energy system of the present invention uses a silicon-based nitride wafer as a carrier, and includes a silicon substrate layer, an epitaxial buffer layer provided on the silicon substrate layer, and the epitaxial buffer. A u-GaN layer on the layer, and a plurality of pn-junction quantum well devices disposed on the u-GaN layer, the pn-junction quantum well device including an n-GaN layer provided with a stepped mesa, An InGaN / GaN quantum well layer, a p-GaN layer, and a p-electrode, an n-electrode provided on the lower mesa of the stepped mesa, and two adjacent pn-junction quantum well devices are sequentially arranged on the upper mesa from bottom to top. A groove etched to the u-GaN layer is provided therebetween, and the n-electrode of the pn junction quantum well device and the p-electrode of the adjacent pn junction quantum well device are connected by a metal layer, and a metal layer is provided below A SiO 2 layer that isolates it from an InGaN / GaN quantum well, an n-GaN layer, a u-GaN layer, and a p-GaN layer.
进一步的，本发明的悬空p-n结量子阱基串联阵列能量系统中，多个p-n结量子阱器件通过金属层以串联形式相连。Further, in the floating p-n junction quantum well-based tandem array energy system of the present invention, a plurality of p-n junction quantum well devices are connected in series through a metal layer.
进一步的，本发明的悬空p-n结量子阱基串联阵列能量系统中，所述p-电极和n-电极均为Ni/Au电极，即沉积的金属材料为Ni/Au。Further, in the suspended p-n junction quantum well-based tandem array energy system of the present invention, the p-electrode and n-electrode are both Ni / Au electrodes, that is, the deposited metal material is Ni / Au.
进一步的，本发明的悬空p-n结量子阱基串联阵列能量系统中，经过两次反应离子束刻蚀到u-GaN层，生成的n-GaN下台面、u-GaN层凹槽，将两个器件的p-GaN层、量子阱、n-GaN层隔开。Further, in the suspended pn-junction quantum well-based tandem array energy system of the present invention, after the reactive ion beam is etched into the u-GaN layer twice, the n-GaN lower mesa and the u-GaN layer groove are generated. The p-GaN layer, quantum well, and n-GaN layer of the device are separated.
进一步的，本发明的悬空p-n结量子阱基串联阵列能量系统中，在n-GaN层、u-GaN层和p-GaN层的一部分上覆盖一层SiO 2层，作为隔离层。 Further, in the suspended pn junction quantum well-based tandem array energy system of the present invention, a part of the n-GaN layer, the u-GaN layer, and the p-GaN layer is covered with a layer of SiO 2 as an isolation layer.
本发明的制备上述的悬空p-n结量子阱基串联阵列能量系统的制备方法，包括以下步骤：The method for preparing the above-mentioned suspended p-n junction quantum well-based tandem array energy system includes the following steps:
步骤(1)在硅基氮化物晶片背后对硅衬底层进行减薄抛光；Step (1) thinning and polishing the silicon substrate layer behind the silicon-based nitride wafer;
步骤(2)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出所需的第一n-GaN图形区域；Step (2) uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and using photolithography alignment technology to define a required first n-GaN pattern area on the photoresist layer;
步骤(3)刻蚀第一n-GaN图形区域；去除残余光刻胶，得到阶梯状台面、位于上台面的p-n结量子阱器件的InGaN/GaN量子阱层和p-GaN层；Step (3) etching the first n-GaN pattern region; removing the residual photoresist to obtain a stepped mesa, an InGaN / GaN quantum well layer and a p-GaN layer of the p-n junction quantum well device located on the upper mesa;
步骤(4)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术定义出位于p-GaN层上的p-电极窗口区域、位于n-GaN层下台面的n-电极窗口区域；Step (4) uniformly coat a layer of photoresist on the upper surface of the silicon-based nitride wafer, and use photo-alignment technology to define the p-electrode window area on the p-GaN layer and the n-electrode window area;
步骤(5)在所述p-电极窗口区域与n-电极窗口区域分别蒸镀一层Ni/Au，形成欧姆接触，实现p-电极与n-电极，去除残余光刻胶后，即得到p-n结量子阱器件；Step (5) depositing a layer of Ni / Au on the p-electrode window area and the n-electrode window area respectively to form an ohmic contact to realize the p-electrode and the n-electrode. After removing the residual photoresist, pn is obtained. Junction quantum well device;
步骤(6)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出第二n-GaN图形区域，所述的第二n-GaN图形区域位于第一n-GaN图形区域内，介于n-电极与相邻p-n结量子阱器件的p-电极之间；Step (6) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and a second n-GaN pattern area is defined on the photoresist layer by using a photolithography alignment technique. The second n- The GaN pattern region is located in the first n-GaN pattern region, between the n-electrode and the p-electrode of an adjacent pn junction quantum well device;
步骤(7)刻蚀第二n-GaN图形区域；去除残余光刻胶，在n-GaN层上形成位于p-电极和n-电极之间的凹陷区域；Step (7) etching the second n-GaN pattern region; removing the residual photoresist, and forming a recessed region between the p-electrode and the n-electrode on the n-GaN layer;
步骤(8)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出位于所述凹陷区域中的u-GaN层图形区域；Step (8): uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and defining a u-GaN layer pattern region in the recessed region on the photoresist layer by using a photolithography alignment technique;
步骤(9)从n-GaN层刻蚀到u-GaN层，去除残余光刻胶，得到凹槽和位于凹槽下方的u-GaN层；Step (9) Etching the n-GaN layer to the u-GaN layer, removing the residual photoresist, and obtaining a groove and a u-GaN layer located under the groove;
步骤(10)在硅基氮化物晶片上表面沉积一层连续的SiO 2层； Step (10) deposit a continuous SiO 2 layer on the upper surface of the silicon-based nitride wafer;
步骤(11)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术对准位于n-电极层的第一n-GaN图形区域、第二n-GaN图形区域、u-GaN层图形区域和p-电极区的p-GaN层图形区域；Step (11) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the first n-GaN pattern region and the second n-GaN pattern region on the n-electrode layer are aligned by using a photolithography alignment technique. , U-GaN layer pattern region and p-electrode region p-GaN layer pattern region;
步骤(12)使用BOE溶液湿法腐蚀掉多余的SiO 2； Step (12) use BOE solution to wet etch away excess SiO 2 ;
步骤(13)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术对准n-电极窗口区域、第一n-GaN图形区域、第二n-GaN图形区域、u-GaN层图形区域、p-电极窗口图形区域；Step (13) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the n-electrode window region, the first n-GaN pattern region, and the second n-GaN pattern region are aligned using a photolithography alignment technique. , U-GaN layer pattern area, p-electrode window pattern area;
步骤(14)在所述n-电极窗口区域、第一n-GaN层图形区域、第二n-GaN层图形区域、u-GaN层图形区域、p-电极窗口区域蒸镀一层连续的Ni/Au，以连接p-电极和n-电极；Step (14) A continuous layer of Ni is deposited on the n-electrode window region, the first n-GaN layer pattern region, the second n-GaN layer pattern region, the u-GaN layer pattern region, and the p-electrode window region. / Au to connect the p-electrode and the n-electrode;
步骤(15)在硅基氮化物晶片顶层涂胶保护，防止刻蚀过程中损伤表面器件，将外延缓冲层作为刻蚀阻挡层，利用背后深硅刻蚀技术，通过背后刻蚀窗口将所述硅衬底层贯穿刻蚀至外延缓冲层的下表面，形成一个空腔；Step (15): The top layer of the silicon-based nitride wafer is protected by coating to prevent damage to the surface devices during the etching process. The epitaxial buffer layer is used as an etching barrier layer. The deep silicon etching technology behind the substrate is used to etch the substrate through the back etching window. The silicon substrate layer is etched through to the lower surface of the epitaxial buffer layer to form a cavity;
步骤(16)去除残余光刻胶后，即得到悬空p-n结量子阱器件和串联器件集成阵列，p-电极和n-电极相连，各器件以串联形式相连。Step (16) After removing the residual photoresist, an integrated array of suspended p-n junction quantum well devices and serial devices is obtained, the p-electrode and the n-electrode are connected, and the devices are connected in series.
进一步的，本发明的悬空p-n结量子阱基串联阵列能量系统的制备方法中，所述步骤(5)、步骤(14)中的蒸镀Ni/Au，采用剥离工艺和温度控制在5005℃的氮气退火技术实现。Further, in the method for preparing a suspended pn junction quantum well-based tandem array energy system according to the present invention, the vapor deposition Ni / Au in steps (5) and (14) adopts a stripping process and a temperature controlled at 5005 ° C. Nitrogen annealing technology.
进一步的，本发明的悬空p-n结量子阱基串联阵列能量系统的制备方法中，所述步骤(3)、步骤(7)、步骤(9)中的刻蚀为离子束轰击或反应离子束刻蚀技术。Further, in the method for preparing a suspended pn junction quantum well-based tandem array energy system of the present invention, the etching in steps (3), (7), and (9) is ion beam bombardment or reactive ion beam etching. Eclipse technology.
进一步的，本发明的悬空p-n结量子阱基串联阵列能量系统的制备方法中，所述步骤(10)中，使用等离子体增强化学的气相沉积法沉积一层SiO 2层。 Further, in the method for preparing a suspended pn junction quantum well-based tandem array energy system of the present invention, in the step (10), a layer of SiO 2 is deposited using a plasma enhanced chemical vapor deposition method.
进一步的，本发明的悬空p-n结量子阱基串联阵列能量系统的制备方法中，所述步骤(3)、步骤(7)中，通过多次刻蚀到u-GaN层将各个器件隔离，在所述步骤(10)、步骤(14)中，随后沉积的连续的SiO 2层、金属层将各个器件的n-电极和p-电极串联。 Further, in the method for manufacturing a suspended pn junction quantum well-based tandem array energy system of the present invention, in the steps (3) and (7), each device is isolated by etching to a u-GaN layer multiple times, and In the step (10) and the step (14), successively deposited SiO 2 layers and metal layers connect the n-electrode and p-electrode of each device in series.
本发明将多个器件以串联阵列的形式集成在同一芯片上，在芯片内部以将电极串联，可实现微观级别的器件串联。将悬空p-n结量子阱器件作为光电探测器，可将光能转化为电能，作为可再生能源的一种，同时器件串联的形式可大大提高能量转换效率。将悬空p-n结量子阱器件作为LED光源，将转化的能量供给自身点亮，实现能 源的自给自足。In the present invention, multiple devices are integrated on the same chip in the form of a series array, and electrodes are connected in series inside the chip, so that micro-level devices can be connected in series. Using a suspended p-n junction quantum well device as a photodetector can convert light energy into electrical energy as a kind of renewable energy, and the device in series can greatly improve energy conversion efficiency. The floating p-n junction quantum well device is used as the LED light source, and the converted energy is supplied to light itself to achieve self-sufficiency of energy.
有益效果：本发明与现有技术相比，具有以下优点：Beneficial effect: Compared with the prior art, the present invention has the following advantages:
本发明的悬空p-n结量子阱基串联阵列能量系统及制备方法可实现多种功能：The suspended p-n junction quantum well-based tandem array energy system and the preparation method of the invention can realize various functions:
1、实现了微观级别的器件串联，将多个器件以串联形式集成在同一芯片内，实现器件的阵列排布；1. A series of micro-level devices are realized. Multiple devices are integrated in the same chip in series to realize the array arrangement of devices.
2、集成系统芯片可将光能转化为电能，可作为可再生新能源大规模生产，解决能源再生问题；2. The integrated system chip can convert light energy into electrical energy, which can be used as a large-scale production of renewable new energy to solve the problem of energy regeneration;
3、此集成系统芯片可在高温等严苛条件下运行，能够解决严苛条件下的能源再生问题。3. This integrated system chip can run under severe conditions such as high temperature, which can solve the problem of energy regeneration under severe conditions.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是本发明硅衬底悬空p-n结量子阱基串联阵列能量系统结构示意图。FIG. 1 is a schematic structural diagram of an energy system of a suspended p-n junction quantum well-based series array of a silicon substrate according to the present invention.
图2是本发明硅衬底悬空p-n结量子阱基串联阵列能量系统的俯视图。FIG. 2 is a top view of a p-n junction quantum well-based tandem array energy system of a silicon substrate of the present invention.
图3是本发明硅衬底悬空p-n结量子阱基串联阵列能量系统的工艺流程图。FIG. 3 is a process flow chart of a p-n junction quantum well-based tandem array energy system of a silicon substrate of the present invention.
图中有：1-硅衬底层；2-外延缓冲层；3-u-GaN层；4-n-GaN层；5-InGaN/GaN量子阱；6-SiO 2层；7-n-电极；8-p-GaN层；9-p-电极；10-金属层。 In the picture: 1-Si substrate layer; 2-Epitaxial buffer layer; 3-u-GaN layer; 4-n-GaN layer; 5-InGaN / GaN quantum well; 6-SiO 2 layer; 7-n-electrode; 8-p-GaN layer; 9-p-electrode; 10-metal layer.
具体实施方式detailed description
下面结合实施例和说明书附图对本发明作进一步的说明。The present invention is further described below with reference to the embodiments and the accompanying drawings.
图1给出了本发明的硅衬底悬空p-n结量子阱基串联阵列能量系统的结构示意图。图2给出了本发明的硅衬底悬空p-n结量子阱基串联阵列能量系统的俯视图，图中n-电极7、n-GaN层4、u-GaN层3、p-电极9上覆盖有一层金属层10，将上一个器件的n-电极7和下一个器件的p-电极9以串联形式相连。该集成系统以硅基氮化物晶片为载体，包括硅衬底层1、设置在所述硅衬底层1上的外延缓冲层2、设置在所述外延缓冲层2上的u-GaN层3、设置在u-GaN层3上的多个p-n结量子阱器件，所述p-n结量子阱器件包括设置有阶梯状台面的n-GaN层4、在所述阶梯状台面的上台面从下至上依次设置的InGaN/GaN量子阱层5、p-GaN层8和p-电极9、设置在所述阶梯状台面的下台面上的n-电极7，在两相邻的p-n结量子阱器件之间设置有刻蚀至u-GaN层3的凹槽，p-n结量子阱器件的n-电极7与其相邻p-n结量子阱器件的p-电极9之间通过金属层10连接，所述金属层10下设置有将其与InGaN/GaN量子阱5、n-GaN层4、u-GaN层3、p-GaN层8隔离的SiO 2层6。多个p-n结量子阱器件通过金属层10以串联形式相连。在芯片上将多个量子阱器件以微观阵列形式串联相连，可 大大增加量子阱器件的数目，从而增加能量转化速率。 FIG. 1 is a schematic diagram showing a structure of an energy system of a quantum well-based tandem array of a suspended pn junction of a silicon substrate of the present invention. FIG. 2 shows a top view of a pn junction quantum well-based tandem array energy system of a silicon substrate according to the present invention. The n-electrode 7, n-GaN layer 4, u-GaN layer 3, and p-electrode 9 are covered with a A metal layer 10 connects the n-electrode 7 of the previous device and the p-electrode 9 of the next device in series. The integrated system uses a silicon-based nitride wafer as a carrier, and includes a silicon substrate layer 1, an epitaxial buffer layer provided on the silicon substrate layer 1, a u-GaN layer 3 provided on the epitaxial buffer layer 2, and a set A plurality of pn-junction quantum well devices on the u-GaN layer 3, the pn-junction quantum well device including an n-GaN layer 4 provided with a stepped mesa, and the upper mesa of the stepped mesa is arranged in order from bottom to top InGaN / GaN quantum well layer 5, p-GaN layer 8, and p-electrode 9, and an n-electrode 7 disposed on the lower mesa of the stepped mesa are disposed between two adjacent pn junction quantum well devices There is a groove etched into the u-GaN layer 3, the n-electrode 7 of the pn junction quantum well device and the p-electrode 9 of its adjacent pn junction quantum well device are connected through a metal layer 10, A SiO 2 layer 6 is provided to isolate it from the InGaN / GaN quantum well 5, the n-GaN layer 4, the u-GaN layer 3, and the p-GaN layer 8. A plurality of pn junction quantum well devices are connected in series through the metal layer 10. Connecting multiple quantum well devices in series on the chip in the form of a micro-array can greatly increase the number of quantum well devices, thereby increasing the energy conversion rate.
图3给出了本发明的硅衬底悬空p-n结量子阱基串联阵列能量系统的制备方法流程，本发明方法的一种实施例包括以下步骤：FIG. 3 shows a flow of a method for preparing a silicon substrate suspended p-n junction quantum well-based tandem array energy system according to the present invention. An embodiment of the method of the present invention includes the following steps:
步骤(1)在硅基氮化物晶片背后对硅衬底层1进行减薄抛光；Step (1) thinning and polishing the silicon substrate layer 1 behind the silicon-based nitride wafer;
步骤(2)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出第一n-GaN图形区域；Step (2) uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and defining a first n-GaN pattern region on the photoresist layer by using a photolithography alignment technique;
步骤(3)采用反应离子束刻蚀第一n-GaN图形区域；去除残余光刻胶，得到阶梯状台面、位于上台面的p-n结量子阱器件的InGaN/GaN量子阱层5和p-GaN层8；Step (3) The first n-GaN pattern region is etched by using a reactive ion beam; the residual photoresist is removed to obtain a stepped mesa, an InGaN / GaN quantum well layer 5 and a p-GaN on the upper mesa pn junction quantum well device. Layer 8
步骤(4)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术定义出p-n结量子阱器件位于p-GaN层8上的两个p-电极窗口区域、位于n-GaN层4下台面的n-电极窗口区域，其中两个p-电极窗口区域位于第一n-GaN图形区域两侧；Step (4) uniformly coat a layer of photoresist on the upper surface of the silicon-based nitride wafer, and use photo-alignment technology to define two p-electrode window regions of the pn junction quantum well device on the p-GaN layer 8, An n-electrode window region located on the lower mesa of the n-GaN layer 4, wherein two p-electrode window regions are located on both sides of the first n-GaN pattern region;
步骤(5)在所述p-电极窗口区域与n-电极窗口区域分别蒸镀一层Ni/Au，形成欧姆接触，实现p-电极9与n-电极7，去除残余光刻胶后，即得到p-n结量子阱器件；Step (5) vapor-deposit a layer of Ni / Au in the p-electrode window area and the n-electrode window area to form an ohmic contact, and realize the p-electrode 9 and the n-electrode 7, after removing the residual photoresist, that is, Obtaining a pn junction quantum well device;
步骤(6)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出第二n-GaN图形区域，所述的第二n-GaN图形区域位于第一n-GaN图形区域内，介于n-电极7与下一个p-n结量子阱器件的p-电极9之间；Step (6) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and a second n-GaN pattern area is defined on the photoresist layer by using a photolithography alignment technique. The second n- The GaN pattern region is located in the first n-GaN pattern region, between the n-electrode 7 and the p-electrode 9 of the next pn junction quantum well device;
步骤(7)采用反应离子束刻蚀第二n-GaN图形区域；去除残余光刻胶，在n-GaN层4上形成位于p-电极9和n-电极7之间的凹陷区域；In step (7), the second n-GaN pattern region is etched by using a reactive ion beam; the remaining photoresist is removed, and a recessed region between the p-electrode 9 and the n-electrode 7 is formed on the n-GaN layer 4;
步骤(8)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出位于所述凹陷区域中的u-GaN层图形区域；Step (8): uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and defining a u-GaN layer pattern region in the recessed region on the photoresist layer by using a photolithography alignment technique;
步骤(9)采用反应离子束从n-GaN层4刻蚀到u-GaN层3；去除残余光刻胶，得到凹槽和位于凹槽下方的u-GaN层；Step (9) Etching the n-GaN layer 4 to the u-GaN layer 3 by using a reactive ion beam; removing the residual photoresist to obtain a groove and a u-GaN layer located under the groove;
步骤(10)在硅基氮化物晶片上表面沉积一层连续的SiO 2层6； Step (10) deposit a continuous SiO 2 layer 6 on the upper surface of the silicon-based nitride wafer;
步骤(11)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术对准位于n-电极层的第一n-GaN图形区域、第二n-GaN图形区域、u-GaN层图形区域和p-电极区的p-GaN层区域；Step (11) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the first n-GaN pattern region and the second n-GaN pattern region on the n-electrode layer are aligned by using a photolithography alignment technique. , U-GaN layer pattern region and p-GaN layer region of p-electrode region;
步骤(12)使用BOE溶液湿法腐蚀掉多余的SiO 2； Step (12) use BOE solution to wet etch away excess SiO 2 ;
步骤(13)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术对准n-电极窗口区域、第一n-GaN图形区域、第二n-GaN图形区域、u-GaN层图形区域、p-电极窗口区域；Step (13) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the n-electrode window region, the first n-GaN pattern region, and the second n-GaN pattern region are aligned using a photolithography alignment technique. , U-GaN layer pattern area, p-electrode window area;
步骤(14)在所述n-电极窗口区域、第一n-GaN图形区域、第二n-GaN图形区域、u-GaN层图形区域、p-电极窗口区域蒸镀一层连续的Ni/Au层，以连接p-电极9和n-电极7；Step (14) A continuous layer of Ni / Au is deposited on the n-electrode window region, the first n-GaN pattern region, the second n-GaN pattern region, the u-GaN layer pattern region, and the p-electrode window region. Layer to connect the p-electrode 9 and the n-electrode 7;
步骤(15)在硅基氮化物晶片顶层涂胶保护，防止刻蚀过程中损伤表面器件，将外延缓冲层2作为刻蚀阻挡层；利用背后深硅刻蚀技术，通过背后刻蚀窗口将所述硅衬底层1贯穿刻蚀至外延缓冲层2的下表面，形成一个空腔；Step (15): The top layer of the silicon-based nitride wafer is protected by coating to prevent damage to the surface device during the etching process, and the epitaxial buffer layer 2 is used as an etching barrier layer. The silicon substrate layer 1 is etched through to the lower surface of the epitaxial buffer layer 2 to form a cavity;
步骤(16)去除残余光刻胶后，即得到悬空p-n结量子阱器件和串联器件集成阵列，p-电极和n-电极相连，各器件以串联形式相连。Step (16) After removing the residual photoresist, an integrated array of suspended p-n junction quantum well devices and serial devices is obtained, the p-electrode and the n-electrode are connected, and the devices are connected in series.

Claims (8)

  1. 一种悬空p-n结量子阱基串联阵列能量系统，其特征在于，该系统以硅基氮化物晶片为载体，包括硅衬底层(1)、设置在所述硅衬底层(1)上的外延缓冲层(2)、设置在所述外延缓冲层(2)上的u-GaN层(3)、设置在u-GaN层(3)上的多个p-n结量子阱器件，所述p-n结量子阱器件包括设置有阶梯状台面的n-GaN层(4)、在所述阶梯状台面的上台面从下至上依次设置的InGaN/GaN量子阱层(5)、p-GaN层(8)和p-电极(9)、设置在所述阶梯状台面的下台面上的n-电极(7)，在两相邻的p-n结量子阱器件之间设置有刻蚀至u-GaN层(3)的凹槽，p-n结量子阱器件的n-电极(7)与其相邻p-n结量子阱器件的p-电极(9)之间通过金属层(10)连接，所述金属层(10)下设置有将其与InGaN/GaN量子阱(5)、n-GaN层(4)、u-GaN层(3)、p-GaN层(8)隔离的SiO 2层(6)。 A suspended pn junction quantum well-based tandem array energy system is characterized in that the system uses a silicon-based nitride wafer as a carrier and includes a silicon substrate layer (1) and an epitaxial buffer provided on the silicon substrate layer (1). Layer (2), u-GaN layer (3) provided on said epitaxial buffer layer (2), multiple pn junction quantum well devices provided on u-GaN layer (3), said pn junction quantum well The device includes an n-GaN layer (4) provided with a stepped mesa, an InGaN / GaN quantum well layer (5), a p-GaN layer (8), and p An electrode (9), an n-electrode (7) provided on the lower mesa of the stepped mesa, and an etched u-GaN layer (3) is provided between two adjacent pn junction quantum well devices The groove, the n-electrode (7) of the pn junction quantum well device and the p-electrode (9) of the adjacent pn junction quantum well device are connected by a metal layer (10), and the metal layer (10) is provided below A SiO 2 layer (6) that isolates it from the InGaN / GaN quantum well (5), the n-GaN layer (4), the u-GaN layer (3), and the p-GaN layer (8).
  2. 根据权利要求1所述的悬空p-n结量子阱基串联阵列能量系统，其特征在于，所述多个p-n结量子阱器件通过金属层(10)以串联形式相连。The floating p-n junction quantum well-based tandem array energy system according to claim 1, wherein the plurality of p-n junction quantum well devices are connected in series through a metal layer (10).
  3. 根据权利要求1或2所述的悬空p-n结量子阱基串联阵列能量系统，其特征在于，所述p-电极(9)和n-电极(7)均为Ni/Au电极，即沉积的金属材料为Ni/Au。The suspended pn junction quantum well-based tandem array energy system according to claim 1 or 2, wherein the p-electrode (9) and the n-electrode (7) are both Ni / Au electrodes, that is, deposited metals The material is Ni / Au.
  4. 一种制备悬空p-n结量子阱基串联阵列能量系统的方法，其特征在于，该方法包括以下步骤：A method for preparing a suspended p-n junction quantum well-based tandem array energy system is characterized in that the method includes the following steps:
    步骤(1)在硅基氮化物晶片背后对硅衬底层(1)进行减薄抛光；Step (1) thinning and polishing the silicon substrate layer (1) behind the silicon-based nitride wafer;
    步骤(2)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出所需的第一n-GaN图形区域；Step (2) uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and using photolithography alignment technology to define a required first n-GaN pattern area on the photoresist layer;
    步骤(3)刻蚀第一n-GaN图形区域；去除残余光刻胶，得到阶梯状台面、位于上台面的p-n结量子阱器件的InGaN/GaN量子阱层(5)和p-GaN层(8)；Step (3) etching the first n-GaN pattern region; removing the residual photoresist to obtain a stepped mesa, an InGaN / GaN quantum well layer (5) and a p-GaN layer (5) of a pn junction quantum well device located on the upper mesa. 8);
    步骤(4)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术定义出位于p-GaN层(8)上的p-电极窗口区域、位于n-GaN层(4)下台面的n-电极窗口区域；Step (4) uniformly coat a layer of photoresist on the upper surface of the silicon-based nitride wafer, and define a p-electrode window region on the p-GaN layer (8) and a n-GaN layer by using a photolithography alignment technique. (4) the n-electrode window area of the lower table;
    步骤(5)在所述p-电极窗口区域与n-电极窗口区域分别蒸镀一层Ni/Au，形成欧姆接触，实现p-电极(9)与n-电极(7)，去除残余光刻胶后，即得到p-n结量子阱器件；Step (5) vapor-deposit a layer of Ni / Au on the p-electrode window area and the n-electrode window area to form an ohmic contact to realize the p-electrode (9) and the n-electrode (7), and remove the residual photolithography After glueing, a pn junction quantum well device is obtained;
    步骤(6)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出第二n-GaN图形区域，所述的第二n-GaN图形区域位于第一n-GaN图形区域内，介于n-电极(7)与相邻p-n结量子阱器件的p-电极(9)之间；Step (6) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and a second n-GaN pattern area is defined on the photoresist layer by using a photolithography alignment technique. The second n- The GaN pattern region is located in the first n-GaN pattern region, between the n-electrode (7) and the p-electrode (9) of an adjacent pn junction quantum well device;
    步骤(7)刻蚀第二n-GaN图形区域，去除残余光刻胶，在n-GaN层(4)上形成位于D-电极(9)和n-电极(7)之间的凹陷区域；Step (7) etch the second n-GaN pattern region, remove the residual photoresist, and form a recessed region between the D-electrode (9) and the n-electrode (7) on the n-GaN layer (4);
    步骤(8)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术在光刻胶层上定义出位于所述凹陷区域中的u-GaN层图形区域；Step (8): uniformly coating a layer of photoresist on the upper surface of the silicon-based nitride wafer, and defining a u-GaN layer pattern region in the recessed region on the photoresist layer by using a photolithography alignment technique;
    步骤(9)从n-GaN层(4)刻蚀到u-GaN层(3)；去除残余光刻胶，得到凹槽和位于凹槽下方的u-GaN层；Step (9) etching from the n-GaN layer (4) to the u-GaN layer (3); removing the residual photoresist to obtain a groove and a u-GaN layer located under the groove;
    步骤(10)在硅基氮化物晶片上表面沉积一层连续的SiO 2层(6)； Step (10) deposit a continuous SiO 2 layer (6) on the upper surface of the silicon-based nitride wafer;
    步骤(11)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术对准位于n-电极层的第一n-GaN图形区域、第二n-GaN图形区域、u-GaN层图形区域和D-电极区的p-GaN层图形区域；Step (11) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the first n-GaN pattern region and the second n-GaN pattern region on the n-electrode layer are aligned by using a photolithography alignment technique. , U-GaN layer pattern region and p-GaN layer pattern region of D-electrode region;
    步骤(12)使用BOE溶液湿法腐蚀掉多余的SiO 2； Step (12) use BOE solution to wet etch away excess SiO 2 ;
    步骤(13)在硅基氮化物晶片上表面均匀涂上一层光刻胶，采用光刻对准技术对准n-电极窗口区域、第一n-GaN图形区域、第二n-GaN图形区域、u-GaN层图形区域、p-电极窗口图形区域；Step (13) A layer of photoresist is uniformly coated on the upper surface of the silicon-based nitride wafer, and the n-electrode window region, the first n-GaN pattern region, and the second n-GaN pattern region are aligned using a photolithography alignment technique. , U-GaN layer pattern area, p-electrode window pattern area;
    步骤(14)在所述n-电极窗口区域、第一n-GaN层图形区域、第二n-GaN层图形区域、u-GaN层图形区域、p-电极窗口区域蒸镀一层连续的Ni/Au，以连接p-电极(9)和n-电极(7)；Step (14) A continuous layer of Ni is deposited on the n-electrode window region, the first n-GaN layer pattern region, the second n-GaN layer pattern region, the u-GaN layer pattern region, and the p-electrode window region. / Au to connect the p-electrode (9) and the n-electrode (7);
    步骤(15)在硅基氮化物晶片顶层涂胶保护，防止刻蚀过程中损伤表面器件，将外延缓冲层(2)作为刻蚀阻挡层，利用背后深硅刻蚀技术，通过背后刻蚀窗口将所述硅衬底层(1)贯穿刻蚀至外延缓冲层(2)的下表面，形成一个空腔；In step (15), the top layer of the silicon-based nitride wafer is protected by coating to prevent damage to the surface device during the etching process. The epitaxial buffer layer (2) is used as an etching barrier layer, and the deep silicon etching technology behind is used to etch the window through the back Etching the silicon substrate layer (1) to the lower surface of the epitaxial buffer layer (2) to form a cavity;
    步骤(16)去除残余光刻胶后，即得到悬空p-n结量子阱器件和串联器件集成阵列，p-电极和n-电极相连，各器件以串联形式相连。Step (16) After removing the residual photoresist, an integrated array of suspended p-n junction quantum well devices and serial devices is obtained, the p-electrode and the n-electrode are connected, and the devices are connected in series.
  5. 根据权利要求4所述的悬空p-n结量子阱基串联阵列能量系统的制备方法，其特征在于，所述步骤(5)、步骤(14)中的蒸镀Ni/Au层(10)，采用剥离工艺和温度控制在500 5℃的氮气退火技术实现。The method for preparing a suspended pn junction quantum well-based tandem array energy system according to claim 4, characterized in that, in the step (5) and step (14), the vapor-deposited Ni / Au layer (10) is stripped. Process and temperature controlled by 500 ° C and 5 ° C nitrogen annealing technology.
  6. 根据权利要求4所述的悬空p-n结量子阱基串联阵列能量系统的制备方法，其特征在于，所述步骤(3)、步骤(7)、步骤(9)中的刻蚀为离子束轰击或反应离子束刻蚀技术。The method for preparing a suspended pn junction quantum well-based tandem array energy system according to claim 4, wherein the etching in the step (3), step (7), or step (9) is ion beam bombardment or Reactive ion beam etching technology.
  7. 根据权利要求4、5或6所述的悬空p-n结量子阱基串联阵列能量系统的制备方法，其特征在于，所述步骤(10)中，使用等离子体增强化学的气相沉积法沉积一 层Si0 2层(6)。 The method for preparing a suspended pn junction quantum well-based tandem array energy system according to claim 4, 5 or 6, wherein in the step (10), a layer of Si0 is deposited using a plasma enhanced chemical vapor deposition method. 2 floors (6).
  8. 根据权利要求4、5或6所述的制备悬空p-n结量子阱基串联阵列能量系统的方法，其特征在于，所述步骤(3)、步骤(7)中，通过多次刻蚀到u-GaN层(3)将各个器件隔离，在所述步骤(10)、步骤(14)中，随后沉积的连续的SiO 2层(6)、金属层(10)将各个器件的n-电极(7)和p-电极(9)串联。 The method for preparing a suspended pn junction quantum well-based tandem array energy system according to claim 4, 5 or 6, wherein in step (3) and step (7), etching to u- The GaN layer (3) isolates each device. In the step (10) and step (14), the successively deposited SiO 2 layer (6) and metal layer (10) separate the n-electrode (7) of each device. ) And p-electrode (9).
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