CN111628022B - GaAs-based photoelectric device and preparation method of array thereof - Google Patents

GaAs-based photoelectric device and preparation method of array thereof Download PDF

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CN111628022B
CN111628022B CN201910149206.3A CN201910149206A CN111628022B CN 111628022 B CN111628022 B CN 111628022B CN 201910149206 A CN201910149206 A CN 201910149206A CN 111628022 B CN111628022 B CN 111628022B
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layer
gaas
ohmic contact
substrate
top electrode
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CN111628022A (en
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陈弘
霍雯雪
贾海强
杜春花
江洋
王文新
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Institute of Physics of CAS
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Abstract

The invention provides a GaAs-based photoelectric device and a preparation method of a GaAs-based photoelectric device array, wherein the GaAs-based photoelectric device sequentially comprises the following components from bottom to top: a metal substrate assembly; a back electrode layer; a back electrode ohmic contact layer; a barrier layer for interchannel corrosion; a GaAs active layer; a top electrode ohmic contact layer; a top electrode layer. The preparation method comprises the following steps: 1) the GaAs-based photoelectric device epitaxial wafer comprises a substrate, a substrate corrosion barrier layer, a back electrode ohmic contact layer, a channel corrosion barrier layer, a GaAs active layer and a top electrode ohmic contact layer; 2) preparing a top electrode layer on the top electrode ohmic contact layer; 3) forming a street trench; 4) adhering a transition substrate on the top electrode layer; 5) removing the substrate and the substrate corrosion barrier layer; 6) preparing a back electrode layer on the back electrode ohmic contact layer; 7) preparing a metal substrate assembly on the back electrode layer; 8) and removing the transition substrate. The GaAs-based photoelectric device has good heat dissipation capability, and the preparation method improves the yield.

Description

GaAs-based photoelectric device and preparation method of array thereof
Technical Field
The invention relates to a photoelectric device, in particular to a GaAs-based photoelectric device and a preparation method of an array thereof.
Background
The photovoltaic device has two different structures of a planar type and a vertical type. The planar structure means that a top electrode and a back electrode of the photoelectric device are positioned on the same side of the photoelectric conversion layer, but the two electrodes positioned on the same side reduce the window area of incident light or emergent light of the photoelectric device, so that the photoelectric conversion performance of the photoelectric device is reduced. The vertical structure means that two electrodes of the photoelectric device are positioned at two opposite sides of the photoelectric conversion layer, and the influence on the window area of the photoelectric device is small. In addition, the current direction in the photoelectric device with the vertical structure is vertical to the photoelectric conversion layer, so that the current blocking effect is reduced.
In a GaAs-based opto-electronic device of the vertical type, the GaAs substrate has some defects. The GaAs substrate has poor thermal conductivity and low electrical conductivity, has a high absorption rate for light having a wavelength of less than 870nm (a wavelength corresponding to the bandgap of the GaAs substrate), and is thick and fragile, and cannot be folded and bent.
In order to improve the performance of a vertical type GaAs-based photoelectric device, an original substrate is removed and a metal substrate is prepared. The metal bonding method has high requirements on the cleanliness, the bending degree, the flatness and the like of the epitaxial wafer, and the device is damaged at higher bonding temperature, so that the yield is low.
Usually, a plurality of devices can be simultaneously prepared on the same substrate, the plurality of devices need to be separated into discrete sub-devices through later separation, and the separation method can adopt methods such as wet etching, dry etching, laser cutting and the like.
When the wet etching method is used for etching the channel to separate the devices, the epitaxial layer on the substrate is difficult to avoid being completely etched and penetrated, so that the devices are damaged when the later process steps are carried out, and the yield of the devices is reduced.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a GaAs-based photoelectric device, which sequentially comprises the following components from bottom to top:
a metal substrate assembly;
a back electrode layer;
a back electrode ohmic contact layer;
a barrier layer for interchannel corrosion;
a GaAs active layer;
a top electrode ohmic contact layer;
a top electrode layer.
Preferably, the metal substrate assembly is flexible and comprises a metal substrate and an underlying metal layer.
Preferably, the metal substrate is formed by stacking a plurality of different metals by plating or evaporation.
Preferably, the channel etch stop layer is InGaP, InAlP or AlxGa(1-x)As，x≥0.4。
Preferably, the GaAs-based opto-electronic device further comprises: the back field layer is positioned between the channel corrosion barrier layer and the GaAs active layer, the window layer is positioned between the GaAs active layer and the top electrode ohmic contact layer, and the forbidden bandwidth of the back field layer and the window layer are both larger than that of the GaAs active layer.
Preferably, one surface of the top electrode ohmic contact layer, which is in contact with the top electrode layer, has a pattern structure, and one surface of the back electrode ohmic contact layer, which is in contact with the back electrode layer, has a pattern structure.
Preferably, the GaAs-based optoelectronic device further includes:
the first dielectric layer and the top electrode layer are positioned on the surface of the top electrode ohmic contact layer, and the refractive index of the first dielectric layer is between that of air and that of the top electrode ohmic contact layer; and
and the second medium layer is positioned between the metal substrate assembly and the back electrode ohmic contact layer, and the refractive index of the second medium layer is between the refractive index of air and the refractive index of the back electrode ohmic contact layer.
The invention provides a preparation method of a GaAs-based photoelectric device array, which sequentially comprises the following steps:
step 1), providing a GaAs-based photoelectric device epitaxial wafer, which sequentially comprises a substrate, a substrate corrosion barrier layer, a back electrode ohmic contact layer, an inter-channel corrosion barrier layer, a GaAs active layer and a top electrode ohmic contact layer from bottom to top;
step 2), preparing a top electrode layer on the top electrode ohmic contact layer, wherein the top electrode layer comprises a plurality of groups of top electrodes, and isolation channels are formed between adjacent top electrodes in the plurality of groups of top electrodes;
step 3), in the direction vertical to the substrate, starting from the isolation inter-channel, corroding the top electrode ohmic contact layer until the surface of the inter-channel corrosion barrier layer, and stopping corrosion to form an inter-channel groove;
step 4), adhering a transition substrate on the top electrode layer;
step 5), removing the substrate and the substrate corrosion barrier layer;
step 6), preparing a back electrode layer on the back electrode ohmic contact layer;
step 7), preparing a metal substrate assembly on the back electrode layer;
step 8), removing the transition substrate;
and 9) slicing along the direction of the channel grooves.
Preferably, in the step 1), the substrate etch stop layer or the street etch stop layer is InGaP, InAlP, or AlxGa(1-x)As，x≥0.4。
Preferably, the growing the metal substrate assembly includes sequentially growing an underlying metal layer and a plurality of metal substrates on the surface of the back electrode layer, and a partition wall is provided between adjacent metal substrates in the plurality of metal substrates. Preferably, the plurality of metal substrates are grown by plating or evaporating a plurality of different metal layers.
Preferably, in step 1), the GaAs-based optoelectronic device epitaxial wafer further includes a back field layer located between the channel etching blocking layer and the GaAs active layer, and a window layer located between the GaAs active layer and the top electrode ohmic contact layer, where the forbidden bandwidths of the back field layer and the window layer are both greater than the forbidden bandwidth of the GaAs active layer.
Preferably, the method comprises the following steps between the step 1) and the step 2): forming a pattern structure on the surface of the top electrode ohmic contact layer; between the step 5) and the step 6), the method further comprises the following steps: and forming a pattern structure on the surface of the back electrode ohmic contact layer.
Preferably, the method further comprises the following steps between the step 2) and the step 3): preparing a dielectric layer on the surface of the top electrode ohmic contact layer in a region which is not covered by the top electrode layer and is outside the isolation channel; between step 6) and step 7), further comprising: and preparing a dielectric layer on the surface of the back electrode ohmic contact layer in the area which is not covered by the back electrode layer.
The invention also provides a preparation method of the GaAs-based photoelectric device array, which sequentially comprises the following steps:
step 1), providing a GaAs-based photoelectric device epitaxial wafer, which sequentially comprises a substrate, a substrate corrosion barrier layer, a top electrode ohmic contact layer, a GaAs active layer, an interlayer corrosion barrier layer and a back electrode ohmic contact layer from bottom to top;
step 2), preparing a back electrode layer on the back electrode ohmic contact layer;
step 3), preparing a metal substrate assembly on the back electrode layer;
step 4), adhering a transition substrate on the metal substrate assembly;
step 5), removing the substrate and the substrate corrosion barrier layer;
step 6), preparing a top electrode layer on the top electrode ohmic contact layer, wherein the top electrode layer comprises a plurality of groups of top electrodes, and isolation channels are formed between adjacent top electrodes in the plurality of groups of top electrodes;
step 7), in the direction vertical to the substrate, starting from the isolation inter-channel, corroding the top electrode ohmic contact layer until the surface of the inter-channel corrosion barrier layer, and stopping corrosion to form an inter-channel groove;
step 8), removing the transition substrate;
and 9) slicing along the direction of the channel grooves.
Preferably, in the step 1), the substrate etch stop layer or the inter-channel etch stop layer is InGaP, InAlP or AlxGa(1-x)As，x≥0.4。
Preferably, the growing the metal substrate assembly includes sequentially growing an underlying metal layer and a plurality of metal substrates on the surface of the back electrode layer, and a partition wall is provided between adjacent metal substrates in the plurality of metal substrates. Growing the plurality of metal substrates is formed by electroplating or evaporating a plurality of different metal layers.
Preferably, in step 1), the GaAs-based optoelectronic device epitaxial wafer further includes a back field layer located between the channel etching blocking layer and the GaAs active layer, and a window layer located between the GaAs active layer and the top electrode ohmic contact layer, where the forbidden bandwidths of the back field layer and the window layer are both greater than the forbidden bandwidth of the GaAs active layer.
Preferably, the method further comprises the following steps between the step 1) and the step 2): forming a pattern structure on the surface of the back electrode ohmic contact layer; between the step 5) and the step 6), the method further comprises the following steps: and forming a pattern structure on the surface of the top electrode ohmic contact layer.
Preferably, the method further comprises the following steps between the step 2) and the step 3): preparing a dielectric layer on the surface of the back electrode ohmic contact layer in the area which is not covered by the back electrode; between the step 6) and the step 7), the method further comprises the following steps: and preparing a dielectric layer on the surface of the top electrode ohmic contact layer in a region which is not covered by the electrode layer and is outside the isolation interchannel.
The metal substrate component in the GaAs-based photoelectric device has good heat conductivity and heat dissipation performance, improves the heat dissipation capacity of the GaAs-based photoelectric device, has the effect of improving reflection, and is favorable for improving the performance of the GaAs-based photoelectric device.
The metal base plate assembly is flexible, suitable for being bent and folded, and configured in various desired shapes.
The channel corrosion barrier layer avoids short circuit and damage of the GaAs-based photoelectric device caused in the manufacturing process, and the yield is improved.
Drawings
Embodiments of the invention are further described below with reference to the accompanying drawings, in which:
fig. 1 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 according to a first embodiment of the present invention.
Fig. 2 is a top view of the array of GaAs-based opto-electronic device structures from step 2 of the first embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of the array of GaAs-based opto-electronic device structures obtained in step 3 of the first embodiment of the present invention.
Fig. 4 is a top view of the array of GaAs-based optoelectronic device structures shown in fig. 3.
Fig. 5 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 4 of the first embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 5 of the first embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 7 of the first embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of a GaAs-based photovoltaic device array of a first embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 of a second embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of a GaAs-based opto-electronic device according to a second embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 of a third embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view of an array of GaAs-based optoelectronic device structures obtained in step 3 of a third embodiment of the present invention.
Fig. 13 is a schematic cross-sectional view after a pattern structure is formed on the surface of the back electrode ohmic contact layer of the GaAs-based opto-electronic device structure array according to the third embodiment of the present invention.
Fig. 14 is a schematic cross-sectional view of a GaAs-based photovoltaic device array of a third embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view of a GaAs-based photovoltaic device array of the present invention after a dielectric layer is formed on the top electrode layer.
Fig. 16 is a schematic cross-sectional view of a GaAs-based opto-electronic device array according to a fourth embodiment of the present invention.
Fig. 17 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided in step 1 according to a fifth embodiment of the present invention.
Fig. 18 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 3 of the fifth embodiment of the present invention.
Fig. 19 is a schematic cross-sectional view of the GaAs-based opto-electronic device structure array obtained in step 4 of the fifth embodiment of the present invention.
Fig. 20 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 7 of the fifth embodiment of the present invention.
Fig. 21 is a schematic cross-sectional view of a fifth embodiment of an array of GaAs-based opto-electronic devices in accordance with the present invention.
Fig. 22 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 in accordance with a sixth embodiment of the present invention.
Fig. 23 is a schematic cross-sectional view of a sixth embodiment of a GaAs-based opto-electronic device of the present invention.
Fig. 24 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 of a seventh embodiment of the present invention.
Fig. 25 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 3 of the seventh embodiment of the present invention.
Fig. 26 is a schematic cross-sectional view showing a top electrode ohmic contact layer according to the seventh embodiment of the invention after a pattern structure is formed on the surface thereof.
Fig. 27 is a schematic cross-sectional view of a seventh embodiment of an array of GaAs-based opto-electronic devices in accordance with the present invention.
Fig. 28 is a schematic sectional view after a dielectric layer is formed on the surface of the back electrode ohmic contact layer of the array of GaAs-based optoelectronic device structures according to the eighth embodiment of the present invention.
Fig. 29 is a schematic cross-sectional view of an eighth embodiment of a GaAs-based opto-electronic device array in accordance with the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail by embodiments with reference to the accompanying drawings. For ease of description and understanding, the cross-section in the cross-sectional schematic below is perpendicular to the substrate.
Example 1
Step 1: a GaAs-based optoelectronic device epitaxial wafer is provided.
Fig. 1 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 according to a first embodiment of the present invention. As shown in fig. 1, the epitaxial wafer sequentially includes, from bottom to top: the GaAs substrate comprises an N-type GaAs substrate 111, an N-type GaAs buffer layer 112, an InGaP substrate etching barrier layer 13, a highly doped P-type GaAs back electrode ohmic contact layer 14, an InGaP channel etching barrier layer 15, a GaAs active layer 16 and an N-type GaAs top electrode ohmic contact layer 17. Wherein the GaAs active layer 16 is used for the material for realizing photoelectric interconversion.
Step 2: and preparing a plurality of groups of grid-shaped photoresist patterns on the surface of the ohmic contact layer 17 of the N-type GaAs top electrode.
Fig. 2 is a top view of the GaAs-based optoelectronic device structure array obtained in step 2 according to the first embodiment of the present invention, and as shown in fig. 2, a plurality of gate-like photoresists 171 are parallel to each other and located on the surface of the N-type GaAs top electrode ohmic contact layer 17.
And step 3: and (3) depositing Ni/Au/Ge/Ni/Au on the multi-group grid-shaped photoresist patterns and the surface of the ohmic contact layer 17 of the N-type GaAs top electrode by using an electron beam evaporation technology, and stripping the photoresist by using organic solvents such as acetone to obtain the multi-group grid-shaped electrodes.
Fig. 3 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 3 of the first embodiment of the present invention, and fig. 4 is a top view of the GaAs-based optoelectronic device structure array shown in fig. 3. As shown in fig. 3-4, the top electrode layer includes a plurality of sets (only two of which are shown in fig. 3-4) of top electrodes 181, 182 on the surface of the N-type GaAs top electrode ohmic contact layer 17, with an isolation street between adjacent top electrodes 181, 182. The top electrodes 181, 182 are grid electrodes, and the shape of the via holes thereon is the same as the pattern of the grid photoresist 171 (see fig. 2).
And 4, step 4: etching the N-type GaAs top electrode ohmic contact layer 17 and a part of the GaAs active layer 16 from the isolation streets in a direction perpendicular to the substrate to form street trenches, stopping when etching to the surface of the street etch stop layer 15 based on a high selectivity for etching GaAs and InGaP; a sapphire transition substrate was adhered to the surface of the top electrode layer by a high temperature wax.
Fig. 5 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 4 of the first embodiment of the present invention. As shown in fig. 5, the top electrode layer has an adhesive layer 191 and a transition substrate 192 on a surface thereof in this order.
And 5: the N-type GaAs substrate 111, the N-type GaAs buffer layer 112, and the InGaP substrate etch barrier layer 13 are removed by wet etching. Firstly, selecting an etching solution with high selection ratio to GaAs and InGaP to etch off the N-type GaAs substrate 111 and the N-type GaAs buffer layer 112; and then selecting a proper etching solution to etch the InGaP substrate etch stop layer 13.
Fig. 6 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 5 of the first embodiment of the present invention. As shown in fig. 6, after the InGaP substrate etch stop layer 13 is etched, the surface of the highly doped P-type GaAs back electrode ohmic contact layer 14 is exposed.
Step 6: a back electrode layer made of Ti/Au was evaporated on the surface of the back electrode ohmic contact layer 14 using an electron beam evaporation process.
And 7: an under metal layer made of aluminum is vapor-deposited on the surface of the back electrode layer, and a plurality of metal substrates made of copper are prepared by electroplating, with adjacent metal substrates being separated by a partition wall 103', and partition walls aligned with the via grooves are prepared on the surface of the under metal layer.
Fig. 7 is a schematic cross-sectional view of the array of GaAs-based opto-electronic device structures resulting from step 7 of the first embodiment of the present invention. As shown in fig. 7, the ohmic contact between the back electrode layer 101 and the back electrode ohmic contact layer 14, the 50 μm thick metal substrate 103 and the about 1 μm thick underlying metal layer 102 constitute a flexible metal substrate assembly.
And 8: the sapphire transition substrate 192, the adhesion layer 191 and the partition walls 103' are removed.
Fig. 8 is a schematic cross-sectional view of an array of GaAs-based optoelectronic devices according to a first embodiment of the present invention. As shown in fig. 8, the structure sequentially includes, from bottom to top, a metal substrate 103, a bottom metal layer 102, a back electrode layer 101, a highly doped P-type GaAs back electrode ohmic contact layer 14, an InGaP inter-channel etching barrier layer 15, a GaAs active layer 16, an N-type GaAs top electrode ohmic contact layer 17, and a top electrode layer 182.
And step 9: and slicing along the direction of the channel grooves to obtain a plurality of GaAs-based photoelectric devices.
When the back electrode layer 101 is prepared in step 6, the channel corrosion barrier layer 15 prevents evaporated metal from entering the channel grooves to cause short circuit and damage of the GaAs-based photoelectric device, so that the yield of the channel corrosion barrier layer 15 is improved.
The InGaP substrate etch stop layer 13 is advantageous to extend GaAs material on the surface thereof, and the high selectivity of InGaP and GaAs in etching is convenient to etch the N-type GaAs substrate 111.
The sum of the thicknesses of the metal substrate 103 and the underlying metal layer 102 is in the order of micrometers, and is suitable for being manufactured into a desired non-planar shape as a foldable, bendable flexible substrate; and the GaAs-based photoelectric device has excellent heat-conducting property, and can improve the heat-radiating performance of the GaAs-based photoelectric device.
The underlying metal layer 102 serves as a seed layer for preparing the metal substrate 103, and functions to adhere the metal substrate 103 and the back electrode layer 101; the underlying metal layer 102 is used as a reflecting layer for reflecting incident light waves, so that the back reflection capability is further improved; the underlying metal layer 102 also serves as a stress adjustment layer for adjusting stress between the metal substrate 103 and the back electrode layer 101.
Example 2
It is essentially the same as example 1, with the following differences:
in step 1, a GaAs-based optoelectronic device epitaxial wafer is provided.
Fig. 9 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided in step 1 according to a second embodiment of the present invention. As shown in fig. 9, the epitaxial wafer sequentially includes, from bottom to top: the GaAs substrate comprises an N-type GaAs substrate 211, an N-type GaAs buffer layer 212, an InGaP substrate corrosion barrier layer 23, a highly doped P-type GaAs back electrode ohmic contact layer 24, an InGaP channel corrosion barrier layer 25, a P-type AlGaAs back field layer 256, a GaAs active layer 26, an InGaP window layer 267 and an N-type GaAs top electrode ohmic contact layer 27.
Other steps are the same as embodiment 1, and are not described herein again.
Fig. 10 is a schematic cross-sectional view of a GaAs-based optoelectronic device according to a second embodiment of the present invention, as shown in fig. 10, which sequentially includes a metal substrate 203, a bottom metal layer 202, a back electrode layer 201, a highly doped P-type GaAs back electrode ohmic contact layer 24, an InGaP inter-channel etching barrier layer 25, a P-type AlGaAs back field layer 256, a GaAs active layer 26, an InGaP window layer 267, an N-type GaAs top electrode ohmic contact layer 27, and a top electrode layer 28 from bottom to top.
The forbidden bandwidth of the AlGaAs back field layer 256 is larger than that of the GaAs active layer 26, reducing surface recombination of the GaAs active layer 26.
The forbidden band width of the InGaP window layer 267 is larger than that of the GaAs active layer 26, so that the surface recombination of the GaAs active layer 26 is reduced, and the light incidence rate is improved.
Example 3
It is essentially the same as example 1, with the following differences:
in step 1, a GaAs-based optoelectronic device epitaxial wafer is provided.
Fig. 11 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 of a third embodiment of the present invention. As shown in fig. 11, the epitaxial wafer sequentially includes, from bottom to top: the semiconductor device comprises an N-type GaAs substrate 311, an N-type GaAs buffer layer 312, an InGaP substrate corrosion barrier layer 33, a high-doped P-type GaAs back electrode ohmic contact layer 34, an InGaP channel corrosion barrier layer 35, a P-type AlGaAs back field layer 356, a GaAs active layer 36, an InGaP window layer 367 and an N-type GaAs top electrode ohmic contact layer 37.
The following steps are included after step 1: and preparing a photoresist pattern on the surface of the N-type GaAs top electrode ohmic contact layer 37, and forming a pattern structure on the surface of the N-type GaAs top electrode ohmic contact layer 37 through dry etching or wet etching.
Step 2-3, a top electrode layer is prepared on the surface of the N-type GaAs top electrode ohmic contact layer 37, which is the same as step 2-3 of embodiment 1, and the specific process is not described herein again.
Fig. 12 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 3 according to the third embodiment of the present invention. As shown in fig. 3, the surface of the N-type GaAs top electrode ohmic contact layer 37 has a groove, and the top electrode layer 38 includes a plurality of sets of top electrodes with an isolation gap between adjacent top electrodes.
Step 4-5, beginning to etch a part of the N-type GaAs top electrode ohmic contact layer 37, the InGaP window layer 367, the GaAs active layer 36 and the P-type AlGaAs back field layer 356 from the isolation channel along the direction vertical to the substrate to form a channel groove, and stopping etching until reaching the surface of the channel etching barrier layer 35; a transition substrate is adhered to the surface of the top electrode layer 38, the N-type GaAs substrate 311 and the N-type GaAs buffer layer 312 are removed, and then the InGaP substrate etch stop layer 33 is removed. It is the same as step 4-5 of embodiment 1, and the detailed process is not repeated herein.
The following steps are also included after step 5: and preparing a photoresist pattern on the surface of the high-doping P-type GaAs back electrode ohmic contact layer 34, and etching the surface of the high-doping P-type GaAs back electrode ohmic contact layer 34 by using a dry method or a wet method to form a pattern structure on the surface.
Fig. 13 is a schematic cross-sectional view after a pattern structure is formed on the surface of the back electrode ohmic contact layer of the GaAs-based opto-electronic device structure array according to the third embodiment of the present invention. As shown in fig. 13, the surface of the highly doped P-type GaAs back-electrode ohmic contact layer 34 has a protrusion.
Step 6 to 8, a back electrode layer is prepared on the surface of the back electrode ohmic contact layer 34, a metal substrate assembly is prepared on the surface of the back electrode layer, and the transition substrate, the adhesion layer and the isolation wall are removed, which is the same as step 6 to 8 of embodiment 1, and the specific process is not repeated here.
Fig. 14 is a schematic cross-sectional view of a GaAs-based optoelectronic device array according to a third embodiment of the present invention, as shown in fig. 14, which sequentially includes, from bottom to top, a metal substrate 303, a bottom metal layer 302, a back electrode layer 301, a highly doped P-type GaAs back electrode ohmic contact layer 34, an InGaP inter-channel etching barrier layer 35, a P-type AlGaAs back field layer 356, a GaAs active layer 36, an InGaP window layer 367, an N-type GaAs top electrode ohmic contact layer 37, and a top electrode layer 38.
And 9, slicing along the direction of the channel grooves to obtain a plurality of GaAs-based photoelectric devices.
One of the surfaces of the N-type GaAs top electrode ohmic contact layer 37 in contact with the top electrode layer 38 has a groove, and the incidence rate of light can be increased.
One of the surfaces of the back electrode ohmic contact layer 34 contacting the back electrode layer 301 has a pattern structure capable of reflecting light back into the active layer 36 as a back reflection layer.
Example 4
It is essentially the same as example 3, with the following differences:
step 1-3, providing a GaAs-based photoelectric device epitaxial wafer as shown in fig. 11, forming a pattern structure on the surface of the ohmic contact layer of the N-type GaAs top electrode, and preparing a grid-shaped top electrode layer thereon. It is the same as step 1-3 of example 3, and the detailed process is not repeated here.
The following steps are also included after step 3: preparing SiO in the region which is not covered by the top electrode layer and is not isolated with the interchannel on the surface of the N-type GaAs top electrode ohmic contact layer by a PECVD process2The dielectric layer of (2).
Fig. 15 is a schematic cross-sectional view after a dielectric layer is formed on the surface of the top electrode layer of the GaAs-based optoelectronic device structure array according to the fourth embodiment of the present invention. As shown in fig. 15, from bottom to top, the following are included in sequence: an N-type GaAs substrate 411, an N-type GaAs buffer layer 412, an InGaP substrate etching stopper layer 43, a highly doped P-type GaAs back electrode ohmic contact layer 44, an InGaP channel etching stopper layer 45, a P-type AlGaAs back field layer 456, a GaAs active layer 46, an InGaP window layer 467, an N-type GaAs top electrode ohmic contact layer 47, and a top electrode layer 48 and a dielectric layer 491 on the surface of the N-type GaAs top electrode ohmic contact layer 47.
Step 4-6, beginning to etch a part of the N-type GaAs top electrode ohmic contact layer 47, the InGaP window layer 467, the GaAs active layer 46 and the P-type AlGaAs back field layer 456 from the isolation channels along the direction vertical to the substrate to form channel grooves, and stopping etching until the surface of the channel etching barrier layer 45; and adhering a transition substrate on the surface of the top electrode layer 48, removing the N-type GaAs substrate 411, the N-type GaAs buffer layer 412 and the InGaP substrate corrosion barrier layer 43, so that a pattern structure is formed on the surface of the highly-doped P-type GaAs back electrode ohmic contact layer 44, and preparing a back electrode layer on the surface of the highly-doped P-type GaAs back electrode ohmic contact layer 44. It is the same as step 4-6 of embodiment 3, and the detailed process is not repeated here.
The following steps are also included after step 6: preparing SiO by PECVD in the region of the surface of the high-doped P-type GaAs back electrode ohmic contact layer 44 not covered by the back electrode layer2The dielectric layer of (2).
Step 7-8, preparing a metal substrate assembly on the surface of the back electrode layer, and removing the transition substrate, the adhesion layer and the isolation wall, which is the same as step 7-8 of embodiment 1 or embodiment 3, and the specific process is not described herein again.
Fig. 16 is a schematic cross-sectional view of a GaAs-based optoelectronic device array according to a fourth embodiment of the present invention, as shown in fig. 16, from bottom to top, comprising: the metal substrate 403, the bottom metal layer 402, the back electrode layer 401 and the dielectric layer 492 on the surface of the bottom metal layer 402, the high-doped P-type GaAs back electrode ohmic contact layer 44, the InGaP channel etching barrier layer 45, the P-type AlGaAs back field layer 456, the GaAs active layer 46, the InGaP window layer 467, the N-type GaAs top electrode ohmic contact layer 47, the top electrode layer 48 on the surface of the N-type GaAs top electrode ohmic contact layer 47 and the dielectric layer 491.
The dielectric layer 492 covers the surface of the highly doped P-type GaAs back electrode ohmic contact layer 44 in the region not covered by the back electrode layer 401. The dielectric layer 492 has a refractive index between that of air and the back electrode ohmic contact layer, which may act as an antireflective film to enhance light reflection back to the active region.
The dielectric layer 491, which has a refractive index between that of air and the ohmic contact layer of the top electrode, serves as an antireflection film to improve the incident efficiency of light.
In other embodiments of the present invention, the surface of the dielectric layer 491 has a pattern structure, which further improves the incident efficiency of light.
Example 5
Step 1: a GaAs-based optoelectronic device epitaxial wafer is provided.
Fig. 17 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 of a fifth embodiment of the present invention. As shown in fig. 17, the epitaxial wafer sequentially includes, from bottom to top: an N-type GaAs substrate 511, an N-type GaAs buffer layer 512, an InGaP substrate etching barrier layer 53, an N-type GaAs top electrode ohmic contact layer 57, a GaAs active layer 56, an InGaP channel etching barrier layer 55 and a highly doped P-type GaAs back electrode ohmic contact layer 54. Wherein the GaAs active layer 56 includes stacked N-type GaAs emitter and P-type GaAs base regions.
And 2, step: and evaporating a back electrode layer made of Ti/Au on the surface of the high-doped P type GaAs back electrode ohmic contact layer 54 by using an electron beam evaporation process.
And 3, step 3: an underlying metal layer made of aluminum is vapor-deposited on the surface of the back electrode layer, and partition walls 503 'are prepared on the surface of the underlying metal layer, and a plurality of metal substrates are formed by copper electroplating, wherein the metal substrates are separated from each other by the partition walls 503'.
Fig. 18 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 3 of the fifth embodiment of the present invention, wherein a back electrode layer 501, an underlying metal layer 502, and a metal substrate 503 are sequentially disposed on the surface of the highly doped P-type GaAs back electrode ohmic contact layer 54.
And 4, step 4: a sapphire transition substrate is bonded to the surface of the metal substrate 503 by high temperature wax.
Fig. 19 is a schematic cross-sectional view of the GaAs-based opto-electronic device structure array obtained in step 4 of the fifth embodiment of the present invention. As shown in fig. 19, the metal substrate 503 has an adhesion layer 591 and a transition substrate 592 on a surface thereof in this order.
And 5: the N-GaAs substrate 511 and the N-GaAs buffer layer 512 are removed by wet etching, and then the InGaP substrate etch stop layer 53 is removed to expose the surface of the top electrode ohmic contact layer 57.
And 6: a gate photoresist pattern is prepared on the surface of the top electrode ohmic contact layer 57.
And 7: and evaporating Ni/Au/Ge/Ni/Au on the grid-shaped photoresist pattern by using an electron beam evaporation technology, stripping the photoresist by using an organic solvent such as acetone to obtain a top electrode layer 58, wherein isolation channels are formed among a plurality of top electrodes of the top electrode layer, and part of the top electrode layer 58, the N-type GaAs top electrode ohmic contact layer 57 and the GaAs active layer 56 of the GaAs-based photoelectric device is etched or corroded from the isolation channels to form channel grooves. Based on the high selection ratio of etching GaAs and InGaP, etching is stopped when reaching the surface of the inter-channel etching stopper 55, and at this time, the InGaP inter-channel etching stopper 55 prevents further etching of the back electrode ohmic contact layer 54, the back electrode layer 501, and the like, thereby preventing damage to the GaAs-based photoelectric device, and thus improving the yield in the manufacturing process.
Fig. 20 is a schematic cross-sectional view of the array of GaAs-based opto-electronic device structures from step 7 of a fifth embodiment of the present invention. As shown in fig. 20, the top electrode ohmic contact layer 57 has a top electrode layer 58 on a surface thereof.
And 8: the sapphire transition substrate 592, the adhesion layer 591 and the partition wall 503' are removed.
Fig. 21 is a schematic cross-sectional view of a GaAs-based optoelectronic device array according to a fifth embodiment of the present invention, as shown in fig. 21, which sequentially includes, from bottom to top, a metal substrate 503, a bottom metal layer 502, a back electrode layer 501, a highly doped P-type GaAs back electrode ohmic contact layer 54, an InGaP inter-channel etching barrier layer 55, a GaAs active layer 56, an N-type GaAs top electrode ohmic contact layer 57, and a top electrode layer 58.
And 9, slicing along the direction of the channel grooves to obtain a plurality of GaAs-based photoelectric devices.
Example 6
It is essentially the same as example 5, with the following differences:
in step 1, a GaAs-based photovoltaic device epitaxial wafer is provided.
Fig. 22 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 in accordance with a sixth embodiment of the present invention. As shown in fig. 22, the epitaxial wafer includes, from bottom to top: an N-type GaAs substrate 611, an N-type GaAs buffer layer 612, an InGaP substrate corrosion barrier layer 63, an N-type GaAs top electrode ohmic contact layer 67, an InGaP window layer 667, a GaAs active layer 66, a P-type AlGaAs back field layer 656, an InGaP channel corrosion barrier layer 65 and a highly doped P-type GaAs back electrode ohmic contact layer 64.
The other steps are the same as those in embodiment 5, and are not described herein again.
Fig. 23 is a schematic cross-sectional view of a GaAs-based optoelectronic device according to a sixth embodiment of the present invention, as shown in fig. 23, which sequentially includes, from bottom to top, a metal substrate 603, a bottom metal layer 602, a back electrode layer 601, a highly doped P-type GaAs back electrode ohmic contact layer 64, an InGaP inter-channel etching barrier layer 65, a P-type AlGaAs back field layer 656, a GaAs active layer 66, an InGaP window layer 667, an N-type GaAs top electrode ohmic contact layer 67, and a top electrode layer 68.
Example 7
It is essentially the same as example 5, with the following differences:
in step 1, a GaAs-based photovoltaic device epitaxial wafer is provided.
Fig. 24 is a schematic cross-sectional view of an epitaxial wafer of a GaAs-based opto-electronic device provided at step 1 of a seventh embodiment of the present invention. As shown in fig. 24, the epitaxial wafer includes, from bottom to top: an N-type GaAs substrate 711, an N-type GaAs buffer layer 712, an InGaP substrate etching barrier layer 73, an N-type GaAs top electrode ohmic contact layer 77, an InGaP window layer 767, a GaAs active layer 76, a P-type AlGaAs back field layer 756, an InGaP channel etching barrier layer 75 and a highly doped P-type GaAs back electrode ohmic contact layer 74.
The following steps are included after step 1: and preparing a photoresist pattern on the surface of the high-doping P-type GaAs back electrode ohmic contact layer 74, and enabling the surface of the high-doping P-type GaAs back electrode ohmic contact layer 74 to have a pattern structure through dry etching or wet etching.
And 2-3, sequentially preparing a back electrode layer, a bottom metal layer and a metal substrate on the surface of the high-doping P-type GaAs back electrode ohmic contact layer 74. It is the same as step 2-3 of example 5, and the detailed process is not repeated herein.
Fig. 25 is a schematic cross-sectional view of the GaAs-based optoelectronic device structure array obtained in step 3 of the seventh embodiment of the present invention. As shown in fig. 25, the surface of the highly doped P-type GaAs back electrode ohmic contact layer 74 has a protrusion, the surface of the back electrode layer 701 has a groove adapted to the protrusion, and the underlying metal layer 702 and the metal substrate 703 constitute a flexible metal substrate assembly.
Step 4-5, adhering the transition substrate 792 on the surface of the metal substrate 703, removing the N-GaAs substrate 711 and the N-GaAs buffer layer 712, and then removing the InGaP substrate etch stop layer 73. It is the same as step 4-5 of example 5, and the detailed process is not repeated here.
The following steps are also included after the step 5: and preparing a photoresist pattern on the surface of the ohmic contact layer 77 of the top electrode of the N-type GaAs, and then enabling the surface of the ohmic contact layer 77 of the top electrode of the N-type GaAs to have a pattern structure by using a dry etching method or a wet etching method.
Fig. 26 is a schematic cross-sectional view showing a top electrode ohmic contact layer according to the seventh embodiment of the invention after a pattern structure is formed on the surface thereof. As shown in fig. 26, the metal substrate 703 has an adhesion layer 791 and a sapphire transition substrate 792 on the surface thereof in this order, and the pattern structure of the surface of the N-type GaAs top electrode ohmic contact layer 77 is a groove.
In step 6-8, a top electrode layer is prepared on the surface of the N-type GaAs top electrode ohmic contact layer 77, isolation streets are formed between the top electrodes of the top electrode layer, a portion of the N-type GaAs top electrode ohmic contact layer 77, the InGaP window layer 767, the GaAs active layer 76, and the P-type AlGaAs back field layer 756 is etched from the isolation streets to form street trenches, and the transition substrate, the adhesion layer, and the isolation walls are removed. It is the same as step 6-8 of example 5, and the detailed process is not repeated here.
FIG. 27 is a schematic cross-sectional view of a seventh exemplary GaAs-based photovoltaic device array of the present invention, comprising, in order from bottom to top: the structure comprises a metal substrate 703, a bottom metal layer 702, a back electrode layer 701, a highly doped P-type GaAs back electrode ohmic contact layer 74, an InGaP channel etching barrier layer 75, a P-type AlGaAs back field layer 756, a GaAs active layer 76, an InGaP window layer 767, an N-type GaAs top electrode ohmic contact layer 77 and a top electrode layer 78.
And 9, slicing along the direction of the channel grooves to obtain a plurality of GaAs-based photoelectric devices.
Example 8
It is essentially the same as example 7, with the following differences:
step 1-2, providing a GaAs-based optoelectronic device epitaxial wafer as shown in fig. 24, so that the surface of the back electrode ohmic contact layer has a pattern structure, and preparing a back electrode layer on the surface thereof. It is the same as step 1-2 of example 7, and the detailed process is not repeated here.
The following steps are also included after step 2: a back electrode layer is not coated on the surface of the back electrode ohmic contact layer by adopting a PECVD processSiO production in regions covering and not isolating the streets2The dielectric layer of (2).
Fig. 28 is a schematic cross-sectional view of an eighth embodiment of the present invention after a dielectric layer is formed on the surface of the back electrode ohmic contact layer of the GaAs-based optoelectronic device structure array. As shown in fig. 28, the device comprises, from bottom to top: an N-type GaAs substrate 811, an N-type GaAs buffer layer 812, an InGaP substrate etching barrier layer 83, an N-type GaAs top electrode ohmic contact layer 87, an InGaP window layer 867, a GaAs active layer 86, a P-type AlGaAs back field layer 856, an InGaP inter-channel etching barrier layer 85, a highly doped P-type GaAs back electrode ohmic contact layer 84, and a back electrode layer 801 and a dielectric layer 892 on the surface of the highly doped P-type GaAs back electrode ohmic contact layer 84.
And 3-7, sequentially growing a bottoming metal layer and a metal substrate on the surface of the back electrode layer 801, adhering the transition substrate on the surface of the metal substrate, removing the N-type GaAs substrate 811 and the N-type GaAs buffer layer 812, removing the InGaP substrate corrosion barrier layer 83, forming a pattern structure on the surface of the N-type GaAs top electrode ohmic contact layer 87, preparing a top electrode layer on the surface, forming isolation channels among a plurality of top electrodes of the top electrode layer, and corroding a part of the N-type GaAs top electrode ohmic contact layer 87, the InGaP window layer 867, the GaAs active layer 86 and the P-type AlGaAs back field layer 856 from the isolation channels to form channel grooves. It is the same as step 3-7 of example 7, and the detailed process is not repeated here.
The following steps are also included after step 7: preparing SiO by PECVD in the region uncovered by the top electrode layer on the surface of the ohmic contact layer 87 of the N-type GaAs top electrode2The dielectric layer of (2).
And 8, removing the transition substrate, the adhesion layer and the isolation wall.
Fig. 29 is a schematic cross-sectional view of an eighth embodiment of a GaAs-based photovoltaic device array of the present invention. As shown in fig. 29, the device comprises, from bottom to top: the structure comprises a metal substrate 803, an underlying metal layer 802, a back electrode layer 801 and a dielectric layer 892 which are positioned on the underlying metal layer 802, a highly doped P-type GaAs back electrode ohmic contact layer 84, an InGaP channel corrosion barrier layer 85, a P-type AlGaAs back field layer 856, a GaAs active layer 86, an InGaP window layer 867, an N-type GaAs top electrode ohmic contact layer 87, and a top electrode layer 88 and a dielectric layer 891 which are positioned on the surface of the N-type GaAs top electrode ohmic contact layer 87.
And 9, slicing along the direction of the channel grooves to obtain a plurality of GaAs-based photoelectric devices.
In other embodiments of the present invention, a continuous metal substrate may also be prepared on the surface of the underlying metal layer, i.e. the underlying metal layer does not have a partition wall thereon.
In other embodiments of the present invention, the active layer is a material layer for realizing photoelectric conversion, and the structure thereof is not limited to a PN junction depletion region, and may be a GaAs-based semiconductor material layer, a quantum well structure, or a quantum dot structure.
In other embodiments of the present invention, the ohmic contact layer is a highly doped P-type semiconductor or a highly doped N-type semiconductor, and can form a good ohmic contact with the electrode layer, and simultaneously, current spreading of the device is realized, so that carriers are uniformly distributed in the active layer, and the photoelectric performance of the device is improved.
In other embodiments of the present invention, the corrosion barrier layer is InAlP or AlxGa(1-x)As，x≥0.4。
In other embodiments of the present invention, the dielectric layer is prepared by using electron beam evaporation, magnetron sputtering, and other dielectric film evaporation techniques, and the dielectric layer includes silicon nitride and TiO2、Al2O3A resin or polyimide material.
In other embodiments of the present invention, the material of the window layer, the back field layer includes AlGaAs, InGaP or InAlP.
In other embodiments of the present invention, the pattern structure includes a hemispherical shape, a segment shape, a semi-ellipsoidal shape, a truncated cone shape, a conical shape, a columnar protrusion or a groove matched therewith.
In other embodiments of the present invention, the transition substrate includes a Si substrate, a GaP substrate, a glass substrate, a SiC substrate, a Ge substrate, a PCB board, or the like, and the adhesion layer includes photoresist, polyimide, BCB, photosensitive glue, thermal glue, vacuum ester, or the like.
In other embodiments of the present invention, the electrode layer and the underlying metal layer are prepared by a metal thin film growth process such as magnetron sputtering, electron beam evaporation, ion beam evaporation, thermal evaporation, etc., the material of the electrode layer includes at least one of In, Sn, Al, Au, Pt, Zn, Ag, Ti, Pb, Pd, Ge, Cu, Be, and Ni, the underlying metal layer includes at least one of Ti, Au, Cr, Ni, Ag, Cu, and Al, and the metal substrate includes at least one of gold, silver, copper, aluminum, nickel, molybdenum, titanium, and chromium.
The present invention is not intended to limit the thickness of the metal substrate assembly composed of the metal substrate and the underlying metal layer, and the metal substrate assembly of the present invention is preferably flexible.
In other embodiments of the present invention, the metal substrate is formed by electroplating multiple layers of different metals stacked so that the coefficient of thermal expansion of the metal substrate matches the coefficient of thermal expansion of the epitaxial layers of the GaAs-based optoelectronic device.
In other embodiments of the present invention, the original substrate of the GaAs-based optoelectronic device epitaxial wafer provided includes sapphire substrate, Si substrate, GaP substrate, GaSb substrate, InP substrate, SiC substrate, or Ge substrate.
Although the present invention has been described in connection with the preferred embodiments, it is not intended to be limited to the embodiments described herein, and various changes and modifications may be made without departing from the scope of the invention.

Claims (1)

1. A preparation method of a GaAs-based photoelectric device array is characterized by sequentially comprising the following steps of:
step 1), providing a GaAs-based photoelectric device epitaxial wafer, which sequentially comprises an N-type GaAs substrate, an N-type GaAs buffer layer, an InGaP substrate corrosion barrier layer, a highly-doped P-type GaAs back electrode ohmic contact layer, an InGaP channel corrosion barrier layer, a GaAs active layer and an N-type GaAs top electrode ohmic contact layer from bottom to top;
step 2), preparing a plurality of groups of grid-shaped photoresist patterns on the surface of the ohmic contact layer of the N-type GaAs top electrode;
step 3), depositing Ni/Au/Ge/Ni/Au on the multiple groups of grid-shaped photoresist patterns and the surface of the ohmic contact layer of the N-type GaAs top electrode by using an electron beam evaporation technology, and stripping the photoresist by using an organic solvent to obtain multiple groups of grid-shaped electrodes, wherein the top electrode layer comprises multiple groups of top electrodes positioned on the surface of the ohmic contact layer of the N-type GaAs top electrode, and an isolation spacing channel is arranged between every two adjacent top electrodes;
step 4), etching the ohmic contact layer of the N-type GaAs top electrode and a part of the GaAs active layer from the isolation middle channel along the direction vertical to the substrate to form a middle channel groove, and stopping etching until the surface of the middle channel etching barrier layer is etched based on the high selection ratio of etching GaAs and InGaP; adhering the sapphire transition substrate on the surface of the top electrode layer through the adhesion layer;
step 5), removing the N-type GaAs substrate, the N-type GaAs buffer layer and the InGaP substrate corrosion barrier layer by wet etching, wherein an etching solution with a high selection ratio to GaAs and InGaP is selected to etch the N-type GaAs substrate and the N-type GaAs buffer layer; secondly, selecting proper etching solution to etch the InGaP substrate etching barrier layer;
step 6), evaporating a back electrode layer made of Ti/Au on the surface of the back electrode ohmic contact layer by using an electron beam evaporation process;
step 7), evaporating an aluminum underlying metal layer on the surface of the back electrode layer, preparing a separation wall aligned with the channel groove on the surface of the underlying metal layer, and preparing a plurality of metal substrates made of copper through electroplating or evaporation, wherein adjacent metal substrates are separated by the separation wall;
step 8), removing the sapphire transition substrate, the adhesion layer and the isolation wall;
step 9), slicing is carried out along the direction of the channel grooves to obtain a plurality of GaAs-based photoelectric devices;
the channel corrosion barrier layer prevents evaporated metal from entering the channel groove;
in the step 1), the GaAs-based optoelectronic device epitaxial wafer further includes a back field layer located between the channel etching blocking layer and the GaAs active layer, and a window layer located between the GaAs active layer and the top electrode ohmic contact layer, where the forbidden bandwidths of the back field layer and the window layer are both greater than the forbidden bandwidth of the GaAs active layer;
wherein, between step 5) and step 6) still include: forming a pattern structure on the surface of the back electrode ohmic contact layer;
wherein, also include between said step 3) and step 4): preparing a dielectric layer on the surface of the top electrode ohmic contact layer in a region which is not covered by the top electrode layer and is not outside the isolation gap; between step 6) and step 7), further comprising: and preparing a dielectric layer on the surface of the back electrode ohmic contact layer in the area which is not covered by the back electrode layer.
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