CN103187265A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN103187265A CN103187265A CN2011104574529A CN201110457452A CN103187265A CN 103187265 A CN103187265 A CN 103187265A CN 2011104574529 A CN2011104574529 A CN 2011104574529A CN 201110457452 A CN201110457452 A CN 201110457452A CN 103187265 A CN103187265 A CN 103187265A
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Abstract
The invention provides a manufacturing method of a semiconductor device. A first etching barrier layer is formed on a substrate, the horizontal cross section of the first etching barrier layer is circle-shaped and matched with the shape of the bottom face of a groove formed in follow-up process, and therefore the thickness of an etching barrier pattern on the edge outside the bottom face of the groove is increased. In the process of etching to form the groove, the outer edge of the bottom face of the formed groove can stop at the first etching barrier layer, therefore the problem that the bottom face is uneven due to the fact that etching removing speed near the edge outside the groove is larger than the etching removing speed in the middle is solved, the substrate below the etching barrier layer is prevented from being damaged by etching, the phenomenon of short circuit of the device due to the fact that a super-thick metal layer enters the semiconductor substrate when the super-thick metal layer is formed in a deposition mode can be avoided, the super-thick metal layer which is good in electric connection characteristic can be formed in the follow-up process, and the performance of the semiconductor device can be improved.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, relate in particular to a kind of have super thick metal layers manufacture method of semiconductor device of (Ultra Thick Metal) of being used to form.
Background technology
Make the field at integrated circuit, super thick metal layers (Ultra Thick Metal) be widely used in size at 90nm in the semiconductor device structure of 65nm, the thickness of super thick metal layers can reach more than the 1000nm.
Fig. 1 to Fig. 2 is the structural representation of a kind of manufacture method of semiconductor device in the prior art, and to shown in Figure 2, the process of making super thick metal layers comprises as Fig. 1: at first form etching barrier layer 20 and interlayer dielectric layer 30 in substrate 10; Then form patterned light blockage layer 40 at interlayer dielectric layer 30, and be mask etching interlayer dielectric layer 30 with this patterned light blockage layer 40, with the groove 50 of formation in order to fill super thick metal layers.Yet, because the degree of depth of this groove 50 is bigger, need carry out long etching to interlayer dielectric layer 30, so a large amount of etch by-products (Polymer) that produces in etching process rests in the groove 50, and accumulate in the zone line of groove 50 bottoms, the etching speed of zone line of groove 50 bottoms has slowed down, make the etching speed in groove 50 bottom margin zones greater than the etching speed of zone line, after the long-time etching, cause the etch thicknesses gap more and more big, cause forming structure as shown in Figure 2, the zone line of groove 50 bottoms does not reach etch thicknesses, and the fringe region of groove 50 bottoms has etched in the substrate 10 of below, because the interface evenness of groove 50 bottoms is relatively poor, form the cavity during the follow-up super thick metal layers that deposition forms in this groove 50 easily, influence the characteristic that is electrically connected of super thick metal interconnecting layer, even cause etching break-through substrate 10, the super thick metal layers deposition of follow-up formation enters in the substrate 10, cause the serious short circuit of device, influence performance of semiconductor device.
In order to address the above problem, prior art adopts the simple method that increases the thickness meeting of etching barrier layer, yet, the thickness that excessively increases etching barrier layer 20 can significantly improve the overall dielectric constant of interlayer dielectric layer 30, and then influence the dielectric properties of semiconductor device, influence the performance of semiconductor device equally.
Summary of the invention
The purpose of this invention is to provide a kind ofly when being formed for filling the groove of super thick metal layers, the control etch rate is poor, improve the bottom surface evenness and keep the manufacture method of the semiconductor device of good dielectric properties.
The invention provides a kind of manufacture method of semiconductor device, may further comprise the steps:
Substrate is provided;
Form first etching barrier layer in described substrate, the horizontal cross-section of described first etching barrier layer is around shape, and is suitable with the bottom shape of the groove of follow-up formation;
Form interlayer dielectric layer at described first etching barrier layer;
Form patterned light blockage layer at described interlayer dielectric layer, the outer edge of the interlayer dielectric layer that described patterned light blockage layer exposes be positioned at described first etching barrier layer directly over;
Be the described interlayer dielectric layer of mask etching with described patterned light blockage layer, form groove, the outer edge of the bottom surface of described groove is positioned on described first etching barrier layer.
Optionally, form the step of first etching barrier layer and form between the step of interlayer dielectric layer in described substrate, also comprise: cover second barrier layer at described first etching barrier layer and substrate.
Optionally, form in described substrate before the step of first etching barrier layer, also comprise: cover second barrier layer in described substrate.
Optionally, the step at described substrate formation first etching barrier layer comprises:
Cover the etching block film in described substrate;
The etching block film of etched portions thickness, form first etching barrier layer and under second barrier layer.
Further, the thickness of described first etching barrier layer be described second etching barrier layer thickness 50%～200%.
Further, the material of described second etching barrier layer is silicon nitride or carbonitride of silicium.
Further, after the step that forms groove, also be included in the step that forms super thick metal layers in the described groove.
Further, the material of described first etching barrier layer is silicon nitride or carbonitride of silicium.
Further, the horizontal cross-section of described first etching barrier layer is annular or " mouth " font.
Further, the width of described first etching barrier layer be described trench bottom surfaces width 5%～20%.
Further, described substrate is to have the Semiconductor substrate of active circuit or metal interconnecting layer.
Than prior art; the manufacture method of semiconductor device of the present invention; by forming first etching barrier layer in described substrate; the horizontal cross-section of described first etching barrier layer is around shape; suitable with the bottom shape of the groove of follow-up formation; thereby the etching at thickening trench bottom surfaces outer edge place stops the thickness of figure; when etching forms groove; the bottom surface outer edge of the groove that forms can stop at this first etching barrier layer; overcome and removed speed because of near the etching groove outer edge and cause the irregular problem in bottom surface greater than middle etching removal speed; and be not etched damage of the substrate of having protected the etching barrier layer below; to prevent when deposition forms super thick metal layers; super thick metal layers enters the semiconductor-based end and causes the device short circuit; be conducive in subsequent technique, can form the good super thick metal layers of the characteristic that is electrically connected, improve the performance of semiconductor device.
Description of drawings
Fig. 1 to Fig. 2 is the structural representation of a kind of manufacture method of semiconductor device in the prior art.
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.
Fig. 4～Fig. 8 is the structural representation of fabrication of semiconductor device in one embodiment of the invention.
Fig. 9～Figure 11 is the structural representation of the manufacture process of semiconductor device in another embodiment of the present invention.
Embodiment
For making content of the present invention clear more understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Core concept of the present invention is; stop figure by forming etching in substrate; described etching stops that figure comprises first etching barrier layer and second etching barrier layer; the horizontal cross-section of first etching barrier layer is around shape; and it is suitable with the bottom shape of groove; thereby the etching at thickening trench bottom surfaces outer edge place stops the thickness of figure; overcome and remove speed because of near the etching groove outer edge and cause the irregular problem in bottom surface greater than middle etching removal speed; the further substrate of the protection etching barrier layer below damage that is not etched; to guarantee in subsequent technique, the forming good super thick metal layers of characteristic that is electrically connected, improve the performance of semiconductor device.
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.The manufacture method of the described semiconductor device of present embodiment may further comprise the steps:
Step S01: substrate is provided;
Step S02: form first etching barrier layer in described substrate, the horizontal cross-section of described first etching barrier layer is around shape, and is suitable with the bottom shape of the groove of follow-up formation;
Step S03: form interlayer dielectric layer at described first etching barrier layer;
Step S04: form patterned light blockage layer at described interlayer dielectric layer, the outer edge of the interlayer dielectric layer that described patterned light blockage layer exposes be positioned at described first etching barrier layer directly over;
Step S05: be the described interlayer dielectric layer of mask etching with described patterned light blockage layer, form groove, the outer edge of the bottom surface of described groove is positioned on described first etching barrier layer.
The step that form groove after, also be included in the step that in described groove form super thick metal layers thereafter.
Fig. 4～Figure 11 is the structural representation in the fabrication of semiconductor device in one embodiment of the invention.Describe the manufacture method of several semiconductor device of the present invention in detail below in conjunction with Fig. 3～Figure 11.
[embodiment one]
In conjunction with Fig. 4 and Fig. 5, in step S01, provide substrate 100, described substrate 100 can also be preceding one deck metal interconnecting layer for having the Semiconductor substrate of active circuit.
Continuation is with reference to figure 4 and Fig. 5, in step S02, at first form the first etching block film (not indicating among the figure) in described substrate 100, utilize photoetching and etching technics, this etching block film of patterning, form first etching barrier layer 201, the horizontal cross-section of described first etching barrier layer 201 is around shape, described first etching barrier layer 201 around formation figure and the bottom shape of the groove of follow-up formation suitable, the shape of the groove that concrete shape forms is as required determined, for example be annular or " mouth " font, as shown in Figure 5, in the present embodiment, be that rectangle is example with the trench bottom surfaces, the horizontal cross-section of described first etching barrier layer 201 is " mouth " font, and the outer edge of the bottom surface of the groove of follow-up formation is positioned at the zone line top of first etching barrier layer 201.In addition, the material of described first etching barrier layer 201 can be silicon nitride or carbonitride of silicium, it is poor that the material of silicon nitride or carbonitride of silicium and the interlayer dielectric layer of follow-up formation can produce bigger etch rate, the material of silicon nitride or carbonitride of silicium has lower dielectric constant simultaneously, keep and form good dielectric properties, other etch stop layer in addition, for example carborundum etc. is also within thought range of the present invention.
Then, cover second barrier layer 202 at described first etching barrier layer 201 and substrate 100; First etching barrier layer, the 201 common etchings of forming of second barrier layer 202 and below thereof stop figure 203.Wherein, the material of described second etching barrier layer 202 can be silicon nitride or carbonitride of silicium, and the material of described second barrier layer 202 and first etching barrier layer 201 can be identical, can also be different, can determine according to technological requirement.
Then, in step S03, form interlayer dielectric layer 300 at described second etching barrier layer 202; The thickness of described interlayer dielectric layer 300 determines that according to the technological requirement of semiconductor device the material of described interlayer dielectric layer can be silicon dioxide or low-k (Low-K) material, and preferable is advanced low-k materials, keeps good dielectric properties.
As shown in Figure 6, in step S04, form patterned light blockage layer 400 at described interlayer dielectric layer 300, described patterned light blockage layer 400 can comprise photoresist and be arranged in the bottom antireflective coating (figure does not indicate) of photoresist below, described bottom antireflective coating is poisoned and raising lithography alignment accuracy in order to prevent photoresist, the outer edge of the pattern that described patterned light blockage layer 400 exposes be positioned at described first etching barrier layer 201 directly over, namely the pattern that exposes of described patterned light blockage layer 400 be positioned at described first etching barrier layer 201 directly over.
As shown in Figure 7, in step S05, be the described interlayer dielectric layer 300 of mask etching with described patterned light blockage layer 400, form groove 500, the outer edge of the bottom surface of described groove 500 is positioned on described first etching barrier layer 201, because in the etching process, the etch rate of groove 500 outer edge region is greater than the etch rate of groove 500 zone lines, stop thickness by forming first etching barrier layer 201 with near the etching the thickening groove 500 bottom surface outward flanges, the etch rate of groove 500 outer edge region that slowed down, thereby make trench bottom surfaces form the evenness good interface, be conducive to the follow-up formation good super thick metal layers of characteristic that is electrically connected.
Wherein, the thickness H of described first etching barrier layer 201
2Thickness H for described second etching barrier layer 202
150%～200%.The described first etching barrier layer W
2Width be described groove W
15%～20% of the width of corresponding sides.The thickness of first etching barrier layer 201 and second etching barrier layer 202 is transferred ratio according to the degree of depth of the groove 500 of reality formation and the exposure rate (being figure percentage) of product, in general be more dark more easy the drilling of groove 500 degree of depth, just need to increase the thickness of first etching barrier layer 201 and second etching barrier layer 202.The first etching barrier layer W
2Width also be require to adjust according to actual process, increasing width can prevent from drilling better, prevents from avoiding the dielectric constant values of the whole interlayer dielectric layer of the excessive influence of area simultaneously.
Thereafter, as shown in Figure 8, after the step that forms groove 500, utilize electroplating technology and chemical mechanical milling tech to form super thick metal layers 600 in groove 500, forming technology is the described content of knowing of those skilled in the art, so repeat no more.Because when etching forms groove 500; break-through is not in substrate 100; thereby protected the substrate 100 of etching barrier layer below; super thick metal layers 600 does not enter in the substrate 100; effectively prevented the device short circuit, and groove 500 bottom surfaces that form are comparatively smooth, reduced the formation of hole (Hole) in the super thick metal layers 600 or projection (Hillock); thereby can in subsequent technique, form the good super thick metal layers of the characteristic that is electrically connected, improve the performance of semiconductor device.
[embodiment two]
In conjunction with Fig. 9～Figure 11, on the basis of embodiment one, in step S02, change the sequencing that first etching barrier layer 202 and second etching barrier layer 202 form; Particularly, in substrate 100, cover second barrier layer 202 earlier at present embodiment, the first etching block film (among the figure indicate) on second etching barrier layer 202 then, utilize photoetching and etching technics, the patterning first etching block film, form first etching barrier layer, 201, the first etching barrier layers 201 and under the common etchings of forming in second barrier layer 202 stop figure 203; In the present embodiment; described first etching barrier layer 201 is positioned on described second etching barrier layer 202; the thickness that the etching at same thickening trench bottom surfaces outer edge place stops; with when etching forms groove 500; overcome and remove speed because of near etching groove 500 outer edges and remove the speed irregular problem in bottom surface therefore greater than middle etching; further 100 damages that are not etched at the bottom of the protecting group, guarantee follow-up in groove 500 the formation good super thick metal layers 600 of characteristic that is electrically connected.In addition, the material of the material of first etching barrier layer 201, shape, thickness and second etching barrier layer 202, shape thickness and substrate 100 are identical with embodiment one in the present embodiment.
[embodiment three]
On the basis of embodiment two, present embodiment passes through the etching block film that at first deposition is thicker (indicating) in step S02, this etching block film of patterning then, thereby form comprise first etching barrier layer 201 and under the etching figure on second barrier layer 202, the structure of formation is identical with Figure 11 structure described in the embodiment two.Particularly; in conjunction with Fig. 9 to Figure 11; at first be formed on and cover the thicker etching block film of one deck in the substrate 100 earlier; utilize the segment thickness of photoetching and etching technics etching block film then; the control etch period; make the etching block film form by first etching barrier layer 201 and under it be second etching barrier layer 202 form stop figure 203; by covering depositing operation in conjunction with etching technics; the etching that forms stops figure 203; the etching that can thicken outer edge place, groove 500 bottom surface equally stops thickness; with when etching forms groove 500; overcome and remove speed because of near etching groove 500 outer edges and remove speed greater than middle etching; avoid the irregular problem in bottom surface, further protected substrate 100 damage that is not etched, thereby guaranteed in groove 500, to form the good super thick metal layers 600 of characteristic that is electrically connected.In addition, the material of the material of first etching barrier layer 201, shape, thickness and second etching barrier layer 202, shape thickness and substrate 100 are identical with embodiment one in the present embodiment.
In sum; than prior art; the manufacture method of semiconductor device of the present invention; by forming first etching barrier layer in described substrate; the horizontal cross-section of described first etching barrier layer is around shape; suitable with the bottom shape of the groove of follow-up formation; thereby the etching at thickening trench bottom surfaces outer edge place stops the thickness of figure; when etching forms groove; the outside, bottom surface of the groove that forms can stop at this first etching barrier layer; overcome and removed speed because of near the etching groove outer edge and cause the irregular problem in bottom surface greater than middle etching removal speed; and be not etched damage of the substrate of having protected the etching barrier layer below; to prevent when deposition forms super thick metal layers; super thick metal layers enters the semiconductor-based end and causes the device short circuit; thereby in subsequent technique, can form the good super thick metal layers of the characteristic that is electrically connected, improve the performance of semiconductor device.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (11)
1. the manufacture method of a semiconductor device is characterized in that, comprise,
Substrate is provided;
Form first etching barrier layer in described substrate, the horizontal cross-section of described first etching barrier layer is around shape, and is suitable with the bottom shape of the groove of follow-up formation;
Form interlayer dielectric layer at described first etching barrier layer;
Form patterned light blockage layer at described interlayer dielectric layer, the outer edge of the interlayer dielectric layer that described patterned light blockage layer exposes be positioned at described first etching barrier layer directly over;
Be the described interlayer dielectric layer of mask etching with described patterned light blockage layer, form groove, the outer edge of the bottom surface of described groove is positioned on described first etching barrier layer.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, form the step of first etching barrier layer and form between the step of interlayer dielectric layer in described substrate, also comprise: cover second barrier layer at described first etching barrier layer and substrate.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, forms in described substrate before the step of first etching barrier layer, also comprises: cover second barrier layer in described substrate.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the step that forms first etching barrier layer in described substrate comprises:
Cover the etching block film in described substrate;
The etching block film of etched portions thickness, form first etching barrier layer and under second barrier layer.
5. as the manufacture method of any described semiconductor device in the claim 2 to 4, it is characterized in that, the thickness of described first etching barrier layer be described second etching barrier layer thickness 50%～200%.
6. as the manufacture method of any described semiconductor device in the claim 2 to 4, it is characterized in that the material of described second etching barrier layer is silicon nitride or carbonitride of silicium.
7. as the manufacture method of any described semiconductor device in the claim 1 to 4, it is characterized in that, after the step that forms groove, also be included in the step that forms super thick metal layers in the described groove.
8. as the manufacture method of any described semiconductor device in the claim 1 to 4, it is characterized in that the material of described first etching barrier layer is silicon nitride or carbonitride of silicium.
9. as the manufacture method of any described semiconductor device in the claim 1 to 4, it is characterized in that the horizontal cross-section of described first etching barrier layer is annular or " mouth " font.
10. as the manufacture method of any described semiconductor device in the claim 1 to 4, it is characterized in that, the width of described first etching barrier layer be described trench bottom surfaces width 5%～20%.
11. the manufacture method as any described semiconductor device in the claim 1 to 4 is characterized in that, described substrate is to have the Semiconductor substrate of active circuit or metal interconnecting layer.
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| CN103187265B CN103187265B (en) | 2016-02-03 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628022A (en) * | 2019-02-28 | 2020-09-04 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
| CN112993740A (en) * | 2019-12-02 | 2021-06-18 | 夏普福山激光株式会社 | Laser device |
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| US6187211B1 (en) * | 1998-12-15 | 2001-02-13 | Xerox Corporation | Method for fabrication of multi-step structures using embedded etch stop layers |
| US20040203226A1 (en) * | 1999-12-15 | 2004-10-14 | Oki Electric Industry Co., Ltd. | Semiconductor device with reduced interconnection capacity |
| US20050090055A1 (en) * | 2003-10-23 | 2005-04-28 | Min-Suk Lee | Method for fabricating semiconductor device with fine patterns |
| CN101587860A (en) * | 2008-05-21 | 2009-11-25 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
| CN102024786A (en) * | 2009-09-09 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device for interconnection process and manufacturing method thereof |
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2011
- 2011-12-31 CN CN201110457452.9A patent/CN103187265B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6187211B1 (en) * | 1998-12-15 | 2001-02-13 | Xerox Corporation | Method for fabrication of multi-step structures using embedded etch stop layers |
| US20040203226A1 (en) * | 1999-12-15 | 2004-10-14 | Oki Electric Industry Co., Ltd. | Semiconductor device with reduced interconnection capacity |
| US20050090055A1 (en) * | 2003-10-23 | 2005-04-28 | Min-Suk Lee | Method for fabricating semiconductor device with fine patterns |
| CN101587860A (en) * | 2008-05-21 | 2009-11-25 | 海力士半导体有限公司 | Method for fabricating semiconductor device |
| CN102024786A (en) * | 2009-09-09 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device for interconnection process and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628022A (en) * | 2019-02-28 | 2020-09-04 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
| CN111628022B (en) * | 2019-02-28 | 2022-07-15 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
| CN112993740A (en) * | 2019-12-02 | 2021-06-18 | 夏普福山激光株式会社 | Laser device |
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