CN103187265B - The manufacture method of semiconductor device - Google Patents
The manufacture method of semiconductor device Download PDFInfo
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- CN103187265B CN103187265B CN201110457452.9A CN201110457452A CN103187265B CN 103187265 B CN103187265 B CN 103187265B CN 201110457452 A CN201110457452 A CN 201110457452A CN 103187265 B CN103187265 B CN 103187265B
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Abstract
The invention provides a kind of manufacture method of semiconductor device, by forming the first etching barrier layer on the substrate, the horizontal cross-section of described first etching barrier layer is around shape, suitable with the bottom shape of the groove of follow-up formation, thus thicken the thickness of the etch stopper figure at trench bottom surfaces outer edge place, when etching formation groove, this the first etching barrier layer can be stopped at outside the bottom surface of the groove formed, overcome because of etch near groove outer edge removal speed be greater than intermediate etch remove speed cause the irregular problem in bottom surface, the damage and the substrate protected below etching barrier layer is not etched, to prevent when depositing formation super thick metal level, super thick metal level enters semiconductor base and causes shorted devices, thus the good super thick metal level of the characteristic that is electrically connected can be formed in subsequent technique, improve the performance of semiconductor device.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, particularly relating to a kind of manufacture method of semiconductor device for the formation of having super thick metal level (UltraThickMetal).
Background technology
In IC manufacturing field, super thick metal level (UltraThickMetal) is widely used in size in the semiconductor device structure of 90nm to 65nm, and the thickness of super thick metal level can reach more than 1000nm.
Fig. 1 to Fig. 2 is the structural representation of the manufacture method of a kind of semiconductor device in prior art, and as shown in Figure 1 to Figure 2, the process making super thick metal level comprises: first on substrate 10 is formed, form etching barrier layer 20 and interlayer dielectric layer 30; Then on interlayer dielectric layer 30, form the photoresist layer 40 of patterning, and be mask etching interlayer dielectric layer 30 with the photoresist layer 40 of this patterning, to form the groove 50 of filling super thick metal level.But, because the degree of depth of this groove 50 is larger, need to etch for a long time interlayer dielectric layer 30, therefore a large amount of etch by-products (Polymer) produced in etching process rests in groove 50, and the zone line be gathered in bottom groove 50, slowed down the etching speed of the zone line bottom groove 50, the etching speed of groove 50 bottom edge region is made to be greater than the etching speed of zone line, after long-time etching, cause etch thicknesses gap more and more large, cause the structure formed as shown in Figure 2, zone line bottom groove 50 does not reach etch thicknesses, and the fringe region bottom groove 50 has etched in the substrate 10 of below, because the interface evenness bottom groove 50 is poor, follow-uply easily form cavity when depositing the super thick metal level of formation in this groove 50, affect the characteristic that is electrically connected of super thick metal interconnecting layer, even cause etching break-through substrate 10, the super thick metal level deposition of follow-up formation enters in substrate 10, cause the short circuit that device is serious, affect performance of semiconductor device.
In order to solve the problem, prior art adopts the simple method increasing the thickness meeting of etching barrier layer, but, the thickness of excessive increase etching barrier layer 20 significantly can improve the overall dielectric constant of interlayer dielectric layer 30, and then affect the dielectric properties of semiconductor device, affect the performance of semiconductor device equally.
Summary of the invention
The object of this invention is to provide a kind of when being formed for filling the groove of super thick metal level, controlling that etch rate is poor, raising bottom surface evenness maintain the manufacture method of the semiconductor device of good dielectric properties.
The invention provides a kind of manufacture method of semiconductor device, comprise the following steps:
Substrate is provided;
Form the first etching barrier layer on the substrate, the horizontal cross-section of described first etching barrier layer is around shape, suitable with the bottom shape of the groove of follow-up formation;
Described first etching barrier layer forms interlayer dielectric layer;
Described interlayer dielectric layer is formed the photoresist layer of patterning, and the outer edge of the interlayer dielectric layer that the photoresist layer of described patterning exposes is positioned at directly over described first etching barrier layer;
With the photoresist layer of described patterning for interlayer dielectric layer described in mask etching, form groove, the outer edge of the bottom surface of described groove is positioned on described first etching barrier layer.
Optionally, formed on the substrate between the step of the first etching barrier layer and the step forming interlayer dielectric layer, also comprise: on described first etching barrier layer and substrate, cover the second barrier layer.
Optionally, before forming the step of the first etching barrier layer on the substrate, also comprise: cover the second barrier layer on the substrate.
Optionally, the step forming the first etching barrier layer on the substrate comprises:
Cover etch stop film on the substrate;
The etch stop film of etched portions thickness, formed the first etching barrier layer and under the second barrier layer.
Further, the thickness of described first etching barrier layer is 50% ~ 200% of the thickness of described second etching barrier layer.
Further, the material of described second etching barrier layer is silicon nitride or carbonitride of silicium.
Further, after the step forming groove, also comprise the step forming super thick metal level in the trench.
Further, the material of described first etching barrier layer is silicon nitride or carbonitride of silicium.
Further, the horizontal cross-section of described first etching barrier layer is annular or " mouth " font.
Further, the width of described first etching barrier layer is 5% ~ 20% of the width of described trench bottom surfaces.
Further, described substrate is Semiconductor substrate or the metal interconnecting layer with active circuit.
Compared to prior art, the manufacture method of semiconductor device of the present invention, by forming the first etching barrier layer on the substrate, the horizontal cross-section of described first etching barrier layer is around shape, suitable with the bottom shape of the groove of follow-up formation, thus thicken the thickness of the etch stopper figure at trench bottom surfaces outer edge place, when etching formation groove, the bottom surface outer edge of the groove formed can stop at this first etching barrier layer, overcome because of etch near groove outer edge removal speed be greater than intermediate etch remove speed cause the irregular problem in bottom surface, the damage and the substrate protected below etching barrier layer is not etched, to prevent when depositing formation super thick metal level, super thick metal level enters semiconductor base and causes shorted devices, be conducive to forming the good super thick metal level of the characteristic that is electrically connected in subsequent technique, improve the performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 to Fig. 2 is the structural representation of the manufacture method of a kind of semiconductor device in prior art.
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.
Fig. 4 ~ Fig. 8 is the structural representation of fabrication of semiconductor device in one embodiment of the invention.
Fig. 9 ~ Figure 11 is the structural representation of the manufacture process of semiconductor device in another embodiment of the present invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Core concept of the present invention is, by forming etch stopper figure in substrate, described etch stopper figure comprises the first etching barrier layer and the second etching barrier layer, the horizontal cross-section of the first etching barrier layer is around shape, and it is suitable with the bottom shape of groove, thus thicken the thickness of the etch stopper figure at trench bottom surfaces outer edge place, overcome because of etch near groove outer edge removal speed be greater than intermediate etch remove speed cause the irregular problem in bottom surface, substrate below further protection etching barrier layer is not etched damage, to ensure to form the good super thick metal level of the characteristic that is electrically connected in subsequent technique, improve the performance of semiconductor device.
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.The manufacture method of semiconductor device described in the present embodiment, comprises the following steps:
Step S01: substrate is provided;
Step S02: form the first etching barrier layer on the substrate, the horizontal cross-section of described first etching barrier layer is around shape, suitable with the bottom shape of the groove of follow-up formation;
Step S03: form interlayer dielectric layer on described first etching barrier layer;
Step S04: the photoresist layer forming patterning on described interlayer dielectric layer, the outer edge of the interlayer dielectric layer that the photoresist layer of described patterning exposes is positioned at directly over described first etching barrier layer;
Step S05: with the photoresist layer of described patterning for interlayer dielectric layer described in mask etching, form groove, the outer edge of the bottom surface of described groove is positioned on described first etching barrier layer.
Thereafter, after the step forming groove, also comprise the step forming super thick metal level in the trench.
Fig. 4 ~ Figure 11 is the structural representation in one embodiment of the invention in fabrication of semiconductor device.The manufacture method of several semiconductor device of the present invention is described in detail below in conjunction with Fig. 3 ~ Figure 11.
[embodiment one]
Composition graphs 4 and Fig. 5, in step S01, provide substrate 100, and described substrate 100 can, for having the Semiconductor substrate of active circuit, can also be front one deck metal interconnecting layer.
Continue with reference to figure 4 and Fig. 5, in step S02, first in described substrate 100, the first etch stop film (not indicating in figure) is formed, utilize photoetching and etching technics, this etch stop film of patterning, form the first etching barrier layer 201, the horizontal cross-section of described first etching barrier layer 201 is around shape, described first etching barrier layer 201 around formation figure and the bottom shape of groove of follow-up formation suitable, the shape of the groove that concrete shape is formed as required is determined, be such as annular or " mouth " font, as shown in Figure 5, in the present embodiment, take trench bottom surfaces as rectangle be example, the horizontal cross-section of described first etching barrier layer 201 is " mouth " font, the outer edge of the bottom surface of the groove of follow-up formation is positioned at above the zone line of the first etching barrier layer 201.In addition, the material of described first etching barrier layer 201 can be silicon nitride or carbonitride of silicium, it is poor that the material of silicon nitride or carbonitride of silicium and the interlayer dielectric layer of follow-up formation can produce larger etch rate, the material of silicon nitride or carbonitride of silicium has lower dielectric constant simultaneously, maintain and form good dielectric properties, in addition other etch stop layer, such as carborundum etc. are also within thought range of the present invention.
Then, described first etching barrier layer 201 and substrate 100 cover the second barrier layer 202; The first etching barrier layer 201 composition etch stopper figure 203 jointly of the second barrier layer 202 and below thereof.Wherein, the material of described second etching barrier layer 202 can be silicon nitride or carbonitride of silicium, and described second barrier layer 202 can be identical with the material of the first etching barrier layer 201, can also be different, can determine according to technological requirement.
Then, in step S03, described second etching barrier layer 202 forms interlayer dielectric layer 300; The thickness of described interlayer dielectric layer 300 is determined according to the technological requirement of semiconductor device, the material of described interlayer dielectric layer can be silicon dioxide or low-k (Low-K) material, be preferably advanced low-k materials, maintain good dielectric properties.
As shown in Figure 6, in step S04, described interlayer dielectric layer 300 is formed the photoresist layer 400 of patterning, the photoresist layer 400 of described patterning can comprise photoresist and be arranged in the bottom antireflective coating (figure does not indicate) below photoresist, described bottom antireflective coating is in order to prevent photoresist poisoning and improve lithography alignment accuracy, the outer edge of the pattern of photoresist layer 400 exposure of described patterning is positioned at directly over described first etching barrier layer 201, namely the pattern that the photoresist layer 400 of described patterning exposes is positioned at directly over described first etching barrier layer 201.
As shown in Figure 7, in step S05, with the photoresist layer 400 of described patterning for interlayer dielectric layer described in mask etching 300, form groove 500, the outer edge of the bottom surface of described groove 500 is positioned on described first etching barrier layer 201, due in etching process, the etch rate of groove 500 outer edge region is greater than the etch rate of groove 500 zone line, by forming the first etching barrier layer 201 to thicken the etch stopper thickness near the outward flange of groove 500 bottom surface, the etch rate of groove 500 outer edge region that slowed down, thus make trench bottom surfaces form the good interface of evenness, be conducive to follow-up formation to be electrically connected the good super thick metal level of characteristic.
Wherein, the thickness H of described first etching barrier layer 201
2for the thickness H of described second etching barrier layer 202
150% ~ 200%.Described first etching barrier layer W
2width be described groove W
15% ~ 20% of the width of corresponding sides.The degree of depth of groove 500 that the thickness of the first etching barrier layer 201 and the second etching barrier layer 202 is formed according to reality and the exposure rate (i.e. figure percentage) of product adjust ratio, in general be that groove 500 degree of depth more easily drills more deeply, just need the thickness of increase by first etching barrier layer 201 and the second etching barrier layer 202.First etching barrier layer W
2width be also according to actual process require adjustment, increase width can prevent from better drilling, prevent the dielectric constant values avoiding the whole interlayer dielectric layer of the excessive impact of area simultaneously.
Thereafter, as shown in Figure 8, after the step forming groove 500, utilize electroplating technology and chemical mechanical milling tech to form super thick metal level 600 in groove 500, the content of formation process for knowing described in those skilled in the art, therefore repeat no more.During due to etching formation groove 500; non-break-through is in substrate 100; thus the substrate 100 protected below etching barrier layer; super thick metal level 600 does not enter in substrate 100; effectively prevent shorted devices, and groove 500 bottom surface formed is comparatively smooth, decreases the formation of super thick metal level 600 Hole (Hole) or protruding (Hillock); thus the good super thick metal level of the characteristic that is electrically connected can be formed in subsequent technique, improve the performance of semiconductor device.
[embodiment two]
Composition graphs 9 ~ Figure 11, on the basis of embodiment one, in step S02, changes the sequencing of the first etching barrier layer 202 and the formation of the second etching barrier layer 202; Particularly, in substrate 100, the second barrier layer 202 is first covered at the present embodiment, then first etch stop film (not indicating in figure) on the second etching barrier layer 202, utilize photoetching and etching technics, patterning first etch stop film, formed the first etching barrier layer 201, first etching barrier layer 201 and under the second barrier layer 202 jointly composition etch stopper figure 203; In the present embodiment; described first etching barrier layer 201 is positioned on described second etching barrier layer 202; the thickness of the etch stopper at same thickening trench bottom surfaces outer edge place; with when etching formation groove 500; overcome and be greater than the irregular problem in intermediate etch removal speed bottom surface therefore because etching removal speed near groove 500 outer edge; at the bottom of further protecting group, 100 are not etched damage, ensure in groove 500, to form the good super thick metal level 600 of the characteristic that is electrically connected follow-up.In addition, in the present embodiment, the material of the material of the first etching barrier layer 201, shape, thickness and the second etching barrier layer 202, shape thicknesses and substrate 100 are identical with embodiment one.
[embodiment three]
On the basis of embodiment two, the present embodiment passes through first to deposit thicker etch stop film (sign) in step S02, then this etch stop film of patterning, thus formed comprise the first etching barrier layer 201 and under the etched features on the second barrier layer 202, the structure of formation is identical with Figure 11 structure described in embodiment two.Particularly, composition graphs 9 to Figure 11, first be formed in substrate 100 and first cover the thicker etch stop film of one deck, then the segment thickness of photoetching and etching technics etch stop film is utilized, control etch period, make etch stop film be formed by the first etching barrier layer 201 and be the stop figure 203 that the second etching barrier layer 202 forms under it, by covering depositing operation in conjunction with etching technics, the etch stopper figure 203 formed, the etch stopper thickness at outer edge place, groove 500 bottom surface can be thickeied equally, with when etching formation groove 500, overcome and be greater than intermediate etch removal speed because etching removal speed near groove 500 outer edge, avoid the irregular problem in bottom surface, protect substrate 100 further not to be etched damage, thus ensure in groove 500, form the good super thick metal level 600 of the characteristic that is electrically connected.In addition, in the present embodiment, the material of the material of the first etching barrier layer 201, shape, thickness and the second etching barrier layer 202, shape thicknesses and substrate 100 are identical with embodiment one.
In sum, compared to prior art, the manufacture method of semiconductor device of the present invention, by forming the first etching barrier layer on the substrate, the horizontal cross-section of described first etching barrier layer is around shape, suitable with the bottom shape of the groove of follow-up formation, thus thicken the thickness of the etch stopper figure at trench bottom surfaces outer edge place, when etching formation groove, this the first etching barrier layer can be stopped at outside the bottom surface of the groove formed, overcome because of etch near groove outer edge removal speed be greater than intermediate etch remove speed cause the irregular problem in bottom surface, the damage and the substrate protected below etching barrier layer is not etched, to prevent when depositing formation super thick metal level, super thick metal level enters semiconductor base and causes shorted devices, thus the good super thick metal level of the characteristic that is electrically connected can be formed in subsequent technique, improve the performance of semiconductor device.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (9)
1. a manufacture method for semiconductor device, is characterized in that, comprises,
Substrate is provided;
Form the first etching barrier layer on the substrate, the horizontal cross-section of described first etching barrier layer is around shape, suitable with the bottom shape of the groove of follow-up formation;
Described first etching barrier layer forms interlayer dielectric layer;
Described interlayer dielectric layer is formed the photoresist layer of patterning, and the outer edge of the interlayer dielectric layer that the photoresist layer of described patterning exposes is positioned at directly over described first etching barrier layer;
With the photoresist layer of described patterning for interlayer dielectric layer described in mask etching, form groove;
Wherein, formed between the step of the first etching barrier layer and the step forming interlayer dielectric layer on the substrate, also comprise: on described first etching barrier layer and substrate, cover the second barrier layer, the outer edge of the bottom surface of the described groove of formation is positioned on described first etching barrier layer; Or
Before forming the step of the first etching barrier layer on the substrate, also comprise: cover the second barrier layer on the substrate, under the outer edge of the bottom surface of the described groove of formation is positioned at described first etching barrier layer.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, when described first barrier layer is positioned on described second barrier layer, the step forming the first etching barrier layer on the substrate comprises:
Cover etch stop film on the substrate;
The etch stop film of etched portions thickness, formed the first etching barrier layer and under the second barrier layer.
3. as the manufacture method of the semiconductor device in claim 1 to 2 as described in any one, it is characterized in that, the thickness of described first etching barrier layer is 50% ~ 200% of the thickness of described second etching barrier layer.
4. as the manufacture method of the semiconductor device in claim 1 to 2 as described in any one, it is characterized in that, the material of described second etching barrier layer is silicon nitride or carbonitride of silicium.
5. as the manufacture method of the semiconductor device in claim 1 to 2 as described in any one, it is characterized in that, after the step forming groove, also comprise the step forming super thick metal level in the trench.
6. as the manufacture method of the semiconductor device in claim 1 to 2 as described in any one, it is characterized in that, the material of described first etching barrier layer is silicon nitride or carbonitride of silicium.
7. as the manufacture method of the semiconductor device in claim 1 to 2 as described in any one, it is characterized in that, the horizontal cross-section of described first etching barrier layer is annular or " mouth " font.
8. as the manufacture method of the semiconductor device in claim 1 to 2 as described in any one, it is characterized in that, the width of described first etching barrier layer is 5% ~ 20% of the width of described trench bottom surfaces.
9. as the manufacture method of the semiconductor device in claim 1 to 2 as described in any one, it is characterized in that, described substrate is Semiconductor substrate or the metal interconnecting layer with active circuit.
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| CN111628022B (en) * | 2019-02-28 | 2022-07-15 | 中国科学院物理研究所 | GaAs-based photoelectric device and preparation method of array thereof |
| US10992103B1 (en) * | 2019-12-02 | 2021-04-27 | Sharp Fukuyama Laser Co., Ltd. | Laser device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6187211B1 (en) * | 1998-12-15 | 2001-02-13 | Xerox Corporation | Method for fabrication of multi-step structures using embedded etch stop layers |
| CN102024786A (en) * | 2009-09-09 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device for interconnection process and manufacturing method thereof |
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| JP3457277B2 (en) * | 1999-12-15 | 2003-10-14 | 沖電気工業株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| TWI250558B (en) * | 2003-10-23 | 2006-03-01 | Hynix Semiconductor Inc | Method for fabricating semiconductor device with fine patterns |
| KR100948078B1 (en) * | 2008-05-21 | 2010-03-16 | 주식회사 하이닉스반도체 | Method for manufcturing semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6187211B1 (en) * | 1998-12-15 | 2001-02-13 | Xerox Corporation | Method for fabrication of multi-step structures using embedded etch stop layers |
| CN102024786A (en) * | 2009-09-09 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device for interconnection process and manufacturing method thereof |
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