CN106783803B - A kind of method and semiconductor structure reducing the loss of photo-etching mark figure - Google Patents
A kind of method and semiconductor structure reducing the loss of photo-etching mark figure Download PDFInfo
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- CN106783803B CN106783803B CN201611082385.6A CN201611082385A CN106783803B CN 106783803 B CN106783803 B CN 106783803B CN 201611082385 A CN201611082385 A CN 201611082385A CN 106783803 B CN106783803 B CN 106783803B
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000001259 photo etching Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 8
- 238000001465 metallisation Methods 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Engineering & Computer Science (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention is more particularly directed to the methods and semiconductor structure of a kind of reduction photo-etching mark figure loss.Method is the following steps are included: step 1, depositional control grid layer on a semiconductor substrate；Step 2, the predeterminated position of the control grid layer is performed etching until exposing the semiconductor substrate, forms at least one protruding figure；Step 3, the metallization medium layer on the outside of the upper surface of the protruding figure and protruding figure；Step 4, chemical mechanical planarization is carried out to the upper surface of the dielectric layer, until exposing the upper surface of the protruding figure.Protruding figure can be made to become smaller with dielectric layer interface product by means of the present invention, to reduce the loss in the different caused photo-etching mark figure of rate of Chemical Mechanical Polishing (CMP) dielectric layer and protruding figure.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, in particular to a kind of side for reducing the loss of photo-etching mark figure
Method and semiconductor structure.
Background technique
Semiconductor technology be just continued towards reduce apparent size direction develop, be persistently contracted to 65 nanometers, 45 nanometers very
To smaller.It is smaller and smaller along with the development line width of semiconductor processing technology, the error and litho pattern of litho pattern line width
Defect is also more and more obvious the electrical influence in chip manufacturing proces.How litho pattern is reduced during photoetching to lack
Falling into is the problem of technologist has to take into account that.There are many Producing reason of litho pattern defect, such as resistdefects, photoetching
The exception of equipment is likely to lead to litho pattern defect.Wherein the exception of photo-etching mark figure is exactly that lithographic equipment is caused to generate
One of the reason of litho pattern defect, therefore the photoetching telltale mark graphics request to manufacture small apparent size is also increasingly
It is high.The serious lithographic equipment that will lead to of photo-etching mark pattern lacks can not identify that unit exception is alarmed.Photo-etching mark pattern lacks
The lithographic accuracy that also will affect lithographic equipment simultaneously causes the electrical of chip to generate exception, influences the yield of chip.
Prior art is first to form control gate on a semiconductor substrate, and control gate is made of polysilicon and silicon nitride, is passed through
Control gate intermediate surface is etched, the figure of intermediate recess is formed, is grown later on the control gate surface with intermediate recess figure
Polysilicon filling, finally by the surface of CMP (i.e. chemical-mechanical planarization) polysilicon to control grid layer.Due to control grid layer table
Plane materiel material is silicon nitride, and wherein the Mohs' hardness of silicon nitride is 9, and the Mohs' hardness of polysilicon is 7, and hardness is much larger than polycrystalline
Silicon, during CMP, the Mohs' hardness difference of the two is larger, and polishing speed is different, and polysilicon is caused to connect with silicon nitride surface
The local photo-etching mark figure loss of touching is larger, influences the accuracy of On-line Product monitoring.
Summary of the invention
The present invention provides the methods and semiconductor structure of a kind of reduction photo-etching mark figure loss, solve skill described above
Art problem.
The technical scheme to solve the above technical problems is that a kind of method for reducing the loss of photo-etching mark figure,
The following steps are included:
Step 1, depositional control grid layer on a semiconductor substrate；
Step 2, the predeterminated position of the control grid layer is performed etching until exposing the semiconductor substrate, is formed at least
One protruding figure；
Step 3, the metallization medium layer on the outside of the protruding figure upper surface and protruding figure；
Step 4, chemical mechanical planarization is carried out to the upper surface of the dielectric layer, until exposing the protruding figure
Upper surface.
The beneficial effects of the present invention are: technical solution of the present invention by changing lithography layout, will etch in control grid layer
Between region be changed to the fringe region of etching control grid layer, i.e., compared with the prior art, the present invention to the etch areas of control grid layer compared with
Greatly, the protruding figure width of formation it is smaller and meanwhile deposition dielectric layer area it is also larger, thus make protruding figure upper surface and be situated between
Matter layer contact area becomes smaller, and reduces the different caused light of CMP rate in CMP process dielectric layer Yu protruding figure upper surface
The loss of marking figure.
Based on the above technical solution, the present invention can also be improved as follows.
Further, in step 2, at least one described protruding figure is formed using dry etching method, it is described at least one
Protruding figure combines to form photo-etching mark figure.
Beneficial effect using above-mentioned further scheme is: the pattern precision that dry etching obtains is high, is not in wet process
The side corrosion that corrosion generates, ensure that the integrality of protruding figure.
Further, the protruding figure is rectangular-shape protruding figure.
Further, the control grid layer is multilayered structure, is followed successively by polysilicon layer and silicon nitride layer from bottom to top, described more
Crystal silicon layer deposits on a semiconductor substrate.
Further, the width range of the protruding figure is 90nm~150nm, and the altitude range of the protruding figure is
200nm~300nm.
Further, in step 1, the polysilicon layer and silicon nitride layer are deposited using low-pressure chemical vapor deposition method.
Beneficial effect using above-mentioned further scheme is: using low-pressure chemical vapor deposition method, i.e. LPCVD method is raw
Long polysilicon layer uniformity is good, and step coverage is good, at low cost, is widely used in IC chip grid layer.LPCVD is raw
Long silicon nitride density is high, is not easy to be corroded by hydrofluoric acid, is widely used in the hard mask layer of ic core blade technolgy, shallow ridges
The CMP stop layer of isolation.Meanwhile in this further technical solution, since top layer's material of protruding figure is silicon nitride layer, because
This silicon nitride layer becomes smaller with dielectric layer interface product, to reduce in Chemical Mechanical Polishing (CMP) dielectric layer and silicon nitride layer
Rate it is different caused by photo-etching mark figure loss, while improving the uniformity of CMP.
Further, the dielectric layer is polysilicon layer.
Further, in step 3, the dielectric layer is deposited using low-pressure chemical vapor deposition method.
Beneficial effect using above-mentioned further scheme is: the polysilicon layer uniformity of LPCVD growth is good, at low cost, extensively
It is general to be applied to IC chip ohmic contact layer or interconnection line layer.
In order to solve technical problem of the invention, a kind of semiconductor structure, including semiconductor substrate and utilization are additionally provided
At least one described protruding figure that the method for the reduction photo-etching mark figure loss is formed on a semiconductor substrate, it is described
Dielectric layer is deposited on the outside of protruding figure.
Further, the protruding figure is rectangular-shape protruding figure, the width range of the protruding figure be 90nm~
150nm, the altitude range of the protruding figure are 200nm~300nm.
Beneficial effect using above-mentioned further scheme is: the protruding figure that further technical solution of the present invention is formed is wide
It is larger to spend smaller while deposition dielectric layer area, so that protruding figure upper surface be made to become smaller with dielectric layer interface product, reduces
The loss of the different caused photo-etching mark figure of CMP rate in CMP process dielectric layer Yu protruding figure upper surface.
Detailed description of the invention
Fig. 1 is a kind of flow diagram for the method for reducing the loss of photo-etching mark figure of the embodiment of the present invention；
Fig. 2 is the diagrammatic cross-section of the control grid layer grown in semiconductor substrate in Fig. 1 embodiment；
Fig. 3 is the diagrammatic cross-section that semiconductor substrate forms protruding figure in Fig. 1 embodiment；
Fig. 4 is the diagrammatic cross-section of the dielectric layer grown in Fig. 1 embodiment；
Fig. 5 is the diagrammatic cross-section that photo-etching mark figure is formed in Fig. 1 embodiment.
In attached drawing, parts list represented by the reference numerals are as follows:
1, semiconductor substrate, 2, polysilicon layer, 3 silicon nitride layers, 4, protruding figure, 5, dielectric layer, 6, photo-etching mark figure.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
As shown in Figure 1, a kind of method flow schematic diagram for reducing the loss of photo-etching mark figure of the embodiment of the present invention, including with
Lower step:
Step 1, depositional control grid layer on a semiconductor substrate；
Step 2, the predeterminated position of the control grid layer is performed etching until exposing the semiconductor substrate, is formed at least
One protruding figure；
Step 3, the metallization medium layer on the outside of the protruding figure upper surface and protruding figure；
Step 4, chemical mechanical planarization is carried out to the upper surface of the dielectric layer, until exposing the protruding figure
Upper surface.
The embodiment of the present invention will etch control grid layer intermediate region and be changed to etching control grid layer by changing lithography layout
Fringe region, i.e., compared with the prior art, the present invention are larger to the etch areas of control grid layer, and the protruding figure width of formation is smaller
The dielectric layer area of deposition is also larger simultaneously, to make protruding figure upper surface become smaller with dielectric layer interface product, to reduce
The loss of the different caused photo-etching mark figure of CMP rate in CMP process dielectric layer Yu protruding figure upper surface.
Preferably, in the step 2 of one embodiment of the invention, the control grid layer be multilayered structure, from bottom to top according to
Secondary is polysilicon layer 2 and silicon nitride layer 3, and the polysilicon layer 2 deposits on semiconductor substrate 1, as shown in Figure 2.Specifically, first
First in the semiconductor substrate 1, with SiH4 (i.e. silane) for raw material, the growing polycrystalline silicon layer 2 in LPCVD (i.e.) equipment, it
Afterwards the upper surface of polysilicon layer 2 with SiH2Cl2 (i.e. dichlorosilane) and NH3 (i.e. ammonia) be raw material, in LPCVD equipment
Grown silicon nitride layer 3, to form the control grid layer including silicon nitride layer 3 and polysilicon layer 2.Using low-pressure chemical vapor deposition
Polysilicon layer uniformity it is good, step coverage is good, at low cost, is widely used in IC chip grid layer, silicon nitride is close
Degree is high, is not easy to be corroded by hydrofluoric acid, is widely used in the hard mask layer of ic core blade technolgy, the CMP of shallow isolating trough stops
Only layer.
Preferably, in one embodiment of the invention, dry etching method is used in step 2, inductively it is equal from
Daughter cavity etching control grid layer fringe region forms at least one described protruding figure 4, described 4 groups of at least one protruding figure
Conjunction forms photo-etching mark figure, and the protruding figure 4 is rectangular-shape protruding figure, as shown in Figure 3.Specifically, the dry method
Etching uses etching gas for containing fluorine-based gas, such as CF4 (i.e. carbon tetrafluoride), CHF3 (i.e. trifluoro hydrogen carbon), use is fluorine-based
As etching gas, there is faster etch rate for polysilicon and silicon nitride.
In a preferred embodiment, the width range of the rectangular-shape protruding figure is 90nm~150nm, such as
100nm, 120nm or 130nm etc., the altitude range of the rectangular-shape protruding figure are 200nm~300nm, such as
220nm, 250nm or 270nm etc., larger to the etch areas of control grid layer in this preferred embodiment, the protrusion figure of formation
Shape width it is smaller and meanwhile deposition dielectric layer area it is also larger, thus make protruding figure upper surface and dielectric layer interface product become
It is small, to reduce the different caused photo-etching mark figure of CMP rate in CMP process dielectric layer Yu protruding figure upper surface
Loss.
Preferably, in one embodiment of the invention, in the upper surface of the protruding figure 4 and protruding figure 4
Outside metallization medium layer 5, as shown in figure 4, the dielectric layer 5 is polysilicon layer in the present embodiment.Specific processing step are as follows:
It using SiH4 as raw material, grows in LPCVD equipment, is deposited in the upper surface of the protruding figure 4 and the outside of protruding figure 4
Dielectric layer 5, the polysilicon layer are applied to IC chip ohmic contact layer or interconnection line articulamentum.Then to the medium
The upper surface of layer 5 carries out chemical mechanical planarization, until exposing the upper surface of the protruding figure 4, forms chemical machinery
Photo-etching mark figure 6 after planarization, as shown in Figure 5.
The embodiments of the present invention also provide a kind of semiconductor structures, including semiconductor substrate 1 and utilize the reduction
At least one described protruding figure 4 that the method for photo-etching mark figure loss is formed on semiconductor substrate 1, the protruding figure
4 outside is deposited with dielectric layer, as shown in Figure 5.In the present embodiment, the protruding figure 4 is multilayered structure, from bottom to top successively
For polysilicon layer and silicon nitride layer, on semiconductor substrate 1, while the dielectric layer 5 is polysilicon to the polysilicon layer
Layer.In a preferred embodiment, the protruding figure is rectangular-shape protruding figure, the width of rectangular-shape protruding figure
Range is 90nm~150nm, such as 100nm, 120nm or 130nm etc., and the altitude range of the protruding figure is 200nm
~300nm, such as 220nm, 250nm or 270nm etc..
Technical solution of the present invention is changed to etching control gate by changing lithography layout, by etching control grid layer intermediate region
The fringe region of layer, i.e., compared with the prior art, the present invention is larger to the etch areas of control grid layer, the protruding figure width of formation
Smaller while deposition dielectric layer area is also larger, so that protruding figure upper surface is made to become smaller with dielectric layer interface product, thus
Reduce the loss of the different caused photo-etching mark figure of CMP rate in CMP process dielectric layer Yu protruding figure upper surface.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of method for reducing the loss of photo-etching mark figure, which comprises the following steps:
Step 1, depositional control grid layer on a semiconductor substrate；
Step 2, the predeterminated position of the control grid layer is performed etching until exposing the semiconductor substrate, forms at least one
Protruding figure；
Step 3, the metallization medium layer on the outside of the protruding figure upper surface and protruding figure；
Step 4, chemical mechanical planarization is carried out to the upper surface of the dielectric layer, until exposing the upper of the protruding figure
Surface.
2. a kind of method for reducing the loss of photo-etching mark figure according to claim 1, which is characterized in that in step 2, adopt
At least one described protruding figure is formed with dry etching method.
3. a kind of method for reducing the loss of photo-etching mark figure according to claim 2, which is characterized in that the protrusion figure
Shape is rectangular-shape protruding figure.
4. the method for any a kind of reduction photo-etching mark figure loss according to claim 1~3, which is characterized in that institute
Stating control grid layer is multilayered structure, is followed successively by polysilicon layer and silicon nitride layer from bottom to top, the polysilicon layer is partly being led
In body substrate.
5. a kind of method for reducing the loss of photo-etching mark figure according to claim 4, which is characterized in that the protrusion figure
The width range of shape is 90nm~150nm, and the altitude range of the protruding figure is 200nm~300nm.
6. a kind of method for reducing the loss of photo-etching mark figure according to claim 5, which is characterized in that in step 1, adopt
The polysilicon layer and silicon nitride layer are deposited with low-pressure chemical vapor deposition method.
7. a kind of method for reducing the loss of photo-etching mark figure according to claim 6, which is characterized in that the dielectric layer
For polysilicon layer.
8. a kind of method for reducing the loss of photo-etching mark figure according to claim 7, which is characterized in that in step 3, adopt
The dielectric layer is deposited with low-pressure chemical vapor deposition method.
9. a kind of semiconductor structure, which is characterized in that subtract including semiconductor substrate and using claim 1~8 is any described
At least one described protruding figure that the method for few photo-etching mark figure loss is formed on a semiconductor substrate, the protruding figure
Outside be deposited with dielectric layer.
10. semiconductor structure according to claim 9, which is characterized in that the protruding figure is rectangular-shape protrusion figure
Shape, the width range of the protruding figure are 90nm~150nm, and the altitude range of the protruding figure is 200nm~300nm.
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| CN105845564A (en) * | 2016-05-25 | 2016-08-10 | 上海华力微电子有限公司 | Photoetching and etching method for preventing shaped wafer surface from etching damage |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4439935B2 (en) * | 2004-02-02 | 2010-03-24 | Ｏｋｉセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
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- 2016-11-30 CN CN201611082385.6A patent/CN106783803B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10284590A (en) * | 1997-04-03 | 1998-10-23 | Nippon Steel Corp | Semiconductor device and fabrication thereof |
| JP2001307999A (en) * | 2000-04-27 | 2001-11-02 | Oki Electric Ind Co Ltd | Structure of alignment mark and manufacturing method thereof |
| CN102394234A (en) * | 2011-11-24 | 2012-03-28 | 上海宏力半导体制造有限公司 | Alignment mark manufacturing method used for exposure technology |
| CN103824772A (en) * | 2012-11-19 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Method for improving rear-end photo-etching registration mark morphology |
| CN104347346A (en) * | 2013-08-05 | 2015-02-11 | 上海华虹宏力半导体制造有限公司 | Method for flattening deep grooves with different structures |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |