CN100524691C - Method for etching suspending type etch blocking layer contact hole in embedded flash memory device - Google Patents
Method for etching suspending type etch blocking layer contact hole in embedded flash memory device Download PDFInfo
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- CN100524691C CN100524691C CNB2006101195676A CN200610119567A CN100524691C CN 100524691 C CN100524691 C CN 100524691C CN B2006101195676 A CNB2006101195676 A CN B2006101195676A CN 200610119567 A CN200610119567 A CN 200610119567A CN 100524691 C CN100524691 C CN 100524691C
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Abstract
The invention discloses an etching method for contact holes of a suspended type etching barrier layer of an embedded flash memory device and comprises the following steps: the first step is the etching of top silicon oxy-nitride; the second step is the fast main etching of an oxide film; the third step is the slow main etching of the oxide film: in the step, the selectivity-ratio of silicon oxide to silicon nitride is bigger than 20:1, while the etching rate is relatively slower; the fourth step is to remove polymers which are produced in the previous three steps and are left at bottom parts of the contact holes; the fifth step is to remove the suspended type etching barrier layer of the nitride silicon; the sixth step is the etching of the oxide film at the bottom part. The invention solves the problem of excessive loss of metal contact silicide on the top part of a poly gate due to no etching barrier layer; at the same time, the invention can effectively avoid excessive etching and communication of the poly gate and an isolated edge of a shallow groove caused by deviation of exposing positions, thus the loss of electric leakage of the device can be reduced.
Description
Technical field
The present invention relates to a kind of IC semiconductor method of manufacturing technology, relate in particular to the lithographic method of floated etching barrier layer contact hole in a kind of embedded flash memory device.
Background technology
In embedded flash memory device radio-frequency devices manufacturing process, contact hole (Contact) need be made, in the medium (PMD) before metal for providing the electricity passage between active area and the ground floor metal level.
As shown in Figure 1, the manufacture craft of existing contact hole is: after finishing the Metal Contact of active area (silicide) technology, according to this deposit as metal before silica (APM), silicon nitride (SiN), boron-phosphorosilicate glass (BPSG), atmospheric pressure oxidation silicon (TEOS) and the top silicon oxynitride (SiON, i.e. DARC) of medium.Be coated with photoresist (PR) then, mask exposure is made figure, carry out dry plasma etch at last.For all device technologies, contact hole need drop on polycrystalline grid and the active area simultaneously.Owing to have difference in height between the two, the contact hole of active area is darker.
Problem common in the embedded flash memory device contact hole etching is:
1 compares with the contact hole on the polycrystalline grid, and it is darker that the active area through hole needs etching to get.When considering before each layer metal dielectric deposition, the varied in thickness and the silicon chip inner evenness of each film forming captain film are constantly accumulated, the drift of the etch rate of contact hole etching machine own and the variation of inner evenness simultaneously, open in order to guarantee that active through hole is fully carved, and can not cause circuit breaker, this just requires to increase enough oxide-film over etchings.If but do not have etching barrier layer, a large amount of over etchings can cause the Metal Contact silicide (silicide) at polycrystalline grid top by a large amount of losses, extreme case can all etch away the metal silicide of these low contact resistances, thereby cause contact resistance to become big, influence the electric property of the RC (contact hole resistance) of device, as shown in Figure 2, owing to there is not etching barrier layer, over etching causes the Metal Contact silicide at polycrystalline grid top and active area excessive loss to be arranged all, especially at polycrystalline grid top.Simultaneously, because device size constantly dwindles the raising with integrated level, the alignment precision standard setting of many graph exposures gets very little.In actual production; often have the exposure position skew; at this moment can down continue etching along polycrystalline grid and shallow-trench isolation edge during contact hole etching; thereby cause the serious electric leakage effect of device; as shown in Figure 3; owing to the exposure position skew is arranged and lacks etching barrier layer, can down carve logical a lot along polycrystalline grid and shallow-trench isolation edge during contact hole etching.So when adding etching barrier layer, also need the ratio of accurate Calculation over etching, the control etch period.
2, on the other hand, embedded flash memory device is compared with other logical devices, and it is relatively more responsive that silicon nitride is done etching barrier layer.Because silicon nitride has certain circle ability of catching, decide to the charge carrier of active area, and flush memory device is more responsive to this.So in order not influence the erasable speed and the performance of device, can not be directly with silicon nitride deposition in surfaces of active regions, and need in its lower section deposit one deck silica in advance, promptly be so-called floated etching barrier layer.Therefore, also need the silica of etching bottom after the intact silicon nitride barrier of etching, this just makes that the etching technics of contact hole is more complicated.
Summary of the invention
The technical problem to be solved in the present invention provides the lithographic method of floated etching barrier layer contact hole in a kind of embedded flash memory device, the polycrystalline grid top that solution brings because there not being etching barrier layer and the Metal Contact silicide excessive loss of active area.
For solving the problems of the technologies described above, the invention provides the lithographic method of floated etching barrier layer contact hole in a kind of embedded flash memory device, comprise the steps:
The first step: the etching of top layer silicon oxynitride;
Second the step: the quick etching of oxide-film main etching: the employing etch rate be the 7500-7800 dust/minute, silica is 10:1-13:1 to the selection ratio of silicon nitride, the accurate Calculation etch period is controlled this second step 1000-1200 dust on floated etching barrier layer and is stopped;
The 3rd step: the etching at a slow speed of oxide-film main etching: the 3rd step silica to the selection of silicon nitride than 20:1, etch rate be the 5200-5400 dust/minute;
The 4th step: etching is removed the polymer that residues in the contact hole bottom that is brought by first three step etching;
The 5th step: etching is removed floated silicon nitride etch barrier layer;
The 6th step: the bottom as metal before the silicon oxide layer etching of medium.
The major parameter of first step etching is: pressure 30-90 millitorr; Go up or lower electrode power: 800-1200 watt; Argon gas 150-250sccm; Fluoroform 15-25sccm; Oxygen 5-25sccm; Backside helium pressure: middle part 4-12 holder, edge 10-20 holder.
The major parameter of the second step etching is: pressure 30-90 millitorr; Upper electrode power: 1500-2400 watt, lower electrode power: 800-1600 watt; Argon gas 500-1000sccm; Octafluoro five carbon 5-15sccm; Oxygen 8-25sccm; Backside helium pressure: middle part 4-12 holder, edge 10-20 holder.
The major parameter of the 3rd step etching is: pressure 30-90 millitorr; Upper electrode power: 1500-2400 watt, lower electrode power: 800-1600 watt; Argon gas 500-1000sccm; Octafluoro five carbon 6-20sccm; Oxygen 8-20sccm; Backside helium pressure: middle part 4-12 holder, limit 10-20 holder.Can append 50% over etching in the 3rd step.
The major parameter of the 4th step etching is: pressure 15-35 millitorr; Upper electrode power: 700-1400 watt, lower electrode power: 100-300 watt; Argon gas 100-300sccm; Oxygen 10-30sccm; Backside helium pressure: middle part 4-12 holder, edge 10-30 holder.
The major parameter of the 5th step etching is: pressure 30-50 millitorr; Upper electrode power: 700-1500 watt, lower electrode power: 100-300 watt; Argon gas 100-300sccm; Fluoroform 8-25sccm; Oxygen 10-30sccm; Backside helium pressure: middle part 4-15 holder, edge 10-30 holder.
The 6th step adopted and identical condition of second step: keep etch rate be the 7500-7800 dust/minute, silica to the selection of silicon nitride than being 10:1-13:1.The major parameter of the 6th step etching is: pressure 30-80 millitorr; Upper electrode power: 1500-2500 watt, lower electrode power: 800-1800 watt; Argon gas 500-1000sccm; Octafluoro five carbon 5-15sccm; Oxygen 8-25sccm; Backside helium pressure: middle part 4-15 holder, edge 10-30 holder.
The present invention has following beneficial effect: when the 3rd goes on foot the soft landing of oxide-film main etching, because oxide-film is to the high selectivity (〉 20:1 of nitride film), can guarantee oxide-film is fully etched away, and be parked on the nitride film; Even and the silicon nitride at polycrystalline grid top also loses seldom, silicon nitride thickness is close on the fundamental sum active area, can guarantee like this after removing residual silicon nitride and bottom silica subsequently, and the loss of Metal Contact silicide can be fewer.When the 6th goes on foot the bottom oxide film etching, because thinner thickness, so even add 50% over etching, it is fewer that etch period also can be controlled.Help reducing in a large number the degree of depth that polycrystalline grid and shallow-trench isolation edge are inscribed like this, thereby reduce the leakage current loss of device.On the basis that guarantees enough process windows, adopt the inventive method, the loss of the Metal Contact silicide of polycrystalline grid top and active area significantly reduces, and wherein, polycrystalline grid top drops to 60 dusts from original polycrystalline grid top 270 dusts; Active area drops to＜50 dusts from 200 dusts, has significantly reduced the RC of device.Adopt the inventive method, because the exposure position skew, wear the degree of depth and significantly reduce the quarter at polycrystalline grid and shallow-trench isolation edge, and wherein, polycrystalline grid edge is carved the degree of depth of wearing and significantly is reduced to 400 dusts from 2400 dusts; The shallow-trench isolation edge is carved the degree of depth of wearing and is reduced to＜200 dusts from 1000 dusts, thereby has reduced the leakage loss of device.
Description of drawings
Fig. 1 is existing structural representation with before-metal medium layer of contact hole;
Fig. 2 adopts existing lithographic method to cause the schematic diagram of Metal Contact silicide loss;
Fig. 3 adopts existing method etching contact hole to cause polycrystalline grid and shallow-trench isolation edge to carve the schematic diagram of wearing;
Fig. 4 adopts the inventive method to reduce the schematic diagram of Metal Contact silicide loss;
Fig. 5 adopts the inventive method reduction polycrystalline grid and shallow-trench isolation edge to carve to wear the schematic diagram of the degree of depth.
Embodiment
The invention will be further elaborated below in conjunction with drawings and Examples:
Because the etching of contact hole will be carved DARC (SiON)/TEOS/BPSG/SiN/APM (see figure 1) from top to bottom successively, so, use corresponding etching condition at the film of different materials.
The first step: the etching of top layer silicon oxynitride.If this tunic is not carved clean (residual silicon oxynitride is arranged), will have influence on the etching of oxide-film, perforate Halfway Stopping (etch stop) takes place.This goes on foot major parameter: pressure 30-90 millitorr; Go up or lower electrode power: 800-1200 watt; Argon gas 150-250sccm; Fluoroform 15-25sccm; Oxygen 5-25sccm; Backside helium pressure: middle part 4-12 holder, edge 10-20 holder.
Second step: the quick etching of oxide-film main etching.The requirement of the production efficiency of considering, this step adopts higher etch rate and silicon nitride is hanged down the condition of selecting ratio.Adopt etch rate be the 7500-7800 dust/minute, silica to the selection of silicon nitride than being 10:1-13:1.Calculate according to etching, the accurate Calculation etch period is controlled this step 1000-1200 dust on floated etching barrier layer and is stopped, and for example about 1k Izod right side stops.This goes on foot major parameter: pressure 30-90 millitorr; Upper electrode power: 1500-2400 watt, lower electrode power: 800-1600 watt; Argon gas 500-1000sccm; Octafluoro five carbon 5-15sccm; Oxygen 8-25sccm; Backside helium pressure: middle part 4-12 holder, edge 10-20 holder.
The 3rd step: the etching at a slow speed of oxide-film main etching.By adjusting C
5F
8And O
2Ratio, make this step silica to the selection of silicon nitride higher than very (greater than 20:1), and etch rate slow relatively (5200-5400 dust/minute).When considering before each layer metal dielectric deposition, the varied in thickness and the silicon chip inner evenness of each film forming captain film are constantly accumulated, the drift of the etch rate of contact hole etching machine own and the variation of inner evenness simultaneously, all fully opened quarter in order to ensure all active through holes in the silicon chip face, appended 50% over etching.Because to the high selectivity of silicon nitride, even the silicon nitride at polycrystalline grid top also loses seldom, silicon nitride thickness is close on the fundamental sum active area.Can guarantee like this that after removing residual silicon nitride and bottom silica subsequently the loss of Metal Contact silicide can be fewer.This goes on foot major parameter: pressure 30-90 millitorr; Upper electrode power: 1500-2400 watt, lower electrode power: 800-1600 watt; Argon gas 500-1000sccm; Octafluoro five carbon 6-20sccm; Oxygen 8-20sccm; Backside helium pressure: middle part 4-12 holder, limit 10-20 holder.
The 4th step: the polymer of place to go via bottoms.Continue to carry out smoothly in order to ensure etching, and the control of etching CD (size), remove and residue in the polymer that via bottoms is brought by first three step etching.This goes on foot major parameter: pressure 15-35 millitorr; Upper electrode power: 700-1400 watt, lower electrode power: 100-300 watt; Argon gas 100-300sccm; Oxygen 10-30sccm; Backside helium pressure: middle part 4-12 holder, edge 10-30 holder.
The 5th step: floated silicon nitride etch barrier etch.Through-rate is calculated, and removes the silicon nitride that serves as the barrier layer.This goes on foot major parameter: pressure 30-50 millitorr; Upper electrode power: 700-1500 watt, lower electrode power: 100-300 watt; Argon gas 100-300sccm; Fluoroform 8-25sccm; Oxygen 10-30sccm; Backside helium pressure: middle part 4-15 holder, edge 10-30 holder.
The 6th step: bottom oxide film APM etching.Adopt and identical condition of second step.Because thinner thickness is so even add 50% over etching, it is fewer that etch period also can be controlled.Help reducing in a large number polycrystalline grid and shallow-trench isolation edge like this and carve the degree of depth of wearing, thereby reduce the leakage current loss of device.This goes on foot major parameter: pressure 30-80 millitorr; Upper electrode power: 1500-2500 watt, lower electrode power: 800-1800 watt; Argon gas 500-1000sccm; Octafluoro five carbon 5-15sccm; Oxygen 8-25sccm; Backside helium pressure: middle part 4-15 holder, edge 10-30 holder.
As shown in Figure 4, adopt the inventive method, the loss of the Metal Contact silicide of polycrystalline grid top and active area significantly reduces, and wherein, polycrystalline grid top drops to 60 dusts from original polycrystalline grid top 270 dusts; Active area drops to＜50 dusts from 200 dusts, has significantly reduced the contact hole resistance of device.As shown in Figure 5, adopt the inventive method, because the exposure position skew, wear the degree of depth and significantly reduce the quarter at polycrystalline grid and shallow-trench isolation edge, and wherein, polycrystalline grid edge is carved the degree of depth of wearing and significantly is reduced to 400 dusts from 2400 dusts; The shallow-trench isolation edge is carved the degree of depth of wearing and is reduced to＜200 dusts from 1000 dusts, thereby has reduced the leakage loss of device.
Claims (9)
1, the lithographic method of floated etching barrier layer contact hole in a kind of embedded flash memory device is characterized in that, comprises the steps:
The first step: the etching of top layer silicon oxynitride;
Second the step: the quick etching of oxide-film main etching: the employing etch rate be the 7500-7800 dust/minute, silica is 10:1-13:1 to the selection ratio of silicon nitride, the accurate Calculation etch period is controlled this second step 1000-1200 dust on floated etching barrier layer and is stopped;
The 3rd step: the etching at a slow speed of oxide-film main etching: the 3rd step silica to the selection of silicon nitride than 20:1, etch rate be the 5200-5400 dust/minute;
The 4th step: etching is removed the polymer that residues in the contact hole bottom that is brought by first three step etching;
The 5th step: etching is removed floated silicon nitride etch barrier layer;
The 6th step: the bottom as metal before the silicon oxide layer etching of medium.
2, the lithographic method of floated etching barrier layer contact hole in the embedded flash memory device as claimed in claim 1, it is characterized in that the major parameter of first step etching is: pressure is the 30-90 millitorr; Last or lower electrode power is 800-1200 watt; Argon gas is 150-250sccm; Fluoroform is 15-25sccm; Oxygen is 5-25sccm; Backside helium pressure is middle part 4-12 holder, edge 10-20 holder.
3, the lithographic method of floated etching barrier layer contact hole in the embedded flash memory device as claimed in claim 1 is characterized in that, the major parameter of the second step etching is: pressure is the 30-90 millitorr; Upper electrode power is 1500-2400 watt, and lower electrode power is 800-1600 watt; Argon gas is 500-1000sccm; Octafluoro five carbon are 5-15sccm; Oxygen is 8-25sccm; Backside helium pressure is middle part 4-12 holder, edge 10-20 holder.
4, the lithographic method of floated etching barrier layer contact hole in the embedded flash memory device as claimed in claim 1 is characterized in that, the major parameter of the 3rd step etching is: pressure is the 30-90 millitorr; Upper electrode power is 1500-2400 watt, and lower electrode power is 800-1600 watt; Argon gas is 500-1000sccm; Octafluoro five carbon are 6-20sccm; Oxygen is 8-20sccm; Backside helium pressure is middle part 4-12 holder, edge 10-20 holder.
5, the lithographic method of floated etching barrier layer contact hole in the embedded flash memory device as claimed in claim 1 is characterized in that, appends 50% over etching in the 3rd step.
6, the lithographic method of floated etching barrier layer contact hole in the embedded flash memory device as claimed in claim 1 is characterized in that, the major parameter of the 4th step etching is: pressure is the 15-35 millitorr; Upper electrode power is 700-1400 watt, and lower electrode power is 100-300 watt; Argon gas is 100-300sccm; Oxygen is 10-30sccm; Backside helium pressure is middle part 4-12 holder, edge 10-30 holder.
7, the lithographic method of floated etching barrier layer contact hole in the embedded flash memory device as claimed in claim 1 is characterized in that, the major parameter of the 5th step etching is: pressure is the 30-50 millitorr; Upper electrode power is 700-1500 watt, and lower electrode power is 100-300 watt; Argon gas is 100-300sccm; Fluoroform is 8-25sccm; Oxygen is 10-30sccm; Backside helium pressure is middle part 4-15 holder, edge 10-30 holder.
8, the lithographic method of floated etching barrier layer contact hole in the embedded flash memory device as claimed in claim 1, it is characterized in that, the 6th step adopted and identical condition of second step: keep etch rate be the 7500-7800 dust/minute, silica to the selection of silicon nitride than being 10:1-13:1.
9, the lithographic method of floated etching barrier layer contact hole in the embedded flash memory device as claimed in claim 1 is characterized in that, the major parameter of the 6th step etching is: pressure is the 30-80 millitorr; Upper electrode power is 1500-2500 watt, and lower electrode power is 800-1800 watt; Argon gas is 500-1000sccm; Octafluoro five carbon are 5-15sccm; Oxygen is 8-25sccm; Backside helium pressure is middle part 4-15 holder, edge 10-30 holder.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101625993B (en) * | 2008-07-08 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Dual-damascene structure and manufacturing method thereof |
| CN102403218B (en) * | 2010-09-09 | 2013-07-24 | 上海华虹Nec电子有限公司 | Etching method for contact holes |
| JP5859262B2 (en) * | 2011-09-29 | 2016-02-10 | 東京エレクトロン株式会社 | Deposit removal method |
| CN102623396B (en) * | 2012-04-17 | 2014-05-14 | 上海华力微电子有限公司 | Method for forming connection holes |
| CN102683273A (en) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | Method for forming contact holes |
| CN103633106B (en) * | 2013-11-28 | 2016-06-29 | 上海华力微电子有限公司 | CMOS contact hole etching method and CMOS manufacture method |
| CN110661242B (en) | 2019-01-24 | 2022-03-22 | 台达电子企业管理（上海）有限公司 | Direct current power transmission device, surge control circuit and method |
| CN111244033B (en) * | 2020-01-14 | 2023-05-12 | 重庆京东方显示技术有限公司 | Array substrate preparation method, array substrate and display device |
| CN115939030B (en) * | 2022-12-27 | 2024-02-20 | 上海铭锟半导体有限公司 | Method for etching contact hole without stop layer |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
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Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |