CN105652586A - Method for reducing influence of base reflection through exposure auxiliary graph - Google Patents
Method for reducing influence of base reflection through exposure auxiliary graph Download PDFInfo
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- CN105652586A CN105652586A CN201610212558.5A CN201610212558A CN105652586A CN 105652586 A CN105652586 A CN 105652586A CN 201610212558 A CN201610212558 A CN 201610212558A CN 105652586 A CN105652586 A CN 105652586A
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- secondary graphics
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- reflections affect
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The invention provides a method for reducing the influence of base reflection through an exposure auxiliary graph. The method comprises the following steps: classifying ion implanted layer layout graphic boundaries according to the distances from a photoresist boundary to a front layer active region layer and a polysilicon layer within a photoresist opened region, classifying the ion implanted layer layout graphic boundaries with the distance smaller than or equal to a distance threshold as a first class, and classifying the ion implanted layer layout graphic boundaries with the distance greater than the distance threshold as a second class; adding an auxiliary graph with a second size to the second class of ion implanted layer layout graphic boundaries, which can expose a graph on a silicon wafer; adding an auxiliary graph with a first size on the first class of ion implanted layer layout graphic boundaries, which cannot expose a graph on the silicon wafer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to utilize the method that exposure secondary graphics reduces substrate reflections affect.
Background technology
Along with the continuous reduction of technology node, the dimension of picture of ion implanted layer, and require all more and more higher with the alignment precision of front layer. In lithographic process, ion implanted layer is owing to by the reflections affect of layer pattern before the complexity of bottom, can cause that photoetching offset plate figure size deviates, and even narrow avalanche produces defect problem. Use bottom antireflective coating (BARC) although substrate reflections affect can be reduced, but need to increase etching technics to remove BARC, not only increase cost, also substantially increase technology difficulty. Normal optical closes on the dimension compensation that correction (OPC) is done, it is necessary to feeds back according to the metric data of resolution chart and lays down a regulation, then do compensating approach, but is difficult to exhaustive for Protean domain. The dimension of picture of the ion implanted layer technique focus additionally found in actual process, more than 500nm, is affected by bottom reflection and result in avalanche defect, and conventional OPC revises and cannot do dimension compensation.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, offer can utilize the exposure secondary graphics method to reduce substrate reflections affect, can solve the problem that the photoetching offset plate figure size deviation that bottom reflection light causes, the defect problem of even narrow avalanche.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that utilize the method that exposure secondary graphics reduces substrate reflections affect, including:
First step: according to the distance of the front layer active region layer in photoresist border to photoresist opened areas and polysilicon layer, inject ions into a layer layout patterns border to classify, wherein described distance is classified as first category less than or equal to the ion implanted layer layout patterns border of distance threshold, the ion implanted layer layout patterns border of about for described distance distance threshold is classified as second category;
Second step: the ion implanted layer layout patterns border of second category is added the secondary graphics of the second size, and the secondary graphics of described second size can expose figure on silicon chip;
Third step: the secondary graphics to the ion implanted layer layout patterns border interpolation first size of first category, the secondary graphics of wherein said first size will not expose figure on silicon chip.
Preferably, second it is sized larger than first size.
Preferably, the value of distance threshold is more than 2 times of minimum feature.
Preferably, distance threshold value is between 200nm��600nm.
Preferably, the width of the secondary graphics of the second size is be more than or equal to the minimum feature size of technique, and the interval of the secondary graphics of the second size is be more than or equal to the minimum feature size of technique
Preferably, the span of the width of the secondary graphics of the second size is 100nm��1000nm, and the span at the interval of the secondary graphics of the second size is 100nm��1000nm.
Preferably, the width of the secondary graphics of first size is 30nm��90nm.
Preferably, the secondary graphics of first size be spaced apart 30nm��150nm.
Preferably, it is more excellent that second step performed result before third step, but does not limit the precedence of two steps.
The invention provides the utilization exposure secondary graphics method to reduce substrate reflections affect, wherein for ion implanted layer domain, secondary graphics is added in photoresist opened areas, by the distance to front layer active region layer and polysilicon layer, inject ions into layer layout patterns border to classify: be classified as first category to front layer active region layer and polysilicon layer distance less than or equal to the photoresist border of distance threshold, due near ion implanted regions, undersized secondary graphics is added on the border of first category, is characterized as and will not expose figure on silicon chip; It is classified as second category to front layer active region layer and polysilicon layer distance more than the photoresist border of distance threshold, due to neighbouring for useless shallow plough groove isolation area, large-sized secondary graphics can be added, be characterized as and can expose figure on silicon chip. Thus, the present invention blocks transmission light by increasing secondary graphics, reduces the impact of bottom reflection light, solves bottom reflection light and cause that photoetching offset plate figure size deviates, the defect problem of even narrow avalanche.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows and utilizes exposure secondary graphics to reduce the flow chart of the method for substrate reflections affect according to the preferred embodiment of the invention.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention. Note, represent that the accompanying drawing of structure is likely to be not necessarily drawn to scale. Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure clearly with understandable, below in conjunction with specific embodiments and the drawings, present disclosure is described in detail.
Fig. 1 schematically shows and utilizes exposure secondary graphics to reduce the flow chart of the method for substrate reflections affect according to the preferred embodiment of the invention.
As it is shown in figure 1, utilize the method that exposure secondary graphics reduces substrate reflections affect to include according to the preferred embodiment of the invention:
First step S1: according to the distance of the front layer active region layer in photoresist border to photoresist opened areas and polysilicon layer, inject ions into a layer layout patterns border to classify, wherein described distance is classified as first category less than or equal to the ion implanted layer layout patterns border of distance threshold, the ion implanted layer layout patterns border of about for described distance distance threshold is classified as second category;
Preferably, the value of distance threshold is more than 2 times of minimum feature.
Preferably, distance threshold value is between 200nm��600nm. It is further preferred that distance threshold value is between 300nm��500nm.
Second step S2: the ion implanted layer layout patterns border of second category is added the secondary graphics of the second size, and the secondary graphics of described second size can expose figure on silicon chip;
Preferably, the width of the secondary graphics of the second size is be more than or equal to the minimum feature size of technique; For instance, it is preferred that the span of the width of the secondary graphics of the second size is 100nm��1000nm.
Preferably, the interval of the secondary graphics of the second size is be more than or equal to the minimum feature size of technique. For instance, it is preferred that the span at the interval of the secondary graphics of the second size is 100nm��1000nm.
Third step S3: the secondary graphics to the ion implanted layer layout patterns border interpolation first size of first category, the secondary graphics of wherein said first size will not expose figure on silicon chip.
Preferably, the width of the secondary graphics of first size is 30nm��90nm, the secondary graphics of first size be spaced apart 30nm��150nm.
Preferably, second step S2 performed before third step S3, namely first added large scale secondary graphics, and secondary graphics border is near front layer active region layer and polysilicon layer, then by border first category standard, again adds small size secondary graphics.
The secondary graphics that the present invention increases, transition occlusion area is formed between photoresist border and bulk transmission region, make photoresist border away from transparent area, reduce the total light transmission amount of transparent area simultaneously, reduce the impact on photoresist border of the bottom reflection light, under not increasing the premise of technology difficulty and cost, solve bottom reflection light and cause that photoetching offset plate figure size deviates, the defect problem of even narrow avalanche.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the description such as the term in description " first ", " second ", " the 3rd " is used only for each assembly in differentiation description, element, step etc., rather than is used for logical relation or the ordering relation etc. that represent between each assembly, element, step.
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is not limited to the present invention. For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all may utilize the technology contents of the disclosure above and technical solution of the present invention is made many possible variations and modification, or be revised as the Equivalent embodiments of equivalent variations. Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.
Claims (9)
1. utilize the method that exposure secondary graphics reduces substrate reflections affect, it is characterised in that including:
First step: according to the distance of the front layer active region layer in photoresist border to photoresist opened areas and polysilicon layer, inject ions into a layer layout patterns border to classify, wherein described distance is classified as first category less than or equal to the ion implanted layer layout patterns border of distance threshold, described distance is classified as second category more than the ion implanted layer layout patterns border of distance threshold;
Second step: the ion implanted layer layout patterns border of second category is added the secondary graphics of the second size, and the secondary graphics of described second size can expose figure on silicon chip;
Third step: the secondary graphics to the ion implanted layer layout patterns border interpolation first size of first category, the secondary graphics of wherein said first size will not expose figure on silicon chip.
2. the method utilizing exposure secondary graphics to reduce substrate reflections affect according to claim 1, it is characterised in that second is sized larger than first size.
3. the method utilizing exposure secondary graphics to reduce substrate reflections affect according to claim 1 and 2, it is characterised in that the value of distance threshold is more than 2 times of minimum feature.
4. the method utilizing exposure secondary graphics to reduce substrate reflections affect according to claim 1 and 2, it is characterised in that distance threshold value is between 200nm��600nm.
5. the method utilizing exposure secondary graphics to reduce substrate reflections affect according to claim 1 and 2, it is characterized in that, the width of the secondary graphics of the second size is be more than or equal to the minimum feature size of technique, and the interval of the secondary graphics of the second size is be more than or equal to the minimum feature size of technique.
6. the method utilizing exposure secondary graphics to reduce substrate reflections affect according to claim 1 and 2, it is characterized in that, the span of the width of the secondary graphics of the second size is 100nm��1000nm, and the span at the interval of the secondary graphics of the second size is 100nm��1000nm.
7. the method utilizing exposure secondary graphics to reduce substrate reflections affect according to claim 1 and 2, it is characterised in that the width of the secondary graphics of first size is 30nm��90nm.
8. according to claim 1 and 2 utilize the exposure secondary graphics method that reduces substrate reflections affect, it is characterised in that the secondary graphics of first size be spaced apart 30nm��150nm.
9. the method utilizing exposure secondary graphics to reduce substrate reflections affect according to claim 1 and 2, it is characterised in that it is more excellent that second step performed result before third step, but does not limit the precedence of two steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610212558.5A CN105652586B (en) | 2016-04-07 | 2016-04-07 | The method for reducing substrate reflections affect using exposure secondary graphics |
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| CN201610212558.5A CN105652586B (en) | 2016-04-07 | 2016-04-07 | The method for reducing substrate reflections affect using exposure secondary graphics |
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| CN105652586B CN105652586B (en) | 2019-10-25 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328506A (en) * | 2016-08-31 | 2017-01-11 | 上海华力微电子有限公司 | Method for reducing peeling risk of photoresist of ion implantation layer |
| CN106597804A (en) * | 2016-11-30 | 2017-04-26 | 上海华力微电子有限公司 | Front-layer graph identification-based optical proximity correction method for boundary of ion implanted layer |
| CN107481925A (en) * | 2017-07-31 | 2017-12-15 | 上海华力微电子有限公司 | A kind of OPC modification methods of shallow ion implanted layer |
| CN107799405A (en) * | 2017-11-09 | 2018-03-13 | 上海华力微电子有限公司 | A kind of OPC modification methods for improving the anti-front layer reflection of ion implanted layer |
| CN109188870A (en) * | 2018-09-30 | 2019-01-11 | 上海华力集成电路制造有限公司 | Optical proximity correction method |
| CN109407460A (en) * | 2018-12-05 | 2019-03-01 | 上海华力集成电路制造有限公司 | Expose secondary graphics adding method |
| CN110119062A (en) * | 2018-02-06 | 2019-08-13 | 中芯国际集成电路制造(上海)有限公司 | Optical adjacent correction method, photomask manufacturing method and patterning process |
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| EP1947509A2 (en) * | 2003-02-17 | 2008-07-23 | Matsushita Electric Industrial Co., Ltd. | Pattern formation method |
| CN102376536A (en) * | 2010-08-04 | 2012-03-14 | 海力士半导体有限公司 | Method Of Manufacturing Fine Patterns |
| CN103886153A (en) * | 2014-03-27 | 2014-06-25 | 上海华力微电子有限公司 | Drawing method for polycrystalline silicon layer device auxiliary graphs |
| CN104216233A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Exposure method |
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| EP1947509A2 (en) * | 2003-02-17 | 2008-07-23 | Matsushita Electric Industrial Co., Ltd. | Pattern formation method |
| CN102376536A (en) * | 2010-08-04 | 2012-03-14 | 海力士半导体有限公司 | Method Of Manufacturing Fine Patterns |
| CN104216233A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Exposure method |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328506A (en) * | 2016-08-31 | 2017-01-11 | 上海华力微电子有限公司 | Method for reducing peeling risk of photoresist of ion implantation layer |
| CN106328506B (en) * | 2016-08-31 | 2020-04-10 | 上海华力微电子有限公司 | Method for reducing photoresist stripping risk of ion implantation layer |
| CN106597804A (en) * | 2016-11-30 | 2017-04-26 | 上海华力微电子有限公司 | Front-layer graph identification-based optical proximity correction method for boundary of ion implanted layer |
| CN106597804B (en) * | 2016-11-30 | 2020-08-25 | 上海华力微电子有限公司 | Optical proximity correction method for ion implantation layer boundary based on front layer graph discrimination |
| CN107481925B (en) * | 2017-07-31 | 2019-12-06 | 上海华力微电子有限公司 | OPC correction method for shallow ion implantation layer |
| CN107481925A (en) * | 2017-07-31 | 2017-12-15 | 上海华力微电子有限公司 | A kind of OPC modification methods of shallow ion implanted layer |
| CN107799405B (en) * | 2017-11-09 | 2020-05-01 | 上海华力微电子有限公司 | OPC correction method for improving front layer reflection resistance of ion implantation layer |
| CN107799405A (en) * | 2017-11-09 | 2018-03-13 | 上海华力微电子有限公司 | A kind of OPC modification methods for improving the anti-front layer reflection of ion implanted layer |
| CN110119062A (en) * | 2018-02-06 | 2019-08-13 | 中芯国际集成电路制造(上海)有限公司 | Optical adjacent correction method, photomask manufacturing method and patterning process |
| CN110119062B (en) * | 2018-02-06 | 2022-09-20 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method, mask manufacturing method and patterning process |
| CN109188870A (en) * | 2018-09-30 | 2019-01-11 | 上海华力集成电路制造有限公司 | Optical proximity correction method |
| CN109407460A (en) * | 2018-12-05 | 2019-03-01 | 上海华力集成电路制造有限公司 | Expose secondary graphics adding method |
| CN109407460B (en) * | 2018-12-05 | 2022-03-18 | 上海华力集成电路制造有限公司 | Exposure auxiliary pattern adding method |
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