KR20140081068A - Method of separating substrate from epitaxial layer, method of fabricating semiconductor device using the same and semiconductor device fabricated by the same - Google Patents

Abstract

Disclosed are a method of separating a substrate, a method of fabricating a semiconductor device and a semiconductor device fabricated by the same. A method of separating a substrate according to one aspect of the present invention includes preparing a growth substrate; forming a mask pattern which has an opening region and a masking region on the growth substrate; growing an epi layer which covers the mask pattern on the growth substrate having the mask pattern, and includes a cavity on the masking region; and separating the growth substrate from the epi layer. Because the cavity of the epi layer is formed on the masking region, the growth substrate can be easily separated from the epi layer by using the cavity and a stress lift-off or chemical lift-off technique.

Description

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to a method of manufacturing a semiconductor device, a method of manufacturing a semiconductor device, a method of manufacturing a semiconductor device,

The present invention relates to a method of separating a substrate from an epi layer, a method of manufacturing a semiconductor device, and a semiconductor device manufactured using these methods.

In an inorganic semiconductor light-emitting diode, a vertical-type light-emitting diode has been developed in which a growth substrate for growing an epi layer is separated from an epi layer and a support substrate having good heat radiation characteristics is used to increase light output.

The light emitting diode of the vertical structure has a larger light emitting area at the same chip size as the conventional lateral light emitting diode (lateral LED), and has a high internal quantum efficiency because of high heat dissipation efficiency. Furthermore, the light emitting diode of the vertical structure is easy to improve the light extraction efficiency by facilitating the surface texturing of the light emitting surface.

Various methods for separating a growth substrate for manufacturing vertical type light emitting diodes are known. In particular, a laser lift-off (LLO), a chemical lift-off (CLO), or a stress lift- -Off; SLO) technique has attracted attention.

However, the method of separating a substrate using a laser lift-off technique requires not only expensive equipment but also some problems as follows. First, a laser of a strong energy impacts the epi layer, so cracks may occur in the epi layer. Further, since the laser is irradiated through the growth substrate, it is required that the energy band gap difference between the growth substrate and the epi layer be large. Accordingly, when the same type substrate having little difference in energy band gap is used as a growth substrate, it is difficult to separate the growth substrate and the epi layer by laser lift-off. For example, a gallium nitride epitaxial layer grown on a gallium nitride substrate is difficult to separate using a laser lift-off technique.

Meanwhile, a method of separating a substrate using a chemical lift-off technique includes a method of forming a cavity between a growth substrate and an epi layer, and chemically etching a predetermined region between the growth substrate and the epi layer by penetrating the chemical solution into the cavity region use.

In addition, a method of separating a substrate using a stress lift-off technique uses a method of forming a cavity between a growth substrate and an epi layer to weaken the bonding force between the epi layer and the growth substrate, and separating the substrate from the epi layer by applying stress .

The chemical lift-off or the stress lift-off can prevent the damage of the epi layer as compared with the laser lift-off, and can also be applied to the case of using the same substrate as a growth substrate. In order to apply these chemical lift off or stress lift off techniques, it is required to make a relatively large cavity between the growth substrate and the epi layer.

A problem to be solved by the present invention is to provide a method of separating a growth substrate from an epi layer by forming a relatively large cavity between a growth substrate and an epi layer, and a method of manufacturing a semiconductor device using the method.

A further object of the present invention is to provide a substrate separation method and a semiconductor device manufacturing method which can form a cavity between a growth substrate and an epi layer using an epitaxial layer growth condition.

Another object of the present invention is to provide a substrate separation method and a semiconductor device manufacturing method which can separate an epitaxial layer grown from a growth substrate without dividing it.

Another object of the present invention is to provide a light emitting diode having a novel structure capable of improving light extraction efficiency.

According to one aspect of the present invention, there is provided a substrate separation method comprising: preparing a growth substrate; Forming a mask pattern having a masking region and an opening region on the growth substrate; Growing an epitaxial layer covering the mask pattern on a growth substrate having the mask pattern, the epitaxial layer comprising a cavity on the masking region; And separating the growth substrate from the epi layer. Since cavities are formed in the epilayer on the masking region, the cavity can be used to easily separate the growth substrate from the epilayer using stress lift off or chemical lift-off techniques.

The cavity may be confined and positioned on the masking area. The cavity may also include a lower cavity positioned between the epilayer and the masking region and an upper cavity formed in the thickness direction of the epilayer from the lower cavity. The lower cavity has a relatively wider width than the upper cavity.

The growth of the epi layer is performed by growing a 3D epi layer under a 3D growth condition in which vertical growth is superior to horizontal growth and growing a 2D epi layer in a 2D growth condition in which horizontal growth predominates over vertical growth on the 3D epi layer .

Further, growing the epi layer may include growing a 3D epi layer with constant 3D growth conditions, and then growing the epi layer while gradually changing growth conditions from the 3D growth conditions to 2D growth conditions. Thus, the epitaxial layer can be stably grown by preventing abrupt changes in growth conditions.

In some embodiments, the masking region may have a width in the range of 5 to 30 占 퐉, and further may have a width in the range of 10 to 30 占 퐉. Further, the opening region may have a width of 1 mu m or more and less than 3 mu m.

In some embodiments, the method of separating a substrate includes forming a sacrificial layer on the growth substrate before forming the mask pattern; Etching the sacrificial layer exposed through the opening region of the mask pattern using electrochemical etching (ECE). Further, the epi layer may be grown using the sacrificial layer as a seed. Meanwhile, during the growth of the epi layer, a first cavity may be formed in the sacrificial layer.

In certain embodiments, the sacrificial layer may be partially etched by applying a voltage of at least two stages. Here, the applied voltage may be lower than the voltage applied later.

The substrate separation method may further include: forming a semiconductor laminated structure on the epi layer;

And attaching the supporting substrate on the semiconductor laminated structure. The growth substrate may also be separated using chemical lift off techniques or stress lift off techniques. In particular, the growth substrate may be separated by stress due to a difference in thermal expansion coefficient between the support substrate and the growth substrate.

A semiconductor device manufacturing method according to still another aspect of the present invention includes the above-described substrate separating method.

Furthermore, the semiconductor device manufacturing method may further include exposing the semiconductor stacked structure by dry etching the epi layer after separating the growth substrate.

The dry etch may comprise a first etch step using BCl3 and a second etch step using BCl3 and Cl2. The surface can be relatively planarized by the first etching step using BCl3.

According to another aspect of the present invention, there is provided a light emitting diode comprising: a support substrate; A semiconductor laminated structure located on the supporting substrate and including an active layer; A convex portion and a concave portion formed on an upper surface of the semiconductor laminated structure; And a roughened surface formed on the convex portion and the concave portion. Further, the width of the concave portion has a size within a range of 5 to 30 mu m.

Further, the light emitting diode may further include a sub-concave portion in the concave portion.

According to embodiments of the present invention, a relatively large cavity can be formed between the growth substrate and the epi layer using the epi layer growth technique, and by using the chemical lift off or the stress lift off technique, the growth substrate can be separated can do. In particular, the growth substrate can be separated from the epi layer using the difference in thermal expansion coefficient between the support substrate and the growth substrate, and the growth substrate can be separated without dividing the grown epitaxial layer.

Furthermore, it is possible to provide a light emitting diode with improved light extraction efficiency using the shape of the epi layer.

FIGS. 1 to 12 are cross-sectional views and plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
13 to 15 are sectional views for explaining a method of manufacturing a semiconductor device according to still another embodiment of the present invention.
16 is a cross-sectional SEM image illustrating a cavity formed in an epi layer according to another embodiment of the present invention.
17 is a plan and cross-sectional SEM image of an epilayer after separating a growth substrate according to another embodiment of the present invention.
18 is a plan and cross-sectional SEM image for explaining surface characteristics after etching an epilayer using dry etching according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the same reference numerals denote the same elements, and the width, length, thickness, and the like of the elements may be exaggerated for convenience.

FIGS. 1 to 12 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2 to 3 are plan views for explaining a mask pattern. Here, a method of separating a substrate according to an embodiment of the present invention is also described.

Referring to FIG. 1, a lower epitaxial layer 23 may be grown on a growth substrate 21. The growth substrate 21 may be a sapphire substrate, a GaN substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, or the like. In particular, the growth substrate 110 may be a sapphire substrate or a GaN substrate, and may include a polar, non-polar or semipolar substrate.

The lower epi layer 23 may be formed of a gallium nitride semiconductor, such as undoped GaN or n-type GaN, and may be formed using metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) techniques. When the growth substrate 21 is a gallium nitride substrate, the lower epilayer 23 may be omitted.

A mask pattern 25 is formed on the lower epilayer 23. The mask pattern 25 may be formed of, for example, SiO2 or various silicate-based materials. The mask pattern 25 has a masking region 25a and an opening region 25b. Here, the masking region may have a width in the range of 5 to 30 mu m, and further may have a width in the range of 10 to 30 mu m. Further, the opening region may have a width of less than 3 占 퐉 and a width of 1 占 퐉 or more.

As shown in FIG. 2 (a), the mask pattern 25 may have a stripe shape in each of the masking regions. In addition, as shown in FIG. 2 (b) Shape. Alternatively, as shown in FIG. 3A, the mask pattern 25 may have a hexagonal shape. Alternatively, as shown in FIG. 4 (a), the mask pattern 25 may have a masking area And may have a rhombic shape. Alternatively, as shown in FIG. 3 (b), the mask pattern 25 may have a hexagonal shape as an engraved pattern. Alternatively, as shown in FIG. 4 (b) And may have a rhombic shape. The mask pattern 25 may also be an engraved pattern in which the masking area is circular in shape or the opening area is circular in shape.

Referring to FIG. 5, a 3D epi layer 27 is grown using a 3D growth condition on a growth substrate 21 on which a mask pattern 25 is formed. The 3D epi layer 27 is grown using the metal organic chemical vapor deposition (MOCVD) method, and the growth temperature, the growth pressure, and the V / III ratio are controlled so that the vertical growth is superior to the horizontal growth It grows. Generally, as the growth temperature is relatively low, the growth pressure is relatively high, and the V / III ratio is relatively low, the growth condition becomes 3D. For example, when the growth temperature is 1030 ° C., the growth pressure is 400 torr, and the V / III ratio is 300, the growth condition is 3D.

When the 3D epi layer 27 is grown by the 3D growth conditions, the growth of the epi layer 27 starts in the opening region 25b of the mask pattern 25, and the vertical growth is dominant as compared with the horizontal growth. On the other hand, the grooves 27h are formed on the masking region 25a by adjusting the growth thickness so that the epilayer 27 does not join together on the masking region 25a.

Referring to FIG. 6, after the 3D epilayer 27 is grown by the 3D growth condition, the 2D epilayer 29 is grown under the 2D growth condition in which the horizontal growth is dominant compared to the vertical growth, ). The 2D growth condition can be achieved by setting the growth temperature relatively high, the growth pressure relatively low, and the V / III ratio relatively high for 3D growth conditions. For example, when the growth temperature is 1110 deg. C, the growth pressure is 150 torr, and the V / III ratio is 150, the 2D growth condition is obtained.

During the growth of the 2D epilayer 29, horizontal growth proceeds in the groove 27h of the 3D epilayer 27, so that the upper cavity 28a, which becomes narrower in the upward direction into the epilayer 28, . In addition, the lower cavity 28b can be formed between the masking region 25a and the epilayer 28 by growing the epi layer 28 relatively thick, for example, about 10 mu m or more. The inclination of the wall surface of the lower cavity 28b is gentler than the inclination of the wall surface of the upper cavity 28a. Furthermore, the lower cavity 28b may have a greater width than the height.

In this embodiment, after the 3D epi layer 27 is grown under a constant 3D growth condition, the 2D epi layer 29 may be grown under a constant 2D growth condition by changing the growth condition to the 2D growth condition. However, the present invention is not limited thereto. After the 3D epi layer 27 is formed, the epi layer 29 may be grown while gradually changing the growth conditions under the 2D growth condition under the 3D growth condition.

The 2D growth conditions allow the epilayer 29 to be joined together at the top of the trench 27h to form an epilayer 28 having a flat top surface.

The 3D epilayer 27 and the 2D epilayer 29 may be formed of a single kind of GaN, such as undoped GaN, but are not limited thereto. For example, the 2D epilayers 29 may comprise an n-type GaN layer.

According to the present embodiment, relatively large cavities 28a and 28b can be formed on the masking region 25a of the mask pattern 25 using 3D growth conditions and 2D growth conditions. May be confined within the masking region.

Referring to FIG. 7, a semiconductor laminated structure 30 is grown on the epi layer 29. The semiconductor laminated structure 30 includes a first nitride semiconductor layer 31 and a second nitride semiconductor layer 33 and may include an active layer 32.

The first nitride semiconductor layer 31 and the second nitride semiconductor layer 33 may each be a single layer, but the present invention is not limited thereto. Such multiple layers may include an undoped layer and a doped layer. In addition, the active layer 32 may have a single quantum well structure or a multiple quantum well structure.

The first nitride semiconductor layer 31 may be a nitride semiconductor layer doped with an impurity of the first conductivity type, for example, a compound semiconductor of a III-N series doped with an n-type impurity, such as a nitride of (Al, In, A semiconductor layer, and may include a gallium nitride layer. In addition, the first nitride semiconductor layer 31 may include an undoped layer intentionally doped with no impurity.

The active layer 32 may be formed of a III-N compound semiconductor, for example, an (Al, Ga, In) N semiconductor layer, and a single quantum well structure or a well layer (not shown) and a barrier layer (not shown) Lt; RTI ID = 0.0 > quantum well < / RTI >

The second nitride semiconductor layer 33 includes a III-N compound semiconductor, for example, a (Al, Ga, In) N-based Group III nitride semiconductor layer doped with a P-type impurity For example, a GaN layer.

Referring to Fig. 8, a supporting substrate 51 is attached on the semiconductor laminated structure 30. As shown in Fig. The supporting substrate 51 may be bonded to the semiconductor laminated structure 30 through the bonding metal layer 53. On the other hand, before attaching the supporting substrate 51, a reflective metal layer 35 and a barrier metal layer 37 may be formed on the semiconductor laminated structure 30. The reflective metal layer 35 may comprise, for example, Ag or Al, and the barrier metal layer 37 may comprise Ni. The reflective metal layer 35 is electrically connected to the second nitride semiconductor layer 33 and reflects light generated in the active layer 32 to improve light efficiency. On the other hand, the barrier metal layer 37 covers the reflective metal layer 35 to protect the reflective metal layer 35.

In this embodiment, since relatively large cavities 28a and 28b are formed in the epi layer 28, it is not necessary to previously form an element isolation region for providing a chemical channel. Therefore, the reflective metal layer 35 and the barrier metal layer 37 may be formed on the entire surface of the semiconductor laminated structure 30 without dividing the semiconductor laminated structure 30.

Referring to Fig. 9, the supporting substrate 51 is separated from the epi layer 28. As shown in Fig. The support substrate 51 can be separated from the epi layer 28 using a stress lift-off technique using stress or a chemical lift-off using a chemical solution.

In particular, the support substrate 51 may be formed of a material having a thermal expansion coefficient different from that of the growth substrate 21, for example, a thermal expansion coefficient of 5.5 to 7.5 / K. For example, the supporting substrate 51 may be formed of MoCu or CuW, for example. Thereby, after the support substrate 51 is attached, the growth substrate 21 is separated from the cavities 28a and 28b by the thermal expansion coefficient difference between the support substrate 51 and the growth substrate 21, ). ≪ / RTI >

Alternatively, the growth substrate 21 may be separated from the epi layer 28 using stress, after removing the mask pattern 25 using HF or BOE.

The growth substrate 21 is separated from the epi layer 28 along with the lower epi layer 23 so that the epi layer 28 having the cavities 28a and 29a is exposed.

Referring to FIG. 10, the exposed epi layer 28 is planarized to expose the semiconductor stacked structure 30. The epi layer 28 may be planarized using dry etching. For example, BCl 3 gas is supplied at a flow rate of 35 to 45 sccm, and the protruded portion 28 cv is etched at a higher etch rate than the concave portion by performing one-step etching under the conditions of a process pressure of about 5 mTorr and an RF power of about 500 W. Next, BCl 3 and Cl 2 are supplied at a flow rate of about 5 to 6 sccm and 20 to 25 sccm, respectively, and the epitaxial layer 28 is etched by performing a two-step etching at a process pressure of about 5 mTorr and an RF power of about 300 W. It is possible to prevent the shapes of the cavities 28a and 28b from being transferred to the semiconductor laminated structure 30 by the one-step etching and the two-step etching.

The convex portion 30cv and the concave portion 30cc are formed on the surface of the semiconductor laminated structure 30 by the dry etching. The convex portion 30cv generally corresponds to the protruded portion 28cv of the epi layer 28 and the concave portion 30cc corresponds to the portion where the mask pattern 25 is removed. Further, the convex portion 30cv may be a residual portion of the epi layer 28. [ On the other hand, the sub concave portion 28c may be formed in the concave portion 30cc. The sub concave portion 28c may have an attached shape.

Referring to FIG. 11, isolation trenches 30a for separating the semiconductor laminated structure 30 into device regions are formed. In addition, a roughened surface R can be formed on the surface of the semiconductor laminated structure 30 by using photo enhanced chemical etching or the like. The roughened surface R is formed on the surfaces of the projections 30cv and the recesses 30cc. The light extraction efficiency of the light generated in the active layer 32 is improved by forming the roughened surface R in addition to the projections 30cv and the recesses 30cc.

The roughened surface R may be formed after the element isolation trench 30a is formed, but the roughened surface R may be formed first to form the element isolation trench 30a.

Thereafter, electrodes 39 are formed on the respective device regions. The electrode 39 is electrically connected to the first nitride semiconductor layer 31 of the semiconductor laminated structure 30. [

Referring to Fig. 12, a semiconductor device such as a light emitting diode is completed by dividing the supporting substrate 51 along the element isolation trench 30a. The supporting substrate 51 can be divided using a laser scribing technique.

According to the present embodiment, cavities 28a and 28b can be formed on each masking region 25a of the mask pattern 25 using an epitaxial growth technique. By using these cavities 28a and 28b, (21) can be easily separated from the epi layer (28). Accordingly, the growth substrate 21 can be separated without dividing the semiconductor stacked structure 30, and consequently, the loss of the semiconductor stacked structure 30 can be reduced and the yield of semiconductor devices can be increased.

The epitaxial layer 28 can be easily separated from the growth substrate 21 by, for example, penetrating the chemical solution such as HF or BOE through the upper and lower cavities 28a and 29b to remove the masking region 25a have. In addition, since the bonding strength between the epi layer 28 and the mask pattern 25 is weakened by the upper and lower cavities 28a and 29b, the epi layer 28 can be easily separated from the growth substrate 21 by stress . Moreover, since the lower cavity 28a is formed in a sharp shape between the masking region 25a and the epilayer 28, the interface between the epilayer 28 and the masking region 25a can be easily separated using the stress .

13 to 15 are sectional views for explaining a method of manufacturing a semiconductor device according to still another embodiment of the present invention. The semiconductor device manufacturing method according to the present embodiment is substantially similar to the semiconductor device manufacturing method described with reference to FIGS. 1 to 12, so that the characteristic contents will be mainly described.

First, referring to FIG. 13, a gallium nitride-based sacrificial layer 24 is grown on the growth substrate 21. The sacrificial layer 24 may be grown on the growth substrate 21 using a technique such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The sacrificial layer 24 may be type of a relatively high impurity concentration for example of 1E17 ~ 1E19 / cm ³ Si-doped n gallium nitride-based semiconductor layer, such as a GaN layer. The undoped gallium nitride based semiconductor layer such as the lower epilayer 23 of FIG. 1 may be grown on the growth substrate 21 before the sacrificial layer 24 is grown.

A mask pattern 25 is formed on the sacrifice layer 24. The mask pattern 25 may be formed as described with reference to Fig. However, the opening region 25b of the mask pattern 25 may have a wider width than the opening region 25b described in FIG.

Subsequently, the sacrificial layer 24 exposed in the opening region 25b of the mask pattern 25 is partially etched using electrochemical etching to form fine pores 24a in the sacrificial layer 24 .

In the electrochemical etching process, after a growth substrate 21 on which a sacrifice layer 24 is formed and a cathode electrode (e.g., Pt electrode) are immersed in an ECE solution, a positive voltage is applied to the sacrifice layer 24, And the size of the micro pores 24a can be adjusted by adjusting the molar concentration of the ECE solution, the process time, and the applied voltage.

The ECE solution may be an electrolyte solution, for example, an electrolyte solution containing oxalic acid, HF or NaOH.

In this embodiment, the sacrificial layer 24 may be partially etched by a one-step electrochemical etching (ECE) in which a voltage of the same voltage, for example, in the range of 10 to 60 V is applied successively. However, the present invention is not limited thereto, and can be partially etched by a two-step electrochemical etching (ECE) method in which a relatively low voltage is initially applied and then a relatively high voltage is applied. FIG. 10 shows micropores 241 and 242 formed by two-step electrochemical etching. Micropores 241 are formed in a first step of applying a relatively low voltage, and relatively large micropores 242 are formed. Is formed in two steps of applying a relatively high voltage. For example, using a 0.3M solution of oxalic acid in 20 ℃ for GaN sacrificial layer (24) having a Si doping concentration of 6E18 / cm ^3, step 1, and applying a voltage of 8 ~ 9V, step 2, from 15 to Electrochemical etching can be performed by applying a voltage of 17V.

By using the two-step electrochemical etching, the surface of the n-type gallium nitride based sacrificial layer 24 can maintain a relatively good crystallinity, and the surface of the n-type gallium nitride based sacrificial layer 24 is relatively large Fine pores 242 can be formed, which is advantageous for a subsequent process.

Referring to FIG. 14, a 3D epi layer 27 is grown using the sacrificial layer 24 as a seed, as described with reference to FIG. 5, and a detailed description thereof will be omitted. However, during the growth of the 3D epilayer 27, the micropores 24a are combined and grown to form the cavity 24b. The cavity 24b is formed below the opening region 25b of the mask pattern 25 and is formed to connect the adjacent masking regions 25a to each other.

Referring to FIG. 15, a 2D epilayer 29 is grown on the 3D epilayer 27 to form an epi layer 28 covering the mask pattern 25, as described with reference to FIG.

Thereafter, the individual light emitting diodes can be manufactured through the steps as described with reference to Figs. 7 to 12.

According to the present embodiment, in addition to the cavities 28a and 28b of the embodiment described with reference to Figs. 1 to 12, a cavity 24b is formed below the opening region 25b of the mask pattern 25. Therefore, the epitaxial layer 28 can be more easily separated from the growth substrate 21 by using the chemical lift off or the stress lift off technique.

Further, since the cavity 24b is formed under the opening region 25b, the width of the opening region 25b can be made relatively larger.

16 is a cross-sectional SEM image of an epitaxial wafer manufactured according to the method described above with reference to Figs. 13 to 15. Fig. Here, the growth substrate 21 is a sapphire substrate, the sacrificial layer 24 is an n-type GaN layer, and the mask pattern 25 is made of SiO 2. The sacrificial layer was etched with a 2-step ECE. Also, a 3D epilayer was grown for 60 minutes under a constant 3D growth condition of a growth temperature of 1030 DEG C, a growth pressure of 400 torr, and a V / III ratio of 300. After completion of the 3D growth under the constant conditions, the temperature, pressure and Ⅴ / Ⅲ ratio were gradually changed until the 2D growth condition of growth temperature 1110 캜, growth pressure 150 torr, Ⅴ / Ⅲ ratio 150, The epi layer 28 was grown by growing the epi layer.

Referring to FIG. 16, it can be seen that a first cavity (1) is formed under the opening region of the mask pattern 25, and a second cavity (2) and a third cavity (3) are formed above the masking region. Moreover, it can be seen that the second cavity and the third cavity have a relatively larger volume than the first cavity formed by the ECE.

Therefore, the epilayer 28 can be easily separated from the growth substrate 21 using the second cavity and the third cavity.

FIG. 17 is a plan and cross-sectional SEM images of the epilayer 28 after the growth substrate 21 has been separated from the grown epilayer 28 according to the method described with reference to FIGS.

17 (a) and (b), after the growth substrate 21 is separated, protruded portions 28cv and cavities 28a and 28b are observed on the surface of the epi layer 28. The projected portion 28cv is a portion where the portion of the epi layer 28 formed in the opening region 25b of the mask pattern 25 remains as the mask pattern 25 is removed.

18 is a plan and cross-sectional SEM image for explaining the surface characteristics after etching the epi layer using the dry etching of the epi layer 28 of FIG. The dry etching was performed by the first and second step etching processes as described above with reference to FIG.

18 (a) and (b), protruding portions 30cv and recesses 30cc are observed on the surface of the epi layer 28 after dry etching, and sub-recesses 28c are formed in the recesses 30cc. Is observed. The protrusion 30cv corresponds to the protruding portion 28cv described above, and the recess 30cc generally corresponds to the position of the cavities 28a and 28b. It can be confirmed that the cavities 28a and 28b have almost no shape due to the dry etching in the concave portion 30cc and the surface is relatively planarized. Further, as compared with the protruding portion 28cv of the stripe shape, the protruding portion 30cv is formed relatively irregularly. That is, a part of the position corresponding to the projected portion 28cv is etched to almost the same level as the recessed portion 30cc, and therefore, the projected portion 30cv appears intermittently.

As a result, the epilayer 28 having cavities 28a and 28b can be planarized by dry etching using the first and second step etch processes.

Various embodiments have been described above with reference to the drawings to facilitate understanding of the technical features of the present invention. However, these embodiments may be modified in various ways without departing from the spirit of the present invention, and these modifications are within the scope of the present invention.

Claims (20)

Preparing a growth substrate;
Forming a mask pattern having a masking region and an opening region on the growth substrate;
Growing an epitaxial layer covering the mask pattern on a growth substrate having the mask pattern, the epitaxial layer comprising a cavity on the masking region;
And separating the growth substrate from the epi layer. The method according to claim 1,
Wherein the cavity is confined to the masking region. The method of claim 2,
Said cavity comprising a lower cavity positioned between said epilayer and said masking region and an upper cavity formed in the thickness direction of said epilayer from said lower cavity,
Wherein the lower cavity has a relatively wider width than the upper cavity. The method of claim 3,
The growth of the epi-
Vertical growth is more dominant than horizontal growth, 3D growth conditions are growing,
And growing a 2D epilayer on the 3D epilayer in a 2D growth condition predominately horizontal growth than vertical growth. The method of claim 4,
The growth of the epi-
Growing a 3D epilayer under a constant 3D growth condition, and then growing the epilayer while gradually changing growth conditions from the 3D growth condition to the 2D growth condition. The method according to claim 1,
Wherein the masking region has a width in the range of 5 to 30 占 퐉. The method of claim 6,
Wherein the masking region has a width in the range of 10 to 30 占 퐉. The method of claim 6,
Wherein the opening region has a width of 1 占 퐉 or more and less than 3 占 퐉. The method according to claim 1,
Forming a sacrificial layer on the growth substrate before forming the mask pattern;
Further comprising etching the sacrificial layer exposed through the opening region of the mask pattern using electrochemical etching (ECE). The method of claim 9,
Wherein the epitaxial layer is grown using the sacrificial layer as a seed. The method of claim 10,
Wherein a first cavity is formed in the sacrificial layer during growth of the epi layer. The method of claim 9,
Wherein the sacrificial layer is at least two stages of voltage applied and partially etched, wherein the applied voltage is lower than the voltage applied later. The method according to claim 1,
Forming a semiconductor stacked structure on the epi layer;
Further comprising attaching a support substrate on the semiconductor laminate structure. 14. The method of claim 13,
Wherein the growth substrate is separated using a chemical lift-off technique or a stress lift-off technique. 15. The method of claim 14,
Wherein the growth substrate is separated by stress due to a difference in thermal expansion coefficient between the support substrate and the growth substrate. A method for manufacturing a semiconductor device comprising the substrate separation method according to any one of claims 1 to 15. 18. The method of claim 16,
Removing the growth substrate, and then dry-etching the epi layer to expose the semiconductor stacked structure. 18. The method of claim 17,
The dry etching of the second method of manufacturing a semiconductor device comprising an etching step with a first etching step and the BCl ₃ and Cl ₂ with BCl ₃ together. A support substrate;
A semiconductor laminated structure located on the supporting substrate and including an active layer;
A convex portion and a concave portion formed on an upper surface of the semiconductor laminated structure; And
And a roughened surface formed on the convex portion and the concave portion,
And the width of the recess has a size within a range of 5 to 30 占 퐉. The method of claim 19,
And a sub-concave portion in the concave portion.

Images