CN104681525A - 一种多芯片叠层的封装结构及其封装方法 - Google Patents
一种多芯片叠层的封装结构及其封装方法 Download PDFInfo
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- CN104681525A CN104681525A CN201310617032.1A CN201310617032A CN104681525A CN 104681525 A CN104681525 A CN 104681525A CN 201310617032 A CN201310617032 A CN 201310617032A CN 104681525 A CN104681525 A CN 104681525A
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Abstract
本发明涉及一种多芯片叠层的封装结构及其封装方法,仅使用一个联结片设置于HS芯片的源极和LS芯片的漏极上实现其电性连接,导电损耗和开关损耗减小,且热耗散效率则得到增强。IC芯片绝缘地连接在联结片上,从而可以叠放到HS芯片及LS芯片所在平面的上方,以有效减少封装后的器件尺寸。本发明中可以将第一、第二载片台的底面暴露在塑封体外;还有多种方法,进一步将联结片上不连接IC芯片的一部分表面暴露在塑封体外;或者在联结片上进一步连接散热板,并使该散热板的一部分表面暴露在塑封体外;或者将散热板插入到塑封体预留的缺口中以接触联结片帮助散热。
Description
技术领域
本发明涉及半导体领域,特别涉及一种多芯片叠层的封装结构及其封装方法。
背景技术
在DC-DC(直流-直流)转换器中,通常设有两个MOSFET(金属氧化物半导体场效应管)作为切换开关,一个是高端MOSFET(简称HS),另一个是低端MOSFET(简称LS)。其中,HS的栅极G1及LS的栅极G2均与一控制器(简称IC)连接;HS的漏极D1连接Vin端,源极S1连接LS的漏极D2,而LS的源极S2连接Gnd端,以形成所述的DC-DC转换器。
对于DC-DC转换器中的芯片封装结构,是希望将高端MOSFET芯片和低端MOSFET芯片以及控制器芯片封装在同一个塑封体中,以减少外围器件数量,同时提高电源等的利用效率。然而,对于具体的封装结构来说,上述高端MOSFET芯片和低端MOSFET芯片以及控制器芯片只能在引线框架的同一个平面上平行布置,因此封装后的体积大;而且,仅仅通过引线来连接芯片的相应引脚(例如是HS的源极S1与LS的漏极D2之间),将使得电阻和热阻增加,影响器件成品的性能。
发明内容
本发明的目的是提供一种多芯片叠层的封装结构及其封装方法的多种实施方案,能够通过设置联接片将控制器芯片叠放在高端和低端的MOSFET芯片所在的平面之上,并通过该联接片实现相应芯片引脚的电路连接,以实现将多个半导体芯片封装在同一个半导体封装中,从而减少直流-直流转换器组装时元件的数量,减小整个半导体封装的尺寸,并有效改善器件的电学性能及散热效果。
为了达到上述目的,本发明一个技术方案是提供一种多芯片叠层的封装结构,其包含:
引线框架,其设有相互隔开的第一载片台,第二载片台和若干引脚,所述第二载片台进一步设有相互隔开的第一部分和第二部分;
第一芯片,其背面电极向下布置并导电连接在第一载片台上;
第二芯片,通过翻转使其正面电极向下布置并导电连接在第二载片台的第一部分及第二部分上,该第二芯片的其中一些正面电极连接至所述第一部分,其中另一些正面电极连接至所述第二部分;
联结片,其底面同时导电连接至第一芯片向上布置的其中一些正面电极,及第二芯片向上布置的背面电极上;
第三芯片,其背面向下布置并绝缘地连接在所述联结片的顶面上;
塑封体,其封装了依次叠放为多层结构的第三芯片、联结片、第一芯片及第二芯片、引线框架,以及对应连接在芯片电极与芯片电极之间或芯片电极与引脚之间的引线,并且,使引脚与外部器件连接的部分以及第一载片台和第二载片台背面的至少一部分暴露在该塑封体以外。
一个具体的应用实例中,所述第一芯片是一个作为高端MOSFET芯片的HS芯片,其背面设置的漏极导电连接在第一载片台上;
所述第二芯片是一个作为低端MOSFET芯片且经过芯片级封装的LS芯片,其正面设置的源极导电连接在第二载片台的第一部分上,正面设置的栅极导电连接在第二载片台的第二部分上;
所述联结片的背面导电连接在所述HS芯片正面的源极及所述LS芯片背面的漏极上,用以实现这两个电极之间的电性连接;
所述第三芯片是一个作为控制器的IC芯片,其底面绝缘地连接在联结片的顶面上,而其顶面的若干电极分别通过引线对应连接至其他芯片上的相应电极或引线框架上的相应引脚;
所述HS芯片正面或LS芯片背面上未被联结片遮蔽的若干电极,也分别通过引线对应连接至其他芯片上的相应电极或引线框架上的相应引脚。
一个实施例中,所述封装结构还在形成塑封体前设置有散热板,所述散热板与所述第三芯片分别连接在联结片的顶面之上,以使该散热板与联结片形成导热接触,进而通过该散热板暴露在塑封体顶面之外的表面实现散热。
另一个实施例中,所述封装结构还在形成塑封体后设置有散热板;所述塑封体的顶面上进一步形成有缺口,所述散热板的底部插入至该缺口以连接至联结片的顶面,并形成该散热板与联结片的导热接触,进而通过所述散热板留在塑封体顶面之外的顶部实现散热。
所述联结片设有连接在第一芯片上的高端连接部分,和连接在第二芯片上的低端连接部分;所述联结片的高端连接部分及低端连接部分具有相同或不同的厚度;
一个实施例中,所述高端连接部分、第一芯片、第一载片台厚度的和值,与所述低端连接部分、第二芯片、第二载片台厚度的和值相等,从而使连接后联结片的顶面水平以稳固放置第三芯片。
又一个实施例中,所述第三芯片连接于联结片的高端连接部分或低端连接部分中厚度较小的一个部分之上,高端连接部分或低端连接部分中厚度较大的一个部分的顶面暴露在所述塑封体之外实现散热。
优选的,在所述联结片上形成有若干个局部调整联结片厚度的触点,所述触点是使该联结片顶面向下凹陷形成不穿透的盲孔且同时使该联结片底面向下突出的结构。
所述联结片进一步设有引线连接部分,其导电连接至引线框架所设置的互联引脚上;所述引线连接部分、高端连接部分及低端连接部分,是通过一体成型或通过组装连接来形成所述联结片的;
优选的,所述引线连接部分与所述互联引脚上对应设置有防止组装及封装过程中联结片位置改变的锁定机构。
优选的,所述第一芯片与第一载片台之间,所述第二芯片与第二载片台之间,所述联结片与所述第一芯片及第二芯片之间的导电连接,是通过在相互连接的表面之间设置的焊锡或导电的环氧树脂胶实现;
所述第三芯片与所述联结片之间绝缘地连接,是通过在第三芯片背面设置的不导电粘结胶实现。
优选的所述联结片是铜片。
本发明的另一个技术方案是提供一种多芯片叠层的封装方法,包含:
设置引线框架,其设有相互隔开的第一载片台,第二载片台和若干引脚,所述第二载片台进一步设有相互隔开的第一部分和第二部分;
将第一芯片的背面电极向下布置并导电连接在第一载片台上;
将第二芯片翻转以使其正面电极向下布置并导电连接在第二载片台的第一部分及第二部分上,该第二芯片的其中一些正面电极连接至所述第一部分,其中另一些正面电极连接至所述第二部分;
将联结片底面同时导电连接至第一芯片向上布置的其中一些正面电极,及第二芯片向上布置的背面电极上;
将第三芯片的背面向下布置并绝缘地连接在所述联结片的顶面上;
形成塑封体将依次叠放为多层结构的第三芯片、联结片、第一芯片及第二芯片、引线框架,以及对应连接在芯片电极与芯片电极之间或芯片电极与引脚之间的引线进行封装后,切割所述塑封体形成一个独立的器件;并且,使引脚与外部器件连接的部分以及第一载片台和第二载片台背面的至少一部分暴露在该塑封体以外。
一个实施例中,所述封装方法还在塑封之前将设置的一散热板也连接至所述联结片的顶面之上,以使该散热板与联结片形成导热接触,进而通过该散热板暴露在塑封体顶面之外的表面实现散热。
另一个实施例中,所述封装方法在封装形成的塑封体的顶面上形成有缺口,并将设置的一散热板的底部插入至该缺口以连接至联结片的顶面,并形成该散热板与联结片的导热接触,进而通过所述散热板留在塑封体顶面之外的顶部实现散热。
所述联结片设有连接在第一芯片上的高端连接部分,和连接在第二芯片上的低端连接部分;所述联结片的高端连接部分及低端连接部分具有相同或不同的厚度;
两者厚度不同时,所述第三芯片连接于联结片的高端连接部分或低端连接部分中厚度较小的一个部分之上,高端连接部分或低端连接部分中厚度较大的一个部分的顶面暴露在所述塑封体之外实现散热。
优选的,所述第一芯片与第一载片台之间,所述第二芯片与第二载片台之间,所述联结片与所述第一芯片及第二芯片之间的导电连接,是通过在相互连接的表面之间设置的焊锡或导电的环氧树脂胶实现;
所述第三芯片与所述联结片之间绝缘地连接,是通过在第三芯片背面设置的不导电粘结胶实现。
优选的实施例中,在所述联结片上形成有若干个局部调整联结片厚度的触点,所述触点是通过打孔方式使该联结片顶面向下凹陷形成不穿透的盲孔且同时使该联结片底面向下突出的结构。
上述任意一个实施例中,所述第一芯片是通过以下过程形成的:在硅片上用以连接其他器件的表面分别形成镀层;进行芯片测试;芯片背面研磨及背面金属化以控制第一芯片的厚度并形成相应的背面电极;切割形成各个独立的第一芯片;之后,再将所述第一芯片背面向下连接至第一载片台。
所述第二芯片是通过以下过程形成的:在硅片上用以连接其他器件的表面形成镀层;进行芯片测试及电路图形映射;在硅片正面对应位置植球以形成相应的正面电极;芯片级封装形成封装体;在芯片正面研磨,以使植球的顶部暴露在封装体的顶面外;芯片正面预切割,形成划片槽;芯片背面研磨及背面金属化以控制第二芯片的厚度并形成相应的背面电极;切割形成各个独立的第二芯片;之后,将所述第二芯片翻转后使其正面向下连接至第二载片台。
所述第三芯片是通过以下过程形成的:芯片背面研磨;IC芯片的背面涂覆不导电的粘结胶;切割形成各个独立的第三芯片;之后,将所述第三芯片粘结于已经连接至第一芯片、第二芯片上的联结片的顶面;
在第三芯片、联结片、第一芯片及第二芯片叠放形成多层结构后,还具有以下过程:黏贴胶带,进行固化;在相应的芯片电极与芯片电极之间,及芯片电极与引脚之间分别键接形成引线;形成塑封体;在暴露于塑封体外的位置形成镀层;最终切割形成各个独立的封装器件。
与现有技术相比,本发明所述多芯片叠层的封装结构及其封装方法,其优点在于:
相比原先使用多个贴片或键接的引线来连接HS芯片的源极与LS芯片的漏极的结构,本发明中仅使用一个联结片同时焊接或导电黏贴至HS芯片的源极和LS芯片的漏极上,就可以电性连接这两个电极,工艺简单易于实现,导电损耗和开关损耗减小,且热耗散效率则得到增强,器件成品的性能更好。
相比原先将三个芯片并排放在同一个平面的结构,本发明中的IC芯片绝缘地连接在联结片上,从而可以叠放到HS芯片及LS芯片所在平面的上方,以有效减少封装后的器件尺寸,节约封装材料。
本发明中可以将第一、第二载片台的底面暴露在塑封体外,便于连接电路板及实现散热。本发明中还有三种方法,进一步在塑封体顶面也形成散热用的表面,即,将联结片上不连接IC芯片的一部分表面暴露在塑封体外;或者在联结片上进一步连接散热板,并使该散热板有一部分表面暴露在塑封体外;或者将散热板插入到塑封体预留的缺口中以接触联结片进行散热。
本发明的叠层结构并不会影响在IC芯片与其他芯片之间,HS芯片或LS芯片与引脚之间键接形成连接用的引线。可以通过设置各部分厚度不同的联结片或通过在联结片上连接的散热板来调整封装结构内不同位置的厚度,以使封装结构一侧的IC芯片、其下方的联结片部分、HS芯片、第一载片台及相应的引线的总体厚度,与封装结构另一侧的联结片的较厚部分或散热板与联结片的组合、LS芯片、第二载片台的总体厚度相匹配。
本发明中还可以通过在联结片上打孔形成在底面向下突出的多个触点,这在例如键接引线之后的情况下,可以方便快速地实现对联结片局部的厚度调整。
本发明中在联结片和与之连接的引线框架引脚上对应设置有锁定机构,以确保组装及封装过程中,联结片的位置不会发生改变。另外,散热片也可以通过设置锁定机构来固定其位置。
附图说明
图1A是本发明在第一实施例中所述芯片封装结构的立体图;
图1B是本发明在第一实施例中所述芯片封装结构的正面透视图;
图1C是本发明在第一实施例中所述芯片封装结构的侧剖面示意图;
图1D和图1E是本发明所述芯片封装结构中一种优选联接片正反面的结构示意图;
图2A~图2G是本发明在第一实施例中与所述芯片封装方法各步骤相对应的结构示意图;
图3是本发明在第一实施例中所述芯片封装方法的流程图;
图4A~图4G是本发明在第二实施例中与所述芯片封装方法各步骤相对应的结构示意图;
图5是本发明在第二实施例中所述芯片封装方法的流程图;
图6A~图6H是本发明在第三实施例中与所述芯片封装方法各步骤相对应的结构示意图;
图7是本发明在第三实施例中所述芯片封装方法的流程图;
图8A~图8F是本发明在第四实施例中与所述芯片封装方法各步骤相对应的结构示意图;
图9是本发明在第三实施例中所述芯片封装方法的流程图。
具体实施方式
以下将结合附图,说明本发明的多个优选的实施例。
实施例1
配合参见图1A~图1C所示,本发明中由2个相同类型的MOSFET芯片(2个N型或2个P型),分别作为高端MOSFET(简称为HS芯片20)和低端MOSFET芯片(简称为LS芯片30)。通过一个联结片40将一个控制器芯片(简称为IC芯片50)叠放在这两个MOSFET芯片所在的同一个平面上,并且,将IC芯片50与LS芯片30和HS芯片20的相应电极及引脚14连接后封装在同一个塑封体100内,以形成一个直流-直流转换器。
所述的HS芯片20和LS芯片30,各自在芯片正面设有源极和栅极,而在芯片背面设有漏极;其中,HS芯片20的栅极G1及LS芯片30的栅极G2均与IC芯片50上的控制极连接;HS芯片20的漏极D1连接Vin端,源极S1连接LS芯片30的漏极D2,而LS芯片30的源极S2连接Gnd端,形成所述直流-直流转换器。在直流-直流转换器的Vin-Gnd两端之间还可以设置电容、电感等其他的元器件。
本实施例提供的封装结构中,设有引线框架10(参见图2A所示),该引线框架10在同一平面上设置有相互分离的第一载片台11和第二载片台,其中,第二载片台还设置有相互分离的第一部分12和第二部分13。所述引线框架10还设置有多个相互分离的引脚14,其中包含:低端源极引脚、低端栅极引脚、高端源极引脚、高端栅极引脚,以及互联引脚15等。
本实施例中的这些引脚14分布在第一载片台11和第二载片台的周边,其中,高端漏极引脚是从第一载片台11上延伸设置的,低端源极引脚是从第二载片台的第一部分12上延伸设置的,低端栅极引脚是从第二载片台的第二部分13上延伸设置的;其他若干引脚14则都是与第一载片台11或第二载片台相互隔开的。
所述HS芯片20放置在第一载片台11上,在该HS芯片20的背面与第一载片台11的顶面之间设有焊锡或导电的环氧树脂粘结胶91或其他的导电连接材料,以使HS芯片20背面的漏极S1与第一载片台11形成电性连接,并可以通过高端漏极引脚与外部器件连通。
芯片级封装的LS芯片30,在翻转后放置于第二载片台上,在该LS芯片30向下的正面与第二载片台的第一部分12及第二部分13之间设有焊锡或导电的环氧树脂粘结胶91等,以使LS芯片30正面的源极与第二载片台的第一部分12电性连接,并可以通过低端源极引脚与外部器件连通;同时,LS芯片30正面的栅极G2与第二载片台的第二部分13电性连接,并可以通过低端栅极引脚与外部器件连通。
本实施例提供的封装结构中特别设置的联结片40是由导电材料制成,例如是一种铜片。该联结片40设有高端连接部分41和低端连接部分42,分别通过焊锡或导电的环氧树脂粘结胶91等,粘接设置在HS芯片20及LS芯片30向上的表面之上,从而使HS芯片20正面的源极S1及LS芯片30背面的漏极D2(两者均为向上布置)分别与联结片40底面的相应位置电性连接,并实现HS芯片20的源极S1与LS芯片30的漏极D2之间的电性连接。
所述联结片40的厚度设计,应当满足使联结片40的高端连接部分41与其下方HS芯片20等相加的厚度,等于联结片40的低端连接部分42与其下方LS芯片30等相加的厚度,来保证粘接后整个联结片40的顶面是与HS芯片20及LS芯片30所在的平面相平行的,以便于后续稳固放置IC芯片50。例如,优选的实施例中是使第一载片台11和第二载片台的厚度一致;HS芯片20和LS芯片30厚度一致,连接在引线框架10后两个芯片的顶面水平;并且,使联结片40上对应连接HS芯片20及LS芯片30的位置的厚度一致,从而保证其叠放在两个芯片上后的顶面也是水平的。
配合参见图1D~图1E所示,例如,可以在联结片40的底部分别形成能够调整其高端连接部分41及低端连接部分42的厚度的凸起块411、421。并且,在一个优选的实施例中,在凸起块411、421的位置还可以形成有多个向下突出的触点45,来进一步调整联结片40各部分的厚度。这些触点45的形成,是通过在联结片40上打孔,从而在联结片40的顶面形成不穿透的凹坑,并在联结片40的底部形成所述的触点45。一个联结片40上,不同位置触点45的打孔深度可以相同或不相同,根据具体的厚度调节情况决定。
同时,该联结片40还设置有引脚连接部分43,用来与位于引线框架10周边的互联引脚15进行电性连接,以使HS芯片20的源极S1及LS芯片30的漏极D2及联结片40能够进一步通过该互联引脚15与外部器件连通。所述联结片40的引脚连接部分43,其向下突出部分431的厚度加上与该突出部分431连接的互联引脚15的厚度,也应当满足上述使粘接后联结片40的顶面与两个MOSFET芯片相平行的设计目的。
在一个优选的实施例中,在引线框架10的互联引脚15上及所述联结片40的引脚连接部分43还对应设置有锁定机构。在图1A的示例结构中,互联引脚15上的锁定机构是开设的若干个定位孔81,而联结片40的锁定机构则是在其底部的对应位置的定位件82,图示的定位件82相当于一种从联结片40底面向下延伸或弯折的结构,能够对应插入到这些定位孔81中以实现联结片40位置的固定,以确保在组装及封装过程联结片40不会发生移动。并且,在设置有上述锁定机构时,联结片40上定位件82的厚度,是大于引脚连接部分43的厚度,以确保该定位件82能够对应插入到互联引脚15的定位孔81中。本发明并不限制在其他的实施结构中互换定位孔81及定位件82的位置或使用其他结构的锁定机构。
在图1A的示例结构中,联结片40的表面形状及其尺寸设计,使得该联结片40的高端连接部分41基本覆盖了其下方LS芯片30顶部的绝大部分面积,但低端连接部分42则没有将HS芯片20的顶部完全覆盖。因而,所述HS芯片20正面未被联结片40遮蔽的源极S1和栅极G1,可以分别通过若干个键接的引线60,直接连接至引线框架10的引脚14或其他芯片(例如是IC芯片50)的电极上;或者,将引线框架10的引脚14作为中转,设置多段分别键接的引线60,以间接连接至其他芯片(例如是IC芯片50)上的相应电极。本发明也不限制在其他的实施例中,使用其他结构的联结片40,例如,是不完全覆盖LS芯片30的结构;或者,联结片40不是一体成型的,而是由多个小的联结部件相互连接或组装形成的等等。
本发明所述的IC芯片50,通过不导电的粘结胶92或其他绝缘的固定连接方式,粘接设置在该联结片40的顶面之上,以使IC芯片50、联结片40、HS芯片20与LS芯片30形成为一个自上而下叠放的多层结构,同时该IC芯片50与HS芯片20和LS芯片30的电极之间不会通过联结片40实现电性连接。
在图1A的示例结构中,所述IC芯片50是位于联结片40的高端连接部分41之上,即对应HS芯片20上方的位置;而在其他未显示出的示例中,IC芯片50可以是位于联结片40顶面的其他位置。所述IC芯片50上的若干电极,能够分别通过键接的引线60,电性连接至引线框架10周边的相应引脚14上或其他芯片(例如是HS芯片20)的相应电极上。
本实施例的封装结构中,还包含塑封体100,将上述叠设的IC芯片50、联结片40、HS芯片20与LS芯片30及对应电极上连接的引线60都封装起来形成一个器件,而将各个引脚14与外部器件连接的部分暴露出来,并且使引线框架10上第一载片台11和第二载片台(例如是其第一部分12)的底面暴露在塑封体100之外,用以连接电路板或帮助散热。
以下请配合参见图2A~图2G所示的结构,及图3所示的流程,介绍本实施例所述芯片的封装方法:
即,见图2A,设置一个引线框架10,包含相互隔开的第一载片台11,设有第一部分12和第二部分13的第二载片台,以及多个引脚14。
见图2B,设置一个MOSFET芯片为HS芯片20,将其固定连接在第一载片台11上并使HS芯片20背面的漏极D1与第一载片台11形成电性连接。
见图2C,设置另一个芯片级封装的MOSFET芯片为LS芯片30,将其翻转后固定连接在第二载片台上并使LS芯片30正面的源极S1与第二载片台的第一部分12形成电性连接,且LS芯片30正面的栅极G2与第二载片台的第二部分13形成电性连接。
见图2D,设置一个联结片40,在其背面分别通过设置焊锡或导电的环氧树脂粘结胶91等类似方式,将该联结片40的高端连接部分41连接至HS芯片20顶面,低端连接部分42连接至LS芯片30顶面,引脚连接部分43连接至引线框架10的互联引脚15上,使得HS芯片20正面的源极S1、LS芯片30向上的背面漏极D2与互联引脚15之间相互形成电性连接。
见图2E,将IC芯片50通过不导电的粘结胶92,固定设置在联结片40的顶面上,形成IC芯片50、联结片40、HS芯片20与LS芯片30叠放的多层结构。并且,在HS芯片20正面未被联结片40遮蔽的栅极G1和源极S1,IC芯片50的若干电极,及引线框架10的若干引脚14之间相互通过键接的引线60对应连接。
见图2F及图2G正反两面所示,设置塑封体100将IC芯片50、联结片40、HS芯片20与LS芯片30叠放的多层结构及引线60等都封装起来,而使各个引脚14用以连接外部器件的位置及第一载片台11和第二载片台的背面暴露出来。
再参见图3所示,当设置一个LS芯片30时,通过以下步骤实现:在LS芯片30上用于后续连贴固定的表面形成有镀层,例如是Ni/Au的镀层;芯片测试及电路图形映射;在芯片正面对应位置进行植球以形成相应的电极。芯片级封装;在芯片正面研磨,以使植球的顶部暴露在封装体的顶面外;例如,可以在研磨后使植球暴露的顶面与封装体的顶面齐平,等等。芯片正面预切割,形成划片槽。芯片背面研磨及背面金属化形成相应电极;例如一个具体实例中经过背面研磨及背面金属化后的厚度为6mil,其中硅片的厚度为3mil,硅片上方的封装体厚度为3mil。之后,切割形成各个独立的LS芯片30,再翻转使其以正面朝下且背面朝上的方式导电连接至第二载片台上。
而在设置一个HS芯片20时,通过以下步骤实现:在HS芯片20上用于后续连贴固定的表面形成有镀层,例如是Ni/Pd/Au的镀层;芯片测试;芯片背面研磨及背面金属化,例如以上述的具体实例说明,使背面研磨及背面金属化后HS芯片20和LS芯片30的厚度一致,为6mil。切割形成各个独立的HS芯片20,使其正面朝上,背面朝下连接至第一载片台11。
而在设置一个IC芯片50时,通过以下步骤实现:IC芯片50背面研磨,例如为6mil。在IC芯片50的背面涂覆不导电的粘结胶92。切割形成各个独立的IC芯片50,并置于清洗后的联结片40顶面上。
则IC芯片50、联结片40、HS芯片20与LS芯片30叠放连接之后,具体设有黏贴胶带,进行固化;在相应芯片的电极及引脚14之间键接形成连接的引线60;形成塑封体100;在暴露的位置形成镀层;通过锯切或冲压等类似方式,切割形成各个独立的封装器件的若干步骤。
实施例2
图4A~图4G示出了本实施例中芯片封装各个步骤中的结构示意,图5示出了本实施例中封装方法的流程。其中,本实施例的结构简述如下,即,设置一个引线框架10(图4A),包含第一载片台11,用于固定连接HS芯片20并与其背面漏极D1形成电性连接(图4B);还包含第二载片台,设有第一部分12和第二部分13,用于固定连接翻转的封装LS芯片30并分别与其正面的源极S2和栅极G2形成电性连接(图4C)。将一个联结片40导电连接在HS芯片20及LS芯片30上,以使该联结片40的高端连接部分41电性连接至HS芯片20正面的源极S1,而该联结片40的低端连接部分42电性连接至LS芯片30LS芯片30向上的背面漏极D2,并进而通过该联结片40的引脚连接部分43电性连接至引线框架10的互联引脚15(图4D);
与实施例1中的不同之处在于,本实施例中是在联结片40上同时设置了IC芯片50和一个散热板71,例如是导热性能良好的铜板或类似材料制成所述散热板71。例如,是将该散热板71设置在联结片40的低端连接部分42的顶面上形成良好的导热接触(图4E),而将IC芯片50绝缘地粘接在联结片40的高端连接部分41(图4F)。则,形成IC芯片50与散热板71,联结片40,HS芯片20及LS芯片30叠放的多层结构,并且,散热板71的厚度设计,应当与IC芯片50与HS芯片20或引脚14之间连接若干引线60后的厚度大致相当。将上述多层结构封装在塑封体100中,而使各个引脚14外连的部分,第一载片台11和第二载片台的大部分底面分别暴露在塑封体100的底面之外;同时使散热板71的顶面暴露在塑封体100的顶面之外进一步帮助散热。
配合参见图5所示,本实施例中设置引线框架10、HS芯片20、LS芯片30及IC芯片50的过程与实施例1中基本一致,不同点主要是需要设置散热板71,并在联结片40粘接在HS芯片20和LS芯片30上以后,到清洗联结片40以设置IC芯片50之前,需要增加将散热板71连接至联结片40顶面的步骤。
实施例3
图6A~图6G示出了本实施例中芯片封装各个步骤中的结构示意,图7示出了本实施例中封装方法的流程。其中,本实施例的结构简述如下,即,设置一个引线框架10(图6A),包含第一载片台11,用于固定连接HS芯片20并与其背面漏极D1形成电性连接(图6B);还包含第二载片台,设有第一部分12和第二部分13,用于固定连接翻转的封装LS芯片30并分别与其正面的源极S2和栅极G2形成电性连接(图6C)。将一个联结片40导电连接在HS芯片20及LS芯片30上,以使该联结片40的高端连接部分41电性连接至HS芯片20正面的源极S1,而该联结片40的低端连接部分42电性连接至LS芯片30LS芯片30向上的背面漏极D2,并进而通过该联结片40的引脚连接部分43电性连接至引线框架10的互联引脚15(图6D)。将一个IC芯片50绝缘地粘接在联结片40的高端连接部分41,并形成IC芯片50、HS芯片20及引脚14之间相互的引线60连接(图6E);
与实施例1中的不同之处在于,本实施例中是在使用塑封体100将IC芯片50,联结片40,HS芯片20及LS芯片30叠放的多层结构一起封装时,塑封体100底面暴露的结构不变,而是在该塑封体100的顶面上形成一个缺口101,使得联结片40上的低端连接部分42有一部分面积从该缺口101中暴露出来(图6F)。设置一个散热板72,例如是导热性能良好的铜板或类似材料制成,该散热板72的底部向下设置有一个突起件(图6G),该突起件能够插入塑封体100的缺口101,且具有足够的厚度从而连接至联结片40形成导热接触。该散热板72的顶部留在塑封体100的顶面上(图6H),因此可以在不超过塑封体100面积的情况下设置尽量大的散热面积,以提升散热效果。
配合参见图7所示,本实施例中设置引线框架10、HS芯片20、LS芯片30及IC芯片50的过程与实施例1中基本一致,不同点主要是需要设置散热板72,并在封装多层结构形成带缺口101的塑封体100之后,需要增加将散热板72的突起件插入到缺口101与其中的联结片40顶面实现连接及导热接触的步骤。
实施例4
图8A~图8G示出了本实施例中芯片封装各个步骤中的结构示意,图9示出了本实施例中封装方法的流程。其中,本实施例的结构简述如下,即,设置一个引线框架10(图8A),包含第一载片台11,用于固定连接HS芯片20并与其背面漏极D1形成电性连接(图8B);还包含第二载片台,设有第一部分12和第二部分13,用于固定连接翻转的封装LS芯片30并分别与其正面的源极S2和栅极G2形成电性连接(图8C)。将一个联结片40导电连接在HS芯片20及LS芯片30上,以使该联结片40的高端连接部分41电性连接至HS芯片20正面的源极S1,而该联结片40的低端连接部分42电性连接至LS芯片30LS芯片30向上的背面漏极D2,并进而通过该联结片40的引脚连接部分43电性连接至引线框架10的互联引脚15(图8D);
与实施例1中的不同之处在于,本实施例中的联结片40结构不同,其中,高端连接部分41(及引脚连接部分43)的厚度小于低端连接部分42的厚度(图8D)。而该低端连接部分42的厚度设计,应当满足将IC芯片50绝缘地粘接在联结片40的高端连接部分41上,且在IC芯片50与HS芯片20或引脚14之间连接若干引线60后的厚度大致相当(图8E)。则,塑封体100将上述IC芯片50,联结片40,HS芯片20及LS芯片30叠放的多层结构封装后,除塑封体100底面暴露的部分不变之外,同时还使该联结片40的低端连接部分42的顶面暴露在塑封体100的顶面之外以进一步帮助散热。本实施例中联结片40的三个部分可以是一体成型的,也可以是通过组装或连接后形成的。
配合参见图9所示,本实施例中设置引线框架10、HS芯片20、LS芯片30及IC芯片50及将其封装的过程与实施例1中基本一致,不同点主要是需要在封装前以胶带等覆盖联结片40的高端连接部分41的顶面,以便于封装后能够使其暴露设置。
本发明中各个芯片本身的制作流程可以根据本领域的常规手段实现。而本发明中将多芯片通过联结片40叠放并连接的封装结构及封装方法,除了上文描述的使用两个MOSFET芯片及一个IC芯片50以外,还可以运用到其他器件的封装中,例如是封装高压IGBT芯片(绝缘栅双极型晶体管)、高压控制器,或者用于封装更多数量的芯片或更多的芯片叠层,等等。
尽管本发明的内容已经通过上述优选实施例作了详细介绍,但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后,对于本发明的多种修改和替代都将是显而易见的。因此,本发明的保护范围应由所附的权利要求来限定。
Claims (19)
1.一种多芯片叠层的封装结构,其特征在于,包含:
引线框架,其设有相互隔开的第一载片台,第二载片台和若干引脚,所述第二载片台进一步设有相互隔开的第一部分和第二部分;
第一芯片,其背面电极向下布置并导电连接在第一载片台上;
第二芯片,通过翻转使其正面电极向下布置并导电连接在第二载片台的第一部分及第二部分上,该第二芯片的其中一些正面电极连接至所述第一部分,其中另一些正面电极连接至所述第二部分;
联结片,其底面同时导电连接至第一芯片向上布置的其中一些正面电极,及第二芯片向上布置的背面电极上;
第三芯片,其背面向下布置并绝缘地连接在所述联结片的顶面上;
塑封体,其封装了依次叠放为多层结构的第三芯片、联结片、第一芯片及第二芯片、引线框架,以及对应连接在芯片电极与芯片电极之间或芯片电极与引脚之间的引线,并且,使引脚与外部器件连接的部分以及第一载片台和第二载片台背面的至少一部分暴露在该塑封体以外。
2.如权利要求1所述多芯片叠层的封装结构,其特征在于,
所述第一芯片是一个作为高端MOSFET芯片的HS芯片,其背面设置的漏极导电连接在第一载片台上;
所述第二芯片是一个作为低端MOSFET芯片且经过芯片级封装的LS芯片,其正面设置的源极导电连接在第二载片台的第一部分上,正面设置的栅极导电连接在第二载片台的第二部分上;
所述联结片的背面导电连接在所述HS芯片正面的源极及所述LS芯片背面的漏极上,用以实现这两个电极之间的电性连接;
所述第三芯片是一个作为控制器的IC芯片,其底面绝缘地连接在联结片的顶面上,而其顶面的若干电极分别通过引线对应连接至其他芯片上的相应电极或引线框架上的相应引脚;
所述HS芯片正面或LS芯片背面上未被联结片遮蔽的若干电极,也分别通过引线对应连接至其他芯片上的相应电极或引线框架上的相应引脚。
3.如权利要求1所述多芯片叠层的封装结构,其特征在于,
所述封装结构还在形成塑封体前设置有散热板,所述散热板与所述第三芯片分别连接在联结片的顶面之上,以使该散热板与联结片形成导热接触,进而通过该散热板暴露在塑封体顶面之外的表面实现散热。
4.如权利要求1所述多芯片叠层的封装结构,其特征在于,
所述封装结构还在形成塑封体后设置有散热板;所述塑封体的顶面上进一步形成有缺口,所述散热板的底部插入至该缺口以连接至联结片的顶面,并形成该散热板与联结片的导热接触,进而通过所述散热板留在塑封体顶面之外的顶部实现散热。
5.如权利要求1~4中任意一项所述多芯片叠层的封装结构,其特征在于,
所述联结片设有连接在第一芯片上的高端连接部分,和连接在第二芯片上的低端连接部分;所述联结片的高端连接部分及低端连接部分具有相同或不同的厚度;
所述高端连接部分、第一芯片、第一载片台厚度的和值,与所述低端连接部分、第二芯片、第二载片台厚度的和值相等,从而使连接后联结片的顶面水平以稳固放置第三芯片。
6.如权利要求5所述多芯片叠层的封装结构,其特征在于,
所述第三芯片连接于联结片的高端连接部分或低端连接部分中厚度较小的一个部分之上,高端连接部分或低端连接部分中厚度较大的一个部分的顶面暴露在所述塑封体之外实现散热。
7.如权利要求6所述多芯片叠层的封装结构,其特征在于,
在所述联结片上形成有若干个局部调整联结片厚度的触点,所述触点是使该联结片顶面向下凹陷形成不穿透的盲孔且同时使该联结片底面向下突出的结构。
8.如权利要求5所述多芯片叠层的封装结构,其特征在于,
所述联结片进一步设有引线连接部分,其导电连接至引线框架所设置的互联引脚上;所述引线连接部分、高端连接部分及低端连接部分,是通过一体成型或通过组装连接来形成所述联结片的;
所述引线连接部分与所述互联引脚上对应设置有防止组装及封装过程中联结片位置改变的锁定机构。
9.如权利要求1所述多芯片叠层的封装结构,其特征在于,
所述第一芯片与第一载片台之间,所述第二芯片与第二载片台之间,所述联结片与所述第一芯片及第二芯片之间的导电连接,是通过在相互连接的表面之间设置的焊锡或导电的环氧树脂胶实现;
所述第三芯片与所述联结片之间绝缘地连接,是通过在第三芯片背面设置的不导电粘结胶实现。
10.如权利要求1所述多芯片叠层的封装结构,其特征在于,
所述联结片是铜片。
11.一种多芯片叠层的封装方法,其特征在于,
设置引线框架,其设有相互隔开的第一载片台,第二载片台和若干引脚,所述第二载片台进一步设有相互隔开的第一部分和第二部分;
将第一芯片的背面电极向下布置并导电连接在第一载片台上;
将第二芯片翻转以使其正面电极向下布置并导电连接在第二载片台的第一部分及第二部分上,该第二芯片的其中一些正面电极连接至所述第一部分,其中另一些正面电极连接至所述第二部分;
将联结片底面同时导电连接至第一芯片向上布置的其中一些正面电极,及第二芯片向上布置的背面电极上;
将第三芯片的背面向下布置并绝缘地连接在所述联结片的顶面上;
形成塑封体将依次叠放为多层结构的第三芯片、联结片、第一芯片及第二芯片、引线框架,以及对应连接在芯片电极与芯片电极之间或芯片电极与引脚之间的引线进行封装后,切割所述塑封体形成一个独立的器件;并且,使引脚与外部器件连接的部分以及第一载片台和第二载片台背面的至少一部分暴露在该塑封体以外。
12.如权利要求11所述多芯片叠层的封装方法,其特征在于,
所述封装方法还在塑封之前将设置的一散热板也连接至所述联结片的顶面之上,以使该散热板与联结片形成导热接触,进而通过该散热板暴露在塑封体顶面之外的表面实现散热。
13.如权利要求11所述多芯片叠层的封装方法,其特征在于,
所述封装方法在封装形成的塑封体的顶面上形成有缺口,并将设置的一散热板的底部插入至该缺口以连接至联结片的顶面,并形成该散热板与联结片的导热接触,进而通过所述散热板留在塑封体顶面之外的顶部实现散热。
14.如权利要求11所述多芯片叠层的封装方法,其特征在于,
所述联结片设有连接在第一芯片上的高端连接部分,和连接在第二芯片上的低端连接部分;所述联结片的高端连接部分及低端连接部分具有相同或不同的厚度;
两者厚度不同时,所述第三芯片连接于联结片的高端连接部分或低端连接部分中厚度较小的一个部分之上,高端连接部分或低端连接部分中厚度较大的一个部分的顶面暴露在所述塑封体之外实现散热。
15.如权利要求11所述多芯片叠层的封装方法,其特征在于,
所述第一芯片与第一载片台之间,所述第二芯片与第二载片台之间,所述联结片与所述第一芯片及第二芯片之间的导电连接,是通过在相互连接的表面之间设置的焊锡或导电的环氧树脂胶实现;
所述第三芯片与所述联结片之间绝缘地连接,是通过在第三芯片背面设置的不导电粘结胶实现。
16.如权利要求11所述多芯片叠层的封装方法,其特征在于,
在所述联结片上形成有若干个局部调整联结片厚度的触点,所述触点是通过打孔方式使该联结片顶面向下凹陷形成不穿透的盲孔且同时使该联结片底面向下突出的结构。
17.如权利要求11~16中任意一项所述多芯片叠层的封装方法,其特征在于,
所述第一芯片是通过以下过程形成的:在硅片上用以连接其他器件的表面分别形成镀层;进行芯片测试;芯片背面研磨及背面金属化以控制第一芯片的厚度并形成相应的背面电极;切割形成各个独立的第一芯片;之后,再将所述第一芯片背面向下连接至第一载片台。
18.如权利要求17中任意一项所述多芯片叠层的封装方法,其特征在于,
所述第二芯片是通过以下过程形成的:在硅片上用以连接其他器件的表面形成镀层;进行芯片测试及电路图形映射;在硅片正面对应位置植球以形成相应的正面电极;芯片级封装形成封装体;在芯片正面研磨,以使植球的顶部暴露在封装体的顶面外;芯片正面预切割,形成划片槽;芯片背面研磨及背面金属化以控制第二芯片的厚度并形成相应的背面电极;切割形成各个独立的第二芯片;之后,将所述第二芯片翻转后使其正面向下连接至第二载片台。
19.如权利要求18中任意一项所述多芯片叠层的封装方法,其特征在于,
所述第三芯片是通过以下过程形成的:芯片背面研磨;IC芯片的背面涂覆不导电的粘结胶;切割形成各个独立的第三芯片;之后,将所述第三芯片粘结于已经连接至第一芯片、第二芯片上的联结片的顶面;
在第三芯片、联结片、第一芯片及第二芯片叠放形成多层结构后,还具有以下过程:黏贴胶带,进行固化;在相应的芯片电极与芯片电极之间,及芯片电极与引脚之间分别键接形成引线;形成塑封体;在暴露于塑封体外的位置形成镀层;最终切割形成各个独立的封装器件。
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CN108649020A (zh) * | 2018-05-18 | 2018-10-12 | 上海凯虹科技电子有限公司 | 堆叠芯片的封装方法及采用该方法制造的封装体 |
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