CN104637958B - 阵列基板及显示装置 - Google Patents
阵列基板及显示装置 Download PDFInfo
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Abstract
本发明提供一种阵列基板及显示装置,属于显示技术领域。本发明的阵列基板,其包括交叉设置的多条栅线和多条数据线,以及由相邻栅线和相邻数据线限定的像素单元,所述像素单元包括薄膜晶体管和像素电极,每条数据线包括多个数据线线段,每一数据线线段对应一个像素单元,且同一数据线的两相邻的数据线线段通过连接部连接;所述栅线的延伸方向与所述数据线线段的延伸方向的夹角为α,其中,60°≤α≤87°;所述薄膜晶体管的栅极为栅线的凸起结构,所述凸起结构的靠近像素电极的一侧边的延伸方向与所述栅线的延伸方向的夹角为β,其中,20°≤β≤70°。本发明的阵列基板可以得到一个优化的视角方向、较高的开口率和较好的显示质量。
Description
技术领域
本发明属于显示技术领域,具体涉及一种阵列基板及显示装置。
背景技术
液晶显示技术广泛应用与电视、手机以及公共信息显示。液晶显示模式可以分成扭曲向列相(TN,twisted nematic,)模式,垂直取向(VA,vertical aligned)模式,水平电场(horizontal electrical field)模式。其中,水平电场模式包括,面内开关(IPS,in-plane switching)模式和边缘场开关模式(FFS,Fringe field switching),除VA模式以外,TN和水平电场模式的液晶显示面板都需要摩擦工艺,使液晶分子具有一个初始的排列方向。液晶显示面板的优化视角方向与摩擦方向有密切关系。
对于FFS模式,液晶显示面板包括阵列基板和彩膜基板,阵列基板包括多条栅线、多条数据线和多个像素单元,栅线与数据线垂直交叉,相邻的栅线与相邻的数据线限定出像素单元,像素单元包括:薄膜晶体管、像素电极、公共电极;其中,公共电极位于像素电极上方,且公共电极上形成有狭缝,像素电极和公共电极之间设置有绝缘层,数据线上的数据电压通过薄膜晶体管写入像素电极,整块公共电极覆盖所有的像素单元。FFS模式的液晶显示面板需要摩擦工艺,使液晶分子具有一个初始的排列方向,现有技术中FFS的摩擦取向的方向与数据线的延伸方向具有大约7°的夹角,而由于数据线和栅线是垂直交叉设置的,因此在沿数据线的延伸方向观看显示面板,并不能得到一个优化的视角方向。
发明内容
本发明所要解决的技术问题包括,针对现有的阵列基板存在的上述问题,提供一种视角优化、开口率较高以及较好显示质量的阵列基板及显示装置。
本发明提供一种阵列基板,其包括交叉设置的多条栅线和多条数据线,以及由相邻栅线和相邻数据线限定的像素单元,所述像素单元包括薄膜晶体管和像素电极,每条数据线包括多个数据线线段,每一数据线线段对应一个像素单元,且同一数据线的两相邻的数据线线段通过连接部连接;所述栅线的延伸方向与所述数据线线段的延伸方向的夹角为α,其中,60°≤α≤87°;所述薄膜晶体管的栅极为栅线的凸起结构,所述凸起结构的靠近所述像素电极的一侧边的延伸方向与所述栅线的延伸方向的夹角为β,其中,20°≤β≤70°。
优选的是,70°≤α≤85°,30°≤β≤50°。
优选的是,所述像素电极为板状电极,其包括第一边、第二边、第三边、第四边、第五边;其中,所述第一边和所述第二边平行于所述栅线的延伸方向;所述第三边和所述第四边平行于所述数据线线段的延伸方向;所述第五边平行于所述凸起结构的靠近像素电极的一侧边的延伸方向。
优选的是,所述阵列基板还包括公共电极,所述公共电极设置于所述像素电极上方,且与所述像素电极绝缘;所述公共电极具有狭缝,所述狭缝的延伸方向平行于所述数据线线段的延伸方向。
优选的是,所述薄膜晶体管的源极为所述连接部,或者为所述连接部的部分结构。
优选的是,同一条数据线的对应不同像素单元的数据线线段的延伸方向相互平行。
优选的是,所述连接部的形状为曲线线段。
优选的是,所述栅线的突起结构的另一侧边位于所述凸起结构作为栅极的所述薄膜晶体管所在所述像素单元的外侧。
优选的是,所述栅线的凸起结构的顶边与所述凸起结构作为栅极的所述薄膜晶体管所在所述像素单元对应的数据线线段交叠。
优选的是,所述薄膜晶体管的漏极与所述像素电极通过钝化层过孔连接或直接搭接。
本发明提供一种显示装置,所述显示装置包括阵列基板和与该阵列基板对盒设置的对盒基板,所述阵列基板为上述的阵列基板。
本发明具有如下有益效果:
本发明供的阵列基板,每条数据线包括多个数据线线段,每一数据线线段对应一个像素单元,且同一数据线的两相邻的数据线线段通过连接部连接;所述栅线的延伸方向与所述数据线线段的延伸方向的夹角为α,其中,60°≤α≤87°;所述薄膜晶体管的栅极为栅线的凸起结构,所述凸起结构的靠近所述像素电极的一侧边的延伸方向与所述栅线的延伸方向的夹角为β,其中,20°≤β≤70°。该阵列基板可以得到一个优化的视角方向、较高的开口率和较好的显示质量。
附图说明
图1为本发明实施例1的阵列基板上的示意图;
图2为图1中一个像素单元的示意图;
图3为本发明实施例1的夹角α和β的示意图;
图4为图2的A1-A2截面图;
图5为本发明实施例2的阵列基板的示意图;
图6为图5中一个像素单元的示意图;
图7为图5的A1-A2截面图。
其中附图标记为:
1:衬底;
Gi:第i行栅线;Gi+1:第i+1行栅线;Gi-1:第i-1行栅线;
Dj-1:第j-1列数据线;Dj:第j列数据线;Dj+1:第j+1列数据线;
CLi-1:第i-1行公共电极线;CLi:第i行公共电极线;CLi+1:第i+1行公共电极线;
15:栅极绝缘层;
25:钝化层;
10:栅线的凸起结构;10a:栅线的凸起结构的一侧边;10b:栅线的凸起结构的另一侧边;10c:栅线的凸起结构的顶边;
20:有源层;
30:数据线线段;31:源极;32:漏极;
30a:连接部;
40:钝化层过孔;
50:像素电极;50a:第一边;50b-第二边;50c:第三边;50d:第四边;50e:第五边;
60:公共电极;60a:狭缝。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1:
结合图1-4所示,本实施例提供一种阵列基板,该阵列基板包括交叉设置的多条栅线(例如Gi-1、Gi、Gi+1)和多条数据线(例如Dj-1、Dj、Dj+1),以及由相邻栅线和相邻数据线限定的像素单元,每条数据线包括多个数据线线段30,每一数据线线段30对应一个像素单元,且同一数据线的两相邻的数据线线段30通过连接部30a连接;所述栅线的延伸方向与所述数据线线段30的延伸方向的夹角为α;其中,60°≤α≤87°;所述薄膜晶体管的栅极为栅线的凸起结构10,所述凸起结构10的靠近像素电极的一侧边的延伸方向与所述栅线的延伸方向的夹角为β,其中,20°≤β≤70°。
由于本实施例阵列基板的栅线的延伸方向和数据线线段30的延伸方向的夹角为α,60°≤α≤87°,所述凸起结构的靠近像素电极的一侧边的延伸方向与所述栅线的延伸方向的夹角为β,20°≤β≤70°,因此该阵列基板可以得到一个优化的视角方向、较高的开口率和较好的显示质量。
本实施例所提供的阵列基板可应用于TN模式的显示装置中。
具体的,如图2和3所示,由第i行栅线Gi、i+1行栅线Gi+1、第j列数据线Dj、第j+1列数据线Dj+1限定的像素单元Pij为例,其中,与栅线Gi平行的是公共电极线CLi,像素单元Pij包括薄膜晶体管、像素电极50,与该像素电极对应的数据线线段30,数据线线段30的延伸方向与栅线Gi的延伸方向的夹角则为α,薄膜晶体管的栅极为栅线Gi的凸起结构10,所述凸起结构10的靠近像素电极50的一侧边10a的延伸方向与所述栅线Gi的延伸方向的夹角为β。
其中,60°≤α≤87°,20°≤β≤70°。进一步优选地,70°≤α≤85°,30°≤β≤50°。
其中,本实施例的像素电极50为板状电极,其包括第一边50a、第二边50b、第三边50c、第四边50d、第五边50e;其中,所述第一边50a和所述第二边50b平行于所述栅线Gi的延伸方向;所述第三边50c和所述第四边50d平行于所述数据线段30的延伸方向;所述第五边50e平行于所述凸起结构10的靠近像素电极50的一侧边10a的延伸方向。所述栅线的凸起结构10的另一侧边10b位于所述凸起结构10作为栅极的所述薄膜晶体管所在所述像素单元的外侧。所述栅线的凸起结构10的顶边10c与所述凸起结构作为栅极的所述薄膜晶体管所在所述像素单元对应的数据线线段交叠。此时,不仅可以保证阵列基板较大的开口率,而且还充分利用了像素区的空间。
其中,如图4所示,在薄膜晶体管源极31和漏极32所在层与像素电极50所在层之间设置有钝化层25,像素电极50通过贯穿钝化层25的过孔40与薄膜晶体管的漏极32连接。薄膜晶体管的源极31为所述数据线Dj的连接部30a,或者薄膜晶体管的源极31为所述连接部30a的部分结构,特别的是,本实施例中所述数据线Dj的连接部30a的形状为曲线段。需要说明的是,像素电极50也可以设置在栅极绝缘层15上,与薄膜晶体管的漏极32也可以采用直接搭接的方式连接。
其中,本实施例中同一条数据线的对应不同像素单元的数据线线段30的延伸方向相互平行。
相应的,本实施例还针对上述阵列基板提供了一种阵列基板的制备方法,其包括如下步骤:
步骤一、在衬底1上采用溅射的方法沉积一层栅极金属层薄膜,通过构图工艺形成薄膜晶体管栅极、栅线和公共电极线的图形。
需要说明的是,衬底1既可以指没有形成任何膜层的衬底,如白玻璃,也可以指形成有其他膜层或者图案的衬底,例如形成有缓冲层的衬底。构图工艺通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。
其中,所述栅极金属层薄膜的材料可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层,优选为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
步骤二、在完成上述步骤的衬底1上,采用化学气相沉积、等离子辅助化学气相淀积或溅射等制备方法,形成栅极绝缘层15。
其中,所述栅极绝缘层15的材料可以为硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)等中的一种或它们中两种材料组成的多层复合膜。
步骤三、在完成上述步骤衬底1上,通过化学气相沉积、等离子辅助化学气相淀积或溅射等制备方法沉积薄膜晶体管有源层薄膜,通过构图工艺形成薄膜晶体管有源层20的图形。
其中,有源层20的材料可以为非晶硅、多晶硅、微晶硅或者氧化物半导体。
步骤四、在完成上述步骤的衬底1上,采用溅射的方法形成源漏金属层薄膜,并通过构图工艺形成薄膜晶体管源极31、漏极32和数据线的图形。
其中,所述源漏金属层薄膜的材料可以是钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成的,优先为Mo、Al或含Mo、Al的合金材料。
步骤五、在完成上述步骤的衬底1上,采用化学气相沉积、等离子辅助化学气相淀积、或溅射等制备方法,形成钝化层25,并形成贯穿薄膜晶体管的漏极上方的钝化层25的过孔40。
其中,钝化层的材料为硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)等中的一种或它们中两种材料组成的多层复合膜。
步骤六,在完成上述步骤的衬底1上,采用溅射的方法沉积透明导电金属氧化物膜。然后,通过构图工艺,形成像素电极50的图形,像素电极50通过钝化层25的过孔40与漏极32连接。
其中,透明导电金属氧化物膜的材料为ITO(氧化铟锡)、IZO(氧化铟锌)、IGZO(氧化铟镓锌)或InGaSnO(氧化铟镓锡)。
至此完成阵列基板的制备。
实施例2:
结合图5-7所示,本实施例提供一种阵列基板,该阵列基板包括交叉设置的多条栅线(例如Gi-1、Gi、Gi+1)和多条数据线(例如Dj-1、Dj、Dj+1),以及由相邻栅线和相邻数据线限定的像素单元,每条数据线包括多个数据线线段30,每一数据线线段30对应一个像素单元,且同一数据线的两相邻的数据线线段30通过连接部30a连接;所述栅线的延伸方向与所述数据线线段30的延伸方向的夹角为α;其中,60°≤α≤87°;所述薄膜晶体管的栅极为栅线的凸起结构10,所述凸起结构的靠近像素电极的一侧边的延伸方向与所述栅线的延伸方向的夹角为β,其中,20°≤β≤70°。
由于本实施例阵列基板的栅线的延伸方向和数据线线段30的延伸方向的夹角为α,60°≤α≤87°,所述凸起结构的靠近像素电极的一侧边的延伸方向与所述栅线的延伸方向的夹角为β,20°≤β≤70°,因此该阵列基板可以得到一个优化的视角方向、较高的开口率和较好的显示质量。
本实施例所提供的阵列基板可应用于FFS模式的显示装置中。
具体的,如图5和6所示,由第i行栅线Gi、i+1行栅线Gi+1、第j列数据线Dj、第j+1列数据线Dj+1限定的像素单元Pij为例,其中,与栅线Gi平行的是公共电极线CLi,像素单元Pij包括薄膜晶体管、像素电极50,与该像素电极对应的数据线线段30,数据线线段30的延伸方向与栅线Gi的延伸方向的夹角则为α,薄膜晶体管的栅极为栅线Gi的凸起结构10,所述凸起结构10的靠近像素电极50的一侧边10a的延伸方向与所述栅线Gi的延伸方向的夹角为β。
其中,60°≤α≤87°,20°≤β≤70°。进一步优选地,70°≤α≤85°,30°≤β≤50°。
其中,本实施例的像素电极50为板状电极,其包括第一边50a、第二边50b、第三边50c、第四边50d、第五边50e;其中,所述第一边50a和所述第二边50b平行于所述栅线Gi的延伸方向;所述第三边50c和所述第四边50d平行于所述数据线段30的延伸方向;所述第五边50e平行于所述凸起结构10的靠近像素电极50的一侧边10a的延伸方向。所述栅线的凸起结构10的另一侧边10b位于所述凸起结构10作为栅极的所述薄膜晶体管所在所述像素单元的外侧。所述栅线的凸起结构10的顶边10c与所述凸起结构10作为栅极的所述薄膜晶体管所在所述像素单元对应的数据线线段交叠。此时,不仅可以保证阵列基板较大的开口率,而且还充分利用了像素区的空间。
其中,如图7所示,像素电极50和薄膜晶体管的漏极32采用直接搭接的方式连接。薄膜晶体管的源极31为所述数据线Dj的连接部30a,或者薄膜晶体管的源极31为所述连接部30a的部分结构,特别的是,本实施例中所述数据线Dj的连接部30a的形状为曲线线段。
其中,本实施例中同一条数据线的对应不同像素单元的数据线线段30的延伸方向相互平行。
其中,阵列基板还包括公共电极60,公共电极60设于所述像素电极50上方,且与所述像素电极50绝缘;所述公共电极60具有狭缝60a,所述狭缝60a的延伸方向平行于所述数据线线段30的延伸方向。需要说明的是,狭缝60a的延伸方向应当理解为狭缝主体的中间线的延伸方向,狭缝主体不包括狭缝60a两端的部分,狭缝60a的端部的形状与狭缝主体部分相比可能会有些变化,以便更好控制液晶分子的排列。
相应的,本实施例还针对上述阵列基板提供了一种阵列基板的制备方法,其包括如下步骤:
步骤一、在衬底1上采用溅射的方法沉积一层栅极金属层薄膜,通过构图工艺形成包括薄膜晶体管栅极、栅线和公共电极线的图形。
需要说明的是,衬底1既可以指没有形成任何膜层的衬底,如白玻璃,也可以指形成有其他膜层或者图案的衬底,例如形成有缓冲层的衬底。构图工艺通常包括光刻胶涂敷、曝光、显影、刻蚀、光刻胶剥离等工艺。
其中,所述栅极金属层薄膜的材料可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层,优选为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
步骤二、在完成上述步骤的衬底1上,采用化学气相沉积、等离子辅助化学气相淀积或溅射等制备方法,形成栅极绝缘层15。
其中,所述栅极绝缘层15的材料可以为硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)等中的一种或它们中两种材料组成的多层复合膜。
步骤三,在完成上述步骤的衬底1上,采用溅射的方法沉积透明导电金属氧化物膜。然后,通过构图工艺,形成像素电极50的图形。
其中,透明导电金属氧化物膜的材料为ITO(氧化铟锡)、IZO(氧化铟锌)、IGZO(氧化铟镓锌)或InGaSnO(氧化铟镓锡)。
步骤四、在完成上述步骤衬底1上,通过化学气相沉积、等离子辅助化学气相淀积或溅射等制备方法沉积薄膜晶体管有源层薄膜,通过构图工艺形成薄膜晶体管有源层的图形。
其中,有源层20的材料可以为非晶硅、多晶硅、微晶硅或者氧化物半导体。
步骤五、在完成上述步骤的衬底1上,采用溅射的方法形成源漏金属层薄膜,并通过构图工艺形成薄膜晶体管源极31、漏极32和数据线的图形,其中薄膜晶体管的漏极32与像素电极直接搭接。
其中,所述源漏金属层薄膜的材料可以是钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成的,优先为Mo、Al或含Mo、Al的合金材料。
步骤六、在完成上述步骤的衬底1上,采用化学气相沉积、等离子辅助化学气相淀积、或溅射等制备方法,形成钝化层25。
其中,钝化层的材料为硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)等中的一种或它们中两种材料组成的多层复合膜。
步骤七、在完成上述步骤的衬底1上,采用溅射的方法沉积透明导电金属氧化物膜。然后,通过构图工艺,形成公共电极60的图形。
其中,透明导电金属氧化物膜的材料为ITO(氧化铟锡)、IZO(氧化铟锌)、IGZO(氧化铟镓锌)或InGaSnO(氧化铟镓锡)。
至此完成阵列基板的制备。
实施例3:
本实施例提供一种显示装置,其包括上述阵列基板以及与阵列基板相对合的对盒基板。其中,当阵列基板采用实施例1所述的阵列基板时,该显示装置为TN模式的显示装置,在其对盒基板上还设置有公共电极。阵列基板采用实施例2所述的阵列基板时,该显示装置为FFS模式的显示装置
其中,显示装置可以为液晶显示装置或者电致发光显示装置,例如液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例中的显示装置具有优化的视角方向、较高的开口率和较好的显示质量。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (10)
1.一种阵列基板,其包括交叉设置的多条栅线和多条数据线,以及由相邻栅线和相邻数据线限定的像素单元,所述像素单元包括薄膜晶体管和像素电极,其特征在于,每条数据线包括多个数据线线段,每一数据线线段对应一个像素单元,且同一数据线的两相邻的数据线线段通过连接部连接;所述栅线的延伸方向与所述数据线线段的延伸方向的夹角为α,其中,60°≤α≤87°;所述薄膜晶体管的栅极为栅线的凸起结构,所述凸起结构的靠近所述像素电极的一侧边的延伸方向与所述栅线的延伸方向的夹角为β,其中,20°≤β≤70°;
所述像素电极为板状电极,其包括第一边、第二边、第三边、第四边、第五边;其中,所述第一边和所述第二边平行于所述栅线的延伸方向;所述第三边和所述第四边平行于所述数据线线段的延伸方向;所述第五边平行于所述凸起结构的靠近所述像素电极的一侧边的延伸方向。
2.根据权利要求1所述的阵列基板,其特征在于,70°≤α≤85°,30°≤β≤50°。
3.根据权利要求1所述的阵列基板,其特征在于,所述阵列基板还包括公共电极,所述公共电极设置于所述像素电极上方,且与所述像素电极绝缘;所述公共电极具有狭缝,所述狭缝的延伸方向平行于所述数据线线段的延伸方向。
4.根据权利要求1所述的阵列基板,其特征在于,所述薄膜晶体管的源极为所述连接部,或者为所述连接部的部分结构。
5.根据权利要求1所述的阵列基板,其特征在于,同一条数据线的对应不同像素单元的所述数据线线段的延伸方向相互平行。
6.根据权利要求1所述的阵列基板,其特征在于,所述连接部的形状为曲线线段。
7.根据权利要求1所述的阵列基板,其特征在于,所述栅线的凸起结构的另一侧边位于所述凸起结构作为栅极的所述薄膜晶体管所在所述像素单元的外侧。
8.根据权利要求1所述的阵列基板,其特征在于,所述栅线的凸起结构的顶边与所述凸起结构作为栅极的所述薄膜晶体管所在所述像素单元对应的数据线线段交叠。
9.根据权利要求1所述的阵列基板,所述薄膜晶体管的漏极与所述像素电极通过钝化层过孔连接或直接搭接。
10.一种显示装置,所述显示装置包括阵列基板和与该阵列基板对盒设置的对盒基板,其特征在于,所述阵列基板为权利要求1-9任意一项所述的阵列基板。
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