CN104615192B - 一种强化异步时钟管理的复杂可编程逻辑器件 - Google Patents
一种强化异步时钟管理的复杂可编程逻辑器件 Download PDFInfo
- Publication number
- CN104615192B CN104615192B CN201510035684.3A CN201510035684A CN104615192B CN 104615192 B CN104615192 B CN 104615192B CN 201510035684 A CN201510035684 A CN 201510035684A CN 104615192 B CN104615192 B CN 104615192B
- Authority
- CN
- China
- Prior art keywords
- cpld
- delay
- clock
- phase
- locked loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005728 strengthening Methods 0.000 title claims abstract description 6
- 230000005540 biological transmission Effects 0.000 claims description 4
- 230000010363 phase shift Effects 0.000 abstract description 9
- 238000013461 design Methods 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 230000003111 delayed effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 13
- 238000004891 communication Methods 0.000 description 9
- 230000008054 signal transmission Effects 0.000 description 5
- 230000001934 delay Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (6)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710452686.1A CN107340800B (zh) | 2015-01-23 | 2015-01-23 | 带有延迟反馈回路的cpld |
CN201510035684.3A CN104615192B (zh) | 2015-01-23 | 2015-01-23 | 一种强化异步时钟管理的复杂可编程逻辑器件 |
CN201710452695.0A CN107342764B (zh) | 2015-01-23 | 2015-01-23 | 复杂可编程逻辑器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510035684.3A CN104615192B (zh) | 2015-01-23 | 2015-01-23 | 一种强化异步时钟管理的复杂可编程逻辑器件 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710452686.1A Division CN107340800B (zh) | 2015-01-23 | 2015-01-23 | 带有延迟反馈回路的cpld |
CN201710452695.0A Division CN107342764B (zh) | 2015-01-23 | 2015-01-23 | 复杂可编程逻辑器件 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104615192A CN104615192A (zh) | 2015-05-13 |
CN104615192B true CN104615192B (zh) | 2017-08-11 |
Family
ID=53149688
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710452686.1A Active CN107340800B (zh) | 2015-01-23 | 2015-01-23 | 带有延迟反馈回路的cpld |
CN201510035684.3A Active CN104615192B (zh) | 2015-01-23 | 2015-01-23 | 一种强化异步时钟管理的复杂可编程逻辑器件 |
CN201710452695.0A Active CN107342764B (zh) | 2015-01-23 | 2015-01-23 | 复杂可编程逻辑器件 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710452686.1A Active CN107340800B (zh) | 2015-01-23 | 2015-01-23 | 带有延迟反馈回路的cpld |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710452695.0A Active CN107342764B (zh) | 2015-01-23 | 2015-01-23 | 复杂可编程逻辑器件 |
Country Status (1)
Country | Link |
---|---|
CN (3) | CN107340800B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107844672B (zh) * | 2017-12-06 | 2023-11-28 | 西安智多晶微电子有限公司 | 时钟树单元、时钟网络结构及fpga时钟结构 |
CN111835345B (zh) * | 2020-07-30 | 2024-07-12 | 云知声智能科技股份有限公司 | Dll控制电路及控制方法 |
CN113325918B (zh) * | 2021-06-15 | 2022-09-27 | 展讯通信(上海)有限公司 | 时钟管理电路、芯片及电子设备 |
CN114253346A (zh) * | 2021-12-09 | 2022-03-29 | 杭州长川科技股份有限公司 | 时序信号发生器及其校准系统和方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6651181B1 (en) * | 2000-03-29 | 2003-11-18 | Cypress Semiconductor Corp. | Clocking scheme for programmable logic device |
CN1801625A (zh) * | 2004-11-08 | 2006-07-12 | 三星电子株式会社 | 延时锁定环路及具有该延时锁定环路的半导体存储器 |
CN101504861A (zh) * | 2009-03-16 | 2009-08-12 | 东南大学 | 全数字延时锁定环电路 |
CN103677077A (zh) * | 2013-12-18 | 2014-03-26 | 西安智多晶微电子有限公司 | 强化时钟管理的复杂可编程逻辑器件 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7109765B1 (en) * | 1998-11-03 | 2006-09-19 | Altera Corporation | Programmable phase shift circuitry |
EP1214788B1 (de) * | 1999-09-22 | 2003-03-26 | Siemens Aktiengesellschaft | Integrierter schaltkreis mit zumindest zwei taktsystemen |
JP4745127B2 (ja) * | 2006-05-23 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | クロック切替回路 |
US8310292B1 (en) * | 2011-07-13 | 2012-11-13 | Nanya Technology Corp. | Method for resetting DLL with frequency change application |
CN102624383A (zh) * | 2012-04-06 | 2012-08-01 | 南通金枫电气有限公司 | 数字锁相移相触发电路 |
-
2015
- 2015-01-23 CN CN201710452686.1A patent/CN107340800B/zh active Active
- 2015-01-23 CN CN201510035684.3A patent/CN104615192B/zh active Active
- 2015-01-23 CN CN201710452695.0A patent/CN107342764B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6651181B1 (en) * | 2000-03-29 | 2003-11-18 | Cypress Semiconductor Corp. | Clocking scheme for programmable logic device |
CN1801625A (zh) * | 2004-11-08 | 2006-07-12 | 三星电子株式会社 | 延时锁定环路及具有该延时锁定环路的半导体存储器 |
CN101504861A (zh) * | 2009-03-16 | 2009-08-12 | 东南大学 | 全数字延时锁定环电路 |
CN103677077A (zh) * | 2013-12-18 | 2014-03-26 | 西安智多晶微电子有限公司 | 强化时钟管理的复杂可编程逻辑器件 |
Also Published As
Publication number | Publication date |
---|---|
CN107342764A (zh) | 2017-11-10 |
CN107340800A (zh) | 2017-11-10 |
CN107342764B (zh) | 2020-06-12 |
CN104615192A (zh) | 2015-05-13 |
CN107340800B (zh) | 2019-06-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103947116A (zh) | 用于恢复阵发模式脉宽调制(pwm)和非归零(nrz)数据的装置和方法 | |
US6002279A (en) | Clock recovery circuit | |
CN103229420B (zh) | 跨着倍频程边界具有同步范围扩展的分频器 | |
CN101465723B (zh) | 具有降低的延迟时间不确定性的收发器系统、包含该收发器系统的可编程逻辑器件和数字系统以及收发数据的方法 | |
CN104615192B (zh) | 一种强化异步时钟管理的复杂可编程逻辑器件 | |
US7109756B1 (en) | Synchronization of programmable multiplexers and demultiplexers | |
CN100555874C (zh) | 分数n频率合成器内的数字增量求和调制器 | |
CN103105889B (zh) | 一种fpga原型验证板堆叠的时钟同步装置及系统 | |
US9654123B1 (en) | Phase-locked loop architecture and clock distribution system | |
EP1575170A1 (en) | Highly configurable pll architecture for programmable logic device | |
CN101378258B (zh) | 一种模块化分频单元及分频器 | |
CN1996762A (zh) | 一种分数分频器 | |
CN103823778A (zh) | 异构高速串行接口系统架构 | |
CN107528584A (zh) | 复用延迟线的高精度数字延时锁相环 | |
CN107222210A (zh) | 一种可由spi配置数字域时钟相位的dds系统 | |
CN101841332A (zh) | 一种数字锁相环 | |
US6934347B2 (en) | Method for recovering a clock signal in a telecommunications system and circuit thereof | |
CN102394640A (zh) | 延时锁定环电路及快速锁定算法 | |
CN110209625A (zh) | 一种基于低频参考信号的片上同步自修复系统 | |
CN112636751A (zh) | SerDes模块时钟网络架构 | |
CN102916700B (zh) | 数据传输装置及方法 | |
CN102111150B (zh) | 一种用于鉴频鉴相器的数字边沿对齐器 | |
WO2016071813A2 (en) | Digitally controlled oscillator (dco) architecture | |
US7151810B2 (en) | Data and clock synchronization in multi-channel communications | |
CN103677077A (zh) | 强化时钟管理的复杂可编程逻辑器件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Complex programmable logic device enhancing asynchronous clock management Effective date of registration: 20180824 Granted publication date: 20170811 Pledgee: Pudong Development Bank of Shanghai, Limited by Share Ltd, Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, INC. Registration number: 2018610000136 |
|
PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20201228 Granted publication date: 20170811 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: 2018610000136 |