CN104601155B - 开关电路 - Google Patents

开关电路 Download PDF

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Publication number
CN104601155B
CN104601155B CN201410595130.4A CN201410595130A CN104601155B CN 104601155 B CN104601155 B CN 104601155B CN 201410595130 A CN201410595130 A CN 201410595130A CN 104601155 B CN104601155 B CN 104601155B
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Prior art keywords
switching circuit
voltage
transistor
enhancement mode
circuit according
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CN104601155A (zh
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R.奥特伦巴
R.桑德
K.席斯
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

开关电路。在实施例中，开关电路包括输入漏极、源极和栅极节点、包括与低电压增强模式晶体管的电流路径串联耦合的电流路径的高电压耗尽模式晶体管、以及用于检测开关电路的过热的过热检测电路。

Description

开关电路
背景技术
迄今为止，在功率电子应用中使用的晶体管通常已经用硅（Si）半导体材料来制造。用于功率应用的公共晶体管器件包括Si CMOS（CoolMOS）、Si功率MOSFET和Si绝缘栅双极晶体管（IGBT）。例如III-V化合物半导体（诸如GaAs）的化合物半导体在一些应用中也是有用的。最近，碳化硅（SiC）功率器件已经被考虑。诸如氮化镓（GaN）器件的III-N族半导体器件现在作为有吸引力的候选物出现以携带大电流，支持高电压并提供非常低的接通电阻和快开关时间。
发明内容
在实施例中，开关电路包括输入漏极、源极和栅极节点、包括与低电压增强模式晶体管的电流路径串联耦合的电流路径的高电压耗尽模式晶体管、以及用于检测开关电路的过热的过热检测电路。
附图说明
附图的元件不一定相对于彼此成比例。相同的参考数字表示对应的相同部分。各种所示实施例的特征可组合，除非它们排斥彼此。实施例在附图中被描绘并在接下来的描述中被详述。
图1图示根据实施例的开关电路。
图2图示包括栅地阴地放大器布置的开关电路的示意图。
图3图示开关电路的示意图。
图4图示根据实施例的包括两个封装的开关电路。
图5图示根据实施例的包括单个复合封装的开关电路。
图6图示根据实施例的单片集成开关电路。
图7图示根据实施例的单片集成开关电路。
具体实施方式
在下面的详细描述中，参考形成其一部分的附图，且其中通过例证示出其中本公开可被实践的特定实施例。在这个方面中，参考正被描述的一个或多个图的方位来使用方向术语，诸如“顶部”、“底部”、“前面”、“后面”、“最前部”、“尾部”等。因为实施例的部件可被定位于多个不同的方位中，所以方向术语用于说明的目的且决不是限制性的。将理解，其它实施例可被利用，且结构或逻辑改变可被做出而不脱离本发明的范围。其下面的详细描述不应在限制的意义上被理解，且本发明的范围由所附权利要求限定。
如在这个说明书中采用的，术语“耦合的”和/或“电耦合的”并不打算意指元件必须直接耦合在一起，插入元件可被提供在“耦合的”或“电耦合的”元件之间。
诸如高电压耗尽模式晶体管的耗尽模式器件具有负阈值电压，这意味着它可在零栅极电压下传导电流。这些器件在正常情况下是接通的。而诸如低电压增强模式晶体管的增强模式器件具有正阈值电压，这意味着它在零栅极电压下不能传导电流且在正常情况下是断开的。
如在本文使用的，诸如高电压耗尽模式晶体管的“高电压器件”是为高电压开关应用优化的电子器件。也就是说，当晶体管断开时，它能够闭塞高电压，诸如大约300 V或更高、大约600 V或更高或者大约1200 V或更高，且当晶体管接通时，它对于其中它被使用的应用具有足够低的接通电阻（RON），即，它在相当大的电流穿过器件时经历足够低的传导损耗。高电压器件可至少能够闭塞等于高电压供电的电压或在它所用于的开关电路中的最大电压。高电压器件可能能够闭塞300 V、600 V、1200 V或应用所需的其它合适的闭塞电压。
如在本文使用的，诸如低电压增强模式晶体管的“低电压器件”是能够闭塞诸如在0 V和Vlow之间的低电压但不能够闭塞高于Vlow的电压的电子器件，Vlow可以是大约10 V、大约20 V、大约30 V、大约40 V或在大约5 V和50 V之间，诸如在大约10 V和30 V之间。
如在本文使用的，例如，化合物半导体器件可包括形成诸如绝缘栅FET（IGFET）的场效应晶体管（FET）或高电子迁移率晶体管（HEMT）的任何合适的半导体材料。合适的半导体材料包括诸如SiGe、SiC和III-V族材料的化合物半导体材料，所述III-V族材料包括III族砷化物、III族磷化物、III族氮化物或任何其合金。因此，短语“III-V族”指的是包括V族元素和至少一种III族元素的化合物半导体。而且，例如，短语“III族氮化物”指的是包括氮（N）和至少一种III族元素（所述III族元素包括铝（Al）、镓（Ga）、铟（In）和硼（B）且包括但不限于任何其合金）的化合物半导体，诸如，氮化铝镓（AlxGa(1-x)N）、氮化铟镓（InyGa(1-y)N）、氮化铝铟镓（AlxInyGa(1-x-y)N）、氮化镓砷磷（GaAsaPbN(1-a-b)）和氮化铝铟镓砷磷（AlxInyGa(1-x-y)AsaPbN(1-a-b)）。III族氮化物也一般指的是任何极性，其包括但不限于Ga极性、N极性、半极性或非极性晶体取向。
氮化铝镓指的是由化学式AlxGa(1-x)N描述的合金，其中x > 1。
这些半导体材料是具有相对宽的直接带隙并具有高临界击穿场、高饱和漂移速度和良导热性的半导体化合物。作为结果，诸如GaN的III氮化物材料在很多微电子应用中被使用，在所述微电子应用中要求高功率密度和高效率开关。
图1图示根据实施例的开关电路10。开关电路10包括输入漏极节点11、输入源极节点12、输入栅极节点13、包括与低电压增强模式晶体管17的电流路径16串联耦合的电流路径15的高电压耗尽模式晶体管14。开关电路还包括用于检测开关电路10的过热的过热检测电路18。
提供包括温度感测功能和过热保护的开关电路10。过热检测电路18可作为分开的部件被提供，并被放置成使得它与开关电路10热耦合，或过热检测电路19可至少部分地集成在低电压增强模式晶体管17中，且因此与开关电路10热耦合。高电压耗尽模式晶体管14与低电压增强模式晶体管17热耦合，使得过热检测电路可检测高电压耗尽模式晶体管14和/或低电压增强模式晶体管17的过热。
低电压增强模式晶体管17可以是IGFET（绝缘栅场效应晶体管），例如p沟道MOSFET。
高电压耗尽模式晶体管14可以是基于III族氮化物的晶体管或基于III族氮化物的高电子迁移率晶体管（HEMT）。
过热检测电路18可包括具有预先确定的温度相关电压特性的偏置pn结。pn结可以是正向偏置或反向偏置的。
在实施例中，偏置pn结集成在半导体衬底中，且特别是在与低电压增强模式晶体管17相同的半导体衬底中。低电压增强模式晶体管17可包括彼此并联连接并集成在半导体衬底中的多个晶体管单元。偏置pn结可集成在同一半导体衬底中。
在实施例中，低电压增强模式晶体管17包括彼此并联连接并集成在半导体衬底中的多个晶体管单元，以及集成在同一半导体衬底中的正向偏置pn结。正向偏置pn结具有与结温度成反比的电压降。
开关电路10还可包括耦合到正向偏置pn结的用于产生与电压降成比例的电压的电压装置。
过热检测电路18可包括用于接收电压并在电压超过阈值电压时产生用来指示低电压增强模式晶体管17过热的信号的阈值装置。
在实施例中，低电压增强模式晶体管17包括彼此并联连接并集成在半导体衬底中的多个晶体管单元，以及集成在同一半导体衬底中的反向偏置pn结。反向偏置pn结具有温度相关的泄漏电流。开关电路10还可包括耦合到反向偏置pn结的用于产生与反向泄漏电流成比例的电压的电压装置。过热检测电路18可包括用于接收电压并用于在电压超过阈值电压时产生用来指示低电压增强模式晶体管17过热的信号的阈值装置。
过热检测电路18还可包括第一过热检测焊盘和可选地第二过热检测焊盘，这两个过热检测焊盘被定位于半导体衬底上并耦合到偏置pn结。
开关电路10还可包括至少一个过热检测节点。
高电压模式耗尽晶体管14可在栅地阴地放大器布置中操作地连接到低电压增强模式晶体管17。
在实施例中，高电压耗尽模式晶体管14被直接驱动。
高电压耗尽模式晶体管14和低电压增强模式晶体管17可具有不同的布置。
在实施例中，高电压耗尽模式晶体管14可作为分立部件被提供，且低电压增强模式晶体管17可作为分立部件被提供。
在实施例中，高电压耗尽模式晶体管和低电压增强模式晶体管相邻于彼此安装在复合封装中。
在实施例中，高电压耗尽模式晶体管14和低电压增强模式晶体管17被单片地集成。
开关电路10的高电压耗尽模式晶体管14在操作中在正常情况下是接通的。在高电压耗尽模式晶体管14在正常情况下断开是期望的实施例中，这可通过在栅地阴地放大器布置中将高电压耗尽模式晶体管14操作地连接到低电压增强模式晶体管17来实现。
图2图示包括这样的栅地阴地放大器布置的开关电路30的示意图。
在开关电路20中，在正常情况下接通的高电压耗尽模式晶体管21与在正常情况下断开的低电压增强模式晶体管22组合，以形成在正常情况下断开的混合器件。
高电压耗尽模式晶体管21包括源极23、漏极24和栅极25。低电压增强模式晶体管22也包括源极26、漏极27和栅极28。
高电压耗尽模式晶体管21的源极23电耦合到低电压增强模式晶体管22的漏极27。高电压耗尽模式晶体管21的栅极25在栅地阴地放大器配置中与低电压增强模式晶体管22的源极26电耦合。
高电压耗尽模式晶体管21和低电压增强模式晶体管22可被提供在单个封装中或在图2中用虚线29示意性图示的复合半导体主体中。
开关电路包括输入源极节点30、输入栅极节点31和输入漏极节点32。源极节点30可被表示为低电压引线，且漏极节点32可被表示为高电压引线。在图2中所示的示例中，0 V可被施加到低电压引线40而600 V可被施加到高电压引线32。
低电压增强模式晶体管22的源极26和高电压耗尽模式晶体管21的栅极25都电耦合到源极节点30。低电压增强模式晶体管22的栅极28电耦合到栅极节点31，并可由耦合到栅极节点31的栅极驱动器电路驱动。高电压耗尽模式晶体管22的漏极24电耦合到漏极节点22。
开关电路20还包括用于检测开关电路20的过热的过热检测电路33。过热检测电路33可例如通过与低电压增强模式晶体管22热接触而热耦合到开关电路。过热检测电路可至少部分地集成在低电压增强模式晶体管22中。
过热检测电路33耦合到开关电路20的感测节点36。
图3图示开关电路40的示意图，其中高电压耗尽模式晶体管21的栅极25被直接驱动，而不是在栅地阴地放大器配置中与低电压增强模式晶体管22的源极25电耦合，以便提供混合的在正常情况下断开的开关电路40。
开关电路40还包括电耦合到高电压耗尽模式晶体管21的栅极25的第二栅极节点41。通过使用第二栅极节点41来直接控制栅极25。开关电路40还包括耦合到感测电路33的第二感测节点42。
开关电路40可由使用图3中的虚线43和44指示的两个分立部件提供。部件43、44可由分开的半导体封装或由安装在用来提供复合封装的公共封装中的分开的半导体晶体管器件提供。在图3所示的开关电路40中，过热检测电路33与低电压增强模式晶体管22相关，并可单片地集成在低电压增强模式晶体管22中。
过热检测电路33可包括热耦合到开关电路的pn结。Pn结可由集成在例如低电压增强模式晶体管22中的二极管111提供。pn结可以是正向偏置或反向偏置的，且在任一情况下具有可用于检测pn结的温度的预先确定的温度相关电压特性。
如果所检测的温度超过预先确定的阈值，则这可意味着低电压增强模式晶体管22和/或高电压耗尽模式晶体管23过热，因为pn结与低电压增强模式晶体管22和高电压耗尽模式晶体管23热耦合。在这种情况下，开关电路20可被断开。
如上面讨论的，具有过热检测电路的开关电路可由具有各种布置的高电压耗尽模式晶体管和低电压增强模式晶体管形成。
图4图示根据实施例的开关电路50，其中高电压耗尽模式晶体管51被提供在第一封装52中，且低电压增强模式晶体管53被提供在与第一封装52分离的第二封装54中。
低电压增强模式晶体管53是包括在其下表面上的漏极焊盘55和在其上表面上的源极焊盘63、栅极焊盘64和感测焊盘65的垂直MOSFET器件。
高电压耗尽模式晶体管51是基于氮化镓的HEMT并包括在其上表面上的源极焊盘56、栅极焊盘67和漏极焊盘66。
低电压增强模式晶体管53的漏极焊盘55电耦合到高电压耗尽模式晶体管51的源极焊盘56，以便将低电压增强模式晶体管53的电流路径57与高电压耗尽模式晶体管51的电流路径58串联耦合。
导电连接器59可用于将第二封装54的外部触头60（其耦合到低电压增强模式晶体管53的漏极焊盘55）耦合到第二封装52的外部触头61（其耦合到高电压耗尽模式晶体管51的源极焊盘56）。导电连接器59被定位于两个封装52、54外部。导电连接器59可由例如电路板的导电迹线提供。开关电路50还包括过热检测电路62，其在包括其的图4中所示的实施例中单片地集成在低电压增强模式晶体管53中。
使用低电压增强模式晶体管53的分立封装和高电压耗尽模式晶体管51的分开的分立封装52来形成开关电路50可使得能够使用待耦合在一起的标准部件以形成开关电路50。
高电压耗尽模式晶体管的栅极焊盘67在栅地阴地放大器配置中耦合到低电压增强模式晶体管的源极焊盘63。开关电路50包括耦合到低电压增强模式晶体管53的源极63的输入源极节点、耦合到高电压耗尽模式晶体管的漏极焊盘66的输入漏极节点、电耦合到低电压增强模式晶体管53的栅极焊盘64的栅极节点和电耦合到过热检测电路62的感测焊盘65的感测节点。
图5图示根据实施例的开关电路70。开关电路70包括垂直MOSFET的形式的低电压增强模式晶体管71和基于氮化镓的HEMT的形式的高电压耗尽模式晶体管72，这两个晶体管在公共封装73内相邻于彼此布置以形成复合封装。
低电压增强模式晶体管71包括在其上表面上的源极焊盘74、栅极焊盘75、第一温度感测焊盘76和第二温度感测焊盘77和在其下表面上的漏极焊盘78。高电压耗尽模式晶体管包括在其上表面上的源极焊盘79、栅极焊盘80和漏极焊盘81。
低电压增强模式晶体管71的漏极焊盘78电耦合到高电压耗尽模式晶体管72的源极焊盘79，且高电压耗尽模式晶体管72的栅极焊盘80在栅地阴地放大器配置中电耦合到低电压增强模式晶体管71的源极焊盘74。
复合封装73包括电耦合到低电压增强模式晶体管71的源极焊盘74的源极节点、电耦合到高电压耗尽模式晶体管72的漏极焊盘81的漏极节点、电耦合到低电压增强模式晶体管71的栅极焊盘75的栅极节点、电耦合到第一温度感测焊盘76的第一温度感测节点和电耦合到第二温度感测焊盘77的第二温度感测节点。
复合封装73和因此开关电路70还包括用于检测开关电路的过热的过热检测电路82。过热检测电路82至少部分地被布置在低电压增强模式晶体管71中。
如果过热检测电路82检测到温度已经超过预先确定的阈值，则这可意味着低电压增强模式晶体管71和/或高电压耗尽模式晶体管72可能将要遭受故障或正在出故障。这个信息可用于断开开关电路80。
因为低电压增强模式晶体管71、高电压耗尽模式晶体管72和过热检测电路82被布置在复合封装中，所以复合封装可被考虑为包括在正常情况下断开的混合器件，其包括温度感测功能和过热保护。
图6图示根据实施例的开关电路90，其包括基于硅的MOSFET器件的形式的低电压增强模式晶体管91和基于氮化镓的HEMT的形式的高电压耗尽模式晶体管92以及过热检测电路93。
在这个实施例中，低电压增强模式晶体管91和高电压耗尽模式晶体管92被单片地集成以形成复合部件94。
基于硅的低电压增强模式晶体管91可用作用于随后沉积高电压耗尽模式晶体管92的衬底。可在低电压增强晶体管91和高电压耗尽模式晶体管92之间的接口95处提供开关电路90所需的在低电压增强模式晶体管91的漏极焊盘和高电压耗尽模式晶体管92的源极之间的电连接。
图7图示开关电路100的更详细视图，开关电路100包括与高电压耗尽模式晶体管102单片地集成的低电压增强模式晶体管101并提供如例如图2所示的开关电路。开关电路100可作为单个封装被提供。
低电压增强模式晶体管101是基于硅的MOSFET器件，其包括在其下表面上的源极焊盘103、栅极焊盘104和感测焊盘105以及在其上表面上的由硅主体107的高掺杂区形成的漏极电极106。低电压增强模式晶体管101包括在硅主体107内的多个晶体管单元112。晶体管单元112彼此并联连接并集成在硅主体107中。
开关电路100包括至少部分地集成在低电压增强模式晶体管101的硅主体107中的过热检测电路109。
感测电路109还包括耦合到过热检测电路的温度感测焊盘105。在一些实施例中，过热检测电路109还包括在硅主体107上的第二感测焊盘。
开关电路100还包括集成在半导体主体107中的用于检测逻辑113是否检测到温度已经超过预先确定的阈值的逻辑113，这可意味着低电压增强模式晶体管101和/或高电压耗尽模式晶体管102可能将要遭受故障或正在出故障。这个信息可用于断开开关电路100。
开关电路100还包括与低电压增强模式晶体管101单片地集成的高电压耗尽模式晶体管102。高电压耗尽模式晶体管102在这个实施例中是基于氮化镓的HEMT，其包括沉积在低电压增强模式晶体管的漏极106上并与低电压增强模式晶体管的漏极106单片地集成的氮化镓层114。硅主体107可被考虑为沉积在顶部上的HEMT提供半导体衬底。高电压耗尽模式晶体管102还包括布置在氮化镓层114上的氮化铝镓层115和布置在氮化铝镓层115上的氮化镓保护层116。
高电压耗尽模式晶体管包括源极117，其穿过保护层116、氮化铝镓层115和氮化镓层114延伸并被布置在低电压增强模式晶体管101的漏极106上并与低电压增强模式晶体管101的漏极106电耦合。高电压耗尽模式晶体管102还包括漏极电极118，其穿过保护层116和氮化铝镓层115延伸并与氮化镓层114接触。高电压耗尽模式晶体管102还包括栅极电极119，其被布置在保护层116上并横向地被定位于源极电极117和漏极电极118之间。在氮化铝镓层115和氮化镓层114之间的接口120处通过自发极化形成二维气体。氮化镓层114可被考虑为沟道层，且氮化铝镓可被考虑为阻挡层。
开关电路100还包括在高电压耗尽模式晶体管102的栅极电极119和导电迹线121之间的例如接合线128的形式的电连接，低电压增强模式晶体管101的源极焊盘103被安装在导电迹线121上。因此，高电压耗尽模式晶体管102的栅极电极119在栅地阴地放大器配置中电耦合到低电压增强模式晶体管101的源极103。高电压耗尽模式晶体管102的漏极电极118通过另外的电连接（例如夹片123）电耦合到漏极迹线122。
低电压增强模式晶体管具有源极向下的布置，使得源极焊盘103例如通过焊料安装在衬底129的迹线122上，且栅极焊盘104和温度感测焊盘105例如通过焊料安装在布置在衬底129上的另外的迹线124。
开关电路100包括电耦合到漏极迹线121的漏极节点、电耦合到迹线120的源极节点、电耦合到迹线122的栅极节点，迹线122耦合到栅极焊盘104。感测焊盘105由接合线123耦合到逻辑113。逻辑113进一步由接合线126耦合到两个另外的迹线124、125。
衬底129可以是再分布板或引线框。
开关电路100的过热检测电路109包括集成在硅主体107中的pn结。pn结110可由例如集成在硅主体107中的二极管111提供。pn结110可以是正向偏置或反向偏置的，且在任一情况下具有可用于检测pn结110的温度的预先确定的温度相关特性。
因为pn结110集成在硅主体107中，pn结110的温度实质上与低电压增强模式晶体管101的温度相同。因为低电压增强模式晶体管101与高电压耗尽模式晶体管102热耦合，过热检测电路109也热耦合到高电压增强模式晶体管102，并可提供对低电压增强模式晶体管101和高电压耗尽模式晶体管102两者的过热保护，如果晶体管中的一个或两者过热。
在实施例中，pn结110是正向偏置的，并具有与结温度成反比的电压降。过热检测电路109还包括耦合到正向偏置pn结110的用于产生与电压降成比例的电压的电压装置。过热检测电路109还包括用于接收由电压装置产生的电压并用于在电压超过阈值电压时产生用来指示温度已经超过预先确定的阈值的信号的阈值装置。如果温度超过预先确定的阈值，这可意味着低电压增强模式晶体管101和/或高电压耗尽模式晶体管过热。在这种情况下，逻辑113可确定开关电路100应被断开并断开开关电路100。
在实施例中，过热检测电路109的pn结110是反向偏置的，并具有温度相关的反向泄漏电流。在这个实施例中，过热检测电路109可包括耦合到反向偏置pn结110的用于产生与反向泄漏电流成比例的电压的电压装置。过热检测电路109也可包括用于从电压装置接收电压并用于在电压超过阈值电压时产生指示温度已经超过预先确定的阈值温度的信号的阈值装置。如果温度超过预先确定的阈值，这可意味着低电压增强模式晶体管101和/或高电压耗尽模式晶体管过热。在这种情况下，逻辑113可确定开关电路100应被断开。
空间相对术语（诸如“在……下”、“在……之下”、“下部”、“在……之上”、“上部”等）用于容易描述以解释一个元件相对于第二元件的定位。除了与在图中描绘的方位不同的方位以外，这些术语意图包括器件的不同方位。
此外，术语（诸如“第一”、“第二”等）也用于描述各种元件、区、区段等，并且也并不意在为限制性的。相同的术语指的是遍及该描述的相同的元件。
如在本文使用的，术语“具有”、“包含”、“包括”、“由……组成”等是指示所陈述的元件或特征的存在的开放性术语，而不排除附加的元件或特征。冠词“一”、“一个”和“该”意在包括复数以及单数，除非上下文另有清楚的指示。
将理解，本文描述的各种实施例的特征可彼此组合，除非另有明确说明。
虽然已经在本文图示和描述了特定实施例，本领域中的普通技术人员将认识到，多种替换和/或等效实现可代替所示和所述的特定实施例，而不脱离本发明的范围。本申请意在涵盖在本文讨论的特定实施例的任何改编或变化。因此，意图是本发明仅由权利要求及其等效形式限制。

Claims (17)

1.一种开关电路，包括：
输入漏极、源极和栅极节点；
耗尽模式晶体管，其包括与增强模式晶体管的电流路径串联耦合的电流路径，所述耗尽模式晶体管具有比所述增强模式晶体管更高的闭塞电压能力；以及
用于检测所述开关电路的过热的过热检测电路；
其中所述增强模式晶体管是IGFET；
其中所述耗尽模式晶体管是基于III族氮化物的晶体管；
其中所述增强模式晶体管包括彼此并联连接并集成在半导体衬底中的多个晶体管单元，以及集成在同一半导体衬底中的具有预先确定的温度相关电压特性的偏置pn结。
2.根据权利要求1所述的开关电路，其中所述IGFET是p沟道MOSFET。
3.根据权利要求1所述的开关电路，其中所述过热检测电路至少部分地集成在所述增强模式晶体管中。
4.根据权利要求1所述的开关电路，其中所述增强模式晶体管包括彼此并联连接并集成在半导体衬底中的多个晶体管单元，以及集成在同一半导体衬底中的正向偏置pn结，所述正向偏置pn结具有与结温度成反比的电压降。
5.根据权利要求4所述的开关电路，还包括耦合到所述正向偏置pn结的用于产生与所述电压降成比例的电压的电压装置。
6.根据权利要求5所述的开关电路，其中所述过热检测电路包括用于接收所述电压并在所述电压超过阈值电压时产生用来指示所述增强模式晶体管过热的信号的阈值装置。
7.根据权利要求1所述的开关电路，其中所述增强模式晶体管包括彼此并联连接并集成在半导体衬底中的多个晶体管单元，以及集成在同一半导体衬底中的反向偏置pn结，所述反向偏置pn结具有温度相关的反向泄漏电流。
8.根据权利要求7所述的开关电路，还包括耦合到所述反向偏置pn结的用于产生与所述反向泄漏电流成比例的电压的电压装置。
9.根据权利要求8所述的开关电路，其中所述过热检测电路包括用于接收所述电压并用于在所述电压超过阈值电压时产生用来指示所述增强模式晶体管过热的信号的阈值装置。
10.根据权利要求1所述的开关电路，其中所述过热检测电路还包括在所述半导体衬底上并耦合到所述偏置pn结的第一过热检测焊盘和第二过热检测焊盘。
11.根据权利要求1所述的开关电路，还包括至少一个过热检测节点。
12.根据权利要求1所述的开关电路，其中所述耗尽模式晶体管在栅地阴地放大器布置中操作地连接到所述增强模式晶体管。
13.根据权利要求1所述的开关电路，其中所述耗尽模式晶体管被直接驱动。
14.根据权利要求1所述的开关电路，其中所述耗尽模式晶体管作为分立部件被提供，且所述增强模式晶体管作为分立部件被提供。
15.根据权利要求1所述的开关电路，其中所述耗尽模式晶体管和所述增强模式晶体管相邻于彼此安装在复合封装中。
16.根据权利要求1所述的开关电路，其中所述耗尽模式晶体管和所述增强模式晶体管被单片集成。
17.根据权利要求1所述的开关电路，其中所述耗尽模式晶体管是基于III族氮化物的高电子迁移率晶体管HEMT。
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