CN104538371A - Semiconductor chip capsule with high reliability and low cost - Google Patents
Semiconductor chip capsule with high reliability and low cost Download PDFInfo
- Publication number
- CN104538371A CN104538371A CN201510015604.8A CN201510015604A CN104538371A CN 104538371 A CN104538371 A CN 104538371A CN 201510015604 A CN201510015604 A CN 201510015604A CN 104538371 A CN104538371 A CN 104538371A
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- low cost
- high reliability
- metal layer
- semiconductor
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor chip capsule with high reliability and low cost, and relates to the technical field of semiconductor packing. The semiconductor chip capsule comprises a pedestal, a tube cap and a cap sealing adhesive. The pedestal and the tube cap are both made of a raw material of a circuit board, the tube cap is a hollow sealed case, one side of the case is provided with a groove, and a groove edge on the cap is connected with the pedestal through the cap sealing adhesive. An obverse side grounding metal layer and a reverse side grounding metal layer are spread on the upper surface and the lower surface of the pedestal respectively. The two ends of the pedestal are each provided with an obverse side leading wire and a reverse side leading wire. The pedestal is provided with a plurality of vertically-through plate holes, and the plate holes comprise metal connection pieces connecting the obverse side grounding metal layer and the reverse side grounding metal layer. A semiconductor chip is bonded on the obverse side grounding metal layer through conductive adhesive, bonding pressing points of the semiconductor chip are electrically connected with the obverse side leading wire through bonding wires, and the upper surface of the semiconductor chip is coated with protection rubber. The semiconductor chip capsule with high reliability and low cost can pass the rigorous HAST and has the advantages of low cost and high reliability.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation.
Background technology
Packaging body plays the effect of protection semiconductor chip, semiconductor chip can be isolated from the outside, prevent the corrosion of the impurity in air to chip circuit from causing the decline of electric property.Along with the development of electron trade, the application of chip is more and more extensive, also more and more higher to the requirement of environmental suitability, can packaging pass through the hot and humid limit accelerated life test of HAST(Highly Accelerated Temperature/Humidity Stress Test), be the important indicator weighing product reliability at present.Existing capsulation body of semiconductor ship mainly contains plastic sealed and ceramic-type, although plastic sealed with low cost, but when carrying out HAST experiment, owing to adopting capsulation material encapsulation, cause the product produced in batches due to water absorption rate difference, always there is portioned product not by HAST experiment, have impact on the rate of finished products of product, reduce the reliability of product.And although plastic sealed capsulation body of semiconductor ship reliability is higher, cost is also higher.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of capsulation body of semiconductor ship of high reliability and low cost, can by harsh HAST, and with low cost, reliability is high.
For solving the problems of the technologies described above, the technical solution used in the present invention is:
A kind of capsulation body of semiconductor ship of high reliability and low cost, comprise base, pipe cap and sealing cap glue, described base and pipe cap all adopt circuit board raw material to make, and described pipe cap is hollow enclosure, box one side is provided with groove, and the groove limit of pipe cap is connected with base by sealing cap glue; The upper surface of described base and lower surface are all covered with front ground metal layer and back-side ground metal level, two ends are equipped with front lead-in wire and back side lead-in wire, described base is also provided with several up and down in logical dish mesopore, described dish mesopore comprises metal connecting piece front ground metal layer be connected with back-side ground metal level; Semiconductor chip is by conductive adhesive in the ground metal layer of front, and the bonding pressure point of semiconductor chip is gone between by bonding line and front and is electrically connected; Described semiconductor chip upper surface is coated with protecting glue.
Further technical scheme, described dish mesopore is circular port, adopts metallization process to connect the circuit on circular port both sides, is added with filler in dish mesopore.
Further technical scheme, the non-recessed face of described pipe cap is coated with metal level.
Further technical scheme, the quantity of described semiconductor chip is at least two, is electrically connected between described semiconductor chip by bonding line.
Further technical scheme, described protecting glue is do not react and the silicon rubber of good waterproof performance with chip.
The beneficial effect adopting technique scheme to produce is: the present invention adopts general circuit board material as raw material, is made into pipe cap and base, and graphic making adopts ripe circuit board processing technology, with low cost; Bottom adopts plated-through hole to carry out ground connection, and hole fills up by employing dish mesopore technique, reaches the object of sealing, ensures passing through of HAST; Adopt sealing cap glue to connect base and pipe cap, avoid moisture to enter package interior, ensure passing through of HAST; Meanwhile, the upper surface of semiconductor chip applies one deck protecting glue, avoids moisture attack semiconductor chip, ensures passing through of HAST further; Two kinds of waterproof measures, further increase the reliability of semiconductor chip.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embodiment of the present invention 1;
Fig. 2 is the outline drawing of the embodiment of the present invention 1;
Fig. 3 is the structural representation of the embodiment of the present invention 2;
In the accompanying drawings: 1, base, 2, pipe cap, 3, sealing cap glue; 4, front lead-in wire, 5, dish mesopore, 6, the back side lead-in wire; 7, front ground metal layer, 8, back-side ground metal level, 9, semiconductor chip; 10, conducting resinl, 11, bonding pressure point, 12, bonding line; 13, protecting glue; 14, groove, 15, metal level, 16, filler.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Embodiment 1
As shown in Figure 1, a kind of capsulation body of semiconductor ship of high reliability and low cost, comprises base 1, pipe cap 2 and sealing cap glue 3, and sealing cap glue 3 is nonconducting jointing materials that can realize sealing, and base 1 and pipe cap 2 all adopt circuit board raw material to make.As shown in Figure 2, pipe cap 2 is hollow enclosure, and box one side is provided with groove 14, and the groove limit of pipe cap 2 is connected with base 1 by sealing cap glue 3.Base 1 adopts the circuit boards of double-level-metal to be that raw material are made, and the dielectric material of its circuit boards can be arbitrary.Namely the upper surface of base 1 and lower surface are all covered with front ground metal layer 7 and back-side ground metal level 8, two ends are equipped with front lead-in wire 4 and back side lead-in wire 6, base 1 is also provided with some up and down in logical dish mesopore 5, dish mesopore 5 comprises metal connecting piece front ground metal layer 7 be connected with back-side ground metal level 8, dish mesopore 5 is circular port, metallization process is adopted to connect the circuit on circular port both sides, be added with filler 16 in dish mesopore 5, filler 16 can be any material being applicable to coil mesopore technique.The ground plane of semiconductor chip 9 is bonded in front ground metal layer 7 by conducting resinl 10, and the bonding pressure point of semiconductor chip 9 11 is gone between by bonding line 12 and front and 4 to be electrically connected; Semiconductor chip 9 upper surface is coated with protecting glue 13, and protecting glue 13 is do not react and the silicon rubber of good waterproof performance with chip.The non-recessed face of pipe cap 2 is coated with metal level 15.
Embodiment 2
As shown in Figure 3, a kind of capsulation body of semiconductor ship of high reliability and low cost, as different from Example 1, the quantity of the semiconductor chip 9 on base 1 is two, is electrically connected between semiconductor chip 9 by bonding line 12.
Claims (5)
1. the capsulation body of semiconductor ship of a high reliability and low cost, it is characterized in that comprising base (1), pipe cap (2) and sealing cap glue (3), described base (1) and pipe cap (2) all adopt circuit board raw material to make, described pipe cap (2) is hollow enclosure, box one side is provided with groove (14), and the groove limit of pipe cap (2) is connected with base (1) by sealing cap glue (3); The upper surface of described base (1) and lower surface are all covered with front ground metal layer (7) and back-side ground metal level (8), two ends are equipped with front lead-in wire (4) and back side lead-in wire (6), described base (1) is also provided with several up and down in logical dish mesopore (5), described dish mesopore (5) comprises metal connecting piece front ground metal layer (7) be connected with back-side ground metal level (8); Semiconductor chip (9) is bonded in front ground metal layer (7) by conducting resinl (10), the bonding pressure point (11) of semiconductor chip (9) by bonding line (12) and front go between (4) be electrically connected; Described semiconductor chip (9) upper surface is coated with protecting glue (13).
2. the capsulation body of semiconductor ship of a kind of high reliability and low cost according to claim 1, is characterized in that described dish mesopore (5) is circular port, adopts metallization process to connect the circuit on circular port both sides, is added with filler (16) in dish mesopore (5).
3. the capsulation body of semiconductor ship of a kind of high reliability and low cost according to claim 1, is characterized in that the non-recessed face of described pipe cap (2) is coated with metal level (15).
4. the capsulation body of semiconductor ship of a kind of high reliability and low cost according to claim 1 and 2, is characterized in that the quantity of described semiconductor chip (9) is at least two, by bonding line (12) electrical connection between described semiconductor chip (9).
5. the capsulation body of semiconductor ship of a kind of high reliability and low cost according to claim 1, is characterized in that described protecting glue (13) is not for react and the silicon rubber of good waterproof performance with chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510015604.8A CN104538371B (en) | 2015-01-13 | 2015-01-13 | A kind of capsulation body of semiconductor ship of high reliability and low cost |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510015604.8A CN104538371B (en) | 2015-01-13 | 2015-01-13 | A kind of capsulation body of semiconductor ship of high reliability and low cost |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104538371A true CN104538371A (en) | 2015-04-22 |
| CN104538371B CN104538371B (en) | 2018-01-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510015604.8A Active CN104538371B (en) | 2015-01-13 | 2015-01-13 | A kind of capsulation body of semiconductor ship of high reliability and low cost |
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115986433A (en) * | 2023-03-21 | 2023-04-18 | 成都雷电微力科技股份有限公司 | TR module architecture and process method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445831A (en) * | 2002-03-18 | 2003-10-01 | 美新半导体（无锡）有限公司 | Cavity type method for packaging micro-electronics circuit |
| CN101908493A (en) * | 2010-07-07 | 2010-12-08 | 天水天光半导体有限责任公司 | Process for producing hybrid integrated circuit |
| CN102194782A (en) * | 2010-03-08 | 2011-09-21 | 瑞萨电子株式会社 | Semiconductor package, substrate, electronic component, and method of mounting semiconductor package |
| CN202034361U (en) * | 2010-09-15 | 2011-11-09 | 晶诚（郑州）科技有限公司 | Semiconductor packaging structure |
| CN103681593A (en) * | 2013-12-02 | 2014-03-26 | 江苏省宜兴电子器件总厂 | Leadless ceramic chip carrier packaging structure and process for manufacturing same |
| CN103681619A (en) * | 2013-12-18 | 2014-03-26 | 中国电子科技集团公司第五十八研究所 | Silicon substrate air-impermeability sealing structure and manufacturing method thereof |
| CN104201113A (en) * | 2014-09-04 | 2014-12-10 | 中国电子科技集团公司第五十八研究所 | System-in-package type air-tightness sealing structure and manufacturing method thereof |
| CN204348705U (en) * | 2015-01-13 | 2015-05-20 | 河北博威集成电路有限公司 | A kind of capsulation body of semiconductor ship of high reliability and low cost |
-
2015
- 2015-01-13 CN CN201510015604.8A patent/CN104538371B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1445831A (en) * | 2002-03-18 | 2003-10-01 | 美新半导体（无锡）有限公司 | Cavity type method for packaging micro-electronics circuit |
| CN102194782A (en) * | 2010-03-08 | 2011-09-21 | 瑞萨电子株式会社 | Semiconductor package, substrate, electronic component, and method of mounting semiconductor package |
| CN101908493A (en) * | 2010-07-07 | 2010-12-08 | 天水天光半导体有限责任公司 | Process for producing hybrid integrated circuit |
| CN202034361U (en) * | 2010-09-15 | 2011-11-09 | 晶诚（郑州）科技有限公司 | Semiconductor packaging structure |
| CN103681593A (en) * | 2013-12-02 | 2014-03-26 | 江苏省宜兴电子器件总厂 | Leadless ceramic chip carrier packaging structure and process for manufacturing same |
| CN103681619A (en) * | 2013-12-18 | 2014-03-26 | 中国电子科技集团公司第五十八研究所 | Silicon substrate air-impermeability sealing structure and manufacturing method thereof |
| CN104201113A (en) * | 2014-09-04 | 2014-12-10 | 中国电子科技集团公司第五十八研究所 | System-in-package type air-tightness sealing structure and manufacturing method thereof |
| CN204348705U (en) * | 2015-01-13 | 2015-05-20 | 河北博威集成电路有限公司 | A kind of capsulation body of semiconductor ship of high reliability and low cost |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115986433A (en) * | 2023-03-21 | 2023-04-18 | 成都雷电微力科技股份有限公司 | TR module architecture and process method thereof |
| CN115986433B (en) * | 2023-03-21 | 2023-08-04 | 成都雷电微力科技股份有限公司 | TR module architecture and process method thereof |
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| Publication number | Publication date |
|---|---|
| CN104538371B (en) | 2018-01-09 |
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