CN104425368A - 通孔限定方案 - Google Patents
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims description 27
- 238000001039 wet etching Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 239000000463 material Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本发明涉及通孔限定方案。本发明的方法包括在第一介电层上方限定金属图案化层。第一介电层设置在蚀刻停止层上方,且蚀刻停止层设置在第二介电层上方。在金属图案化层和第一介电层上方生长间隔层。在第一介电层中形成具有金属宽度的金属沟槽。在第二介电层中形成具有通孔宽度的通路孔。
Description
技术领域
本发明总体涉及集成电路,更具体地,涉及通孔限定方案。
背景技术
在一些生产工艺中,通过两个分开的曝光工艺使用两个不同的掩模来限定金属线和通孔。期望更有效的且低成本的方法来限定金属层和通孔层。
发明内容
为解决上述问题,本发明提供了一种方法,包括:在第一介电层上方限定金属图案层,其中,第一介电层设置在蚀刻停止层上方,且蚀刻停止层设置在第二介电层上方;在金属图案层和第一介电层上方生长间隔层;在第一介电层中形成具有金属宽度的金属沟槽;以及在第二介电层中形成具有通孔宽度的通路孔。
该方法进一步包括:蚀刻间隔层以与通孔宽度相匹配。
其中,使用湿蚀刻工艺。
该方法进一步包括:蚀刻第一介电层以与通孔宽度相匹配。
该方法进一步包括:在蚀刻第一介电层之后,去除间隔层。
其中,使用湿蚀刻工艺以去除间隔层。
该方法进一步包括:去除金属图案层。
该方法进一步包括:将金属层填充到金属沟槽和通路孔中。
该方法进一步包括:实施抛光工艺以去除金属层的一部分。
其中,使用干蚀刻工艺以形成金属沟槽和通路孔。
其中,金属图案层包括光刻胶。
其中,间隔层包括SiN。
其中,通过原子层沉积(ALD)工艺生长间隔层。
此外,还提供了一种集成电路,包括:通孔,在通孔层中具有通孔宽度;以及金属线,位于金属层中,设置于通孔层上方,其中,金属线具有用于第一区域的第一宽度以及用于第二区域的第二宽度,第一区域不直接位于通孔上方,第二区域直接位于通孔上方,第二宽度大于第一宽度。
其中,第一宽度大于通孔宽度。
该集成电路进一步包括:位于通孔层和金属层之间的蚀刻停止层。
其中,第二宽度比第一宽度大10%至50%。
其中,在直接位于通孔上方的椭圆形或圆形中,金属线的第二宽度大于第一宽度。
此外,还提供了一种方法,包括:在第一介电层上方限定金属图案层,其中,第一介电层设置在蚀刻停止层上方,蚀刻停止层设置在第二介电层上方;在金属图案层和第一介电层上方生长间隔层;蚀刻间隔层以与预定的通孔宽度相匹配;蚀刻第一介电层以与通孔宽度相匹配;在蚀刻第一介电层之后,去除间隔层;在第一介电层中形成具有金属宽度的金属沟槽;在第二介电层中形成具有通孔宽度的通路孔;以及去除金属图案层。
该方法进一步包括:将金属填充到金属沟槽和通路孔中。
附图说明
现将结合附图所进行的以下描述作为参考,其中:
图1A至图7是根据一些实施例的示出了示例性通孔限定方案的中间制造步骤的集成电路结构的布局或者横截面的顶视图。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅示出了制造和使用的具体方式,而不用于限制本发明的范围。
另外,本发明可以在多个实施例中重复参考符号和/或字符。这种重复用于简化和清楚的目的,并且其本身不表示所述多个实施例和/或配置之间的关系。此外,在本发明中,一个部件形成在、连接至和/或偶接至另一个部件上可以包括两个部件直接接触的实施例,也可以包括额外的部件可以形成在两个部件之间使得两个部件不直接接触的实施例。此外,在本发明中可以使用诸如“下面的”、“上面的”、“水平的”、“垂直的”、“在….之上”、“在…上面”、“在…之下”、“在…下面”、“在…上方”、“在…下方”、“在…顶部”、“在…底部”等以及其衍生词(例如“水平地”、“向下地”、“向上地”等)这样的空间关系术语,以容易地描述如本发明中一个部件与另一个部件的关系。空间关系术语旨在包括包含部件的器件的不同方位。
图1A至图7是根据一些实施例的示出了示例性通孔限定方案的中间制造步骤的集成电路结构的布局或者横截面的顶视图。
图1是根据一些实施例的示例性通孔限定方案的布局的顶视图。在图1A中,在布局中示出了金属线200和介电层108。金属线200在下方不具有通孔的区域中的宽度为w1,在下方具有通孔的区域中的宽度为w2。在一些实施例中,w1介于40nm至50nm的范围内,w2介于60nm至70nm的范围内。在一些实施例中,w2比w1大10%至50%。在直接位于通孔上方的椭圆形或圆形中,金属线200的w2大于w1。
图1B是根据一些实施例的图1A中的示例性通孔限定方案的集成电路结构的截面图。图1B示出了沿图1A的布局中的切线A-A’的截面图,尽管,图1B处于使用金属图案化层110的金属图案化限定阶段,且还未形成图1A的布局中的金属线200。在图1B中,示出了衬底102、介电层104和108、蚀刻停止层(或者硬掩模)106和金属图案化层110。
衬底102包括硅、二氧化硅、氧化铝、蓝宝石、锗、砷化镓(GaAs)、硅和锗的合金、磷化铟(InP)、绝缘体上硅(SOI)或者任何其它合适的材料。衬底102可以进一步包括额外的部件或者层来形成不同的器件和功能化的部件。
在一些实施例中,介电层104和108包括SiO2或者厚度介于30nm至100nm的范围内的任何其它合适的材料,并且介电层104和108可以通过化学汽相沉积(CVD)分别形成在衬底102和蚀刻停止层106的上方。在一些实施例中,蚀刻停止层106(或者硬掩模)包括TiN、SiO、SiC、SiN、SiOC、SiON、SiCN、AlOXNY或者厚度介于2nm至10nm的范围内的任何其它合适的材料,并且蚀刻停止层106可以通过CVD或者物理汽相沉积(PVD)形成在介电层104的上方。
金属图案化层110包括光刻胶或者通过光刻胶限定的其它材料。通过单次光刻曝光限定(图案化)金属图案化层110。在一些实施例中,金属图案化层110的厚度介于70nm至100nm的范围内。位于切线A-A’之间的金属图案化层110具有与图1A中金属线200的宽度w2相同的间隔w2。在一些实施例中,w2介于60nm至70nm的范围内。
图2A是根据一些实施例的具有开口区域114(宽度为w3)的图1A中的布局的顶视图。图2B是根据一些实施例的在间隔层112生长之后的图1B中的集成电路结构的截面图。在一些实施例中,间隔层112包括SiN或者任何其它合适的材料,并且间隔层112的厚度介于20nm至30nm的范围内。例如,在一些实施例中,间隔层112包括与包含SiO2的介电层104和106具有不同蚀刻特性的SiN,因此可以进行选择性蚀刻。在一些实施例中,通过原子层沉积(ALD)生长间隔层112。
间隔层112的形状与金属图案化层110共形。间隔层112具有宽度w4和介于20nm至30nm的范围内的厚度t1。图7中区域113具有预先设计的金属槽121,但是在下方不具有通过间隔层112填充(或密封)的预先设计的通孔。另一方面,下方具有预先设计的通孔的另一区域具有形成在预先设计的通孔(形成在图7中的通路孔120中)顶部上的开口区域114,产生的金属图案化层110的间隔为w2。
图3A是根据一些实施例的具有开口区域116(宽度为w5)的图1A中的布局的顶视图。图3B是根据一些实施例的在蚀刻间隔层112以形成具有间隔w5的开口116之后的集成电路结构的截面图,其中,间隔w5与在图7中通路孔120中形成的通孔宽度相匹配。
在这个步骤中可以使用湿蚀刻工艺。例如,可以通过热H3PO4(温度介于80℃到200℃的范围内)蚀刻间隔层112以将其从预先设计的通孔区域顶部去除,并且延伸图2B中的顶部区域114来匹配预先设计的通孔宽度。在一些实施例中,宽度w5介于30nm至50nm的范围内。在一些其他实施例中,由于图2B中的开口区域114的宽度w3可以适合于预先设计的通孔的宽度,因此这个步骤是可选的。
图4A是根据一些实施例的具有开口区域118的图1A中布局的顶视图。图4B是根据一些实施例的在蚀刻介电层108以形成具有间隔w5的开口118之后的集成电路结构的截面图,其中间隔w5与图7中通路孔120中形成通孔宽度相匹配。在这个步骤中可以使用干蚀刻工艺。例如,C2F6或者CF4可以用来干蚀刻包括SiO2的介电层108,Cl2可以用来干蚀刻包括TiN的蚀刻停止层106(或者硬掩模)。
图5A是根据一些实施例的具有开口区域118的图1A中的布局的顶视图。图5B是根据一些实施例的在去除间隔层112之后的图4B中的集成电路结构的截面图。在这个步骤中可以使用湿蚀刻工艺。例如,可以通过温度介于80℃到200℃的范围内的热H3PO4去除间隔层112。
图6A是根据一些实施例的具有通路孔120的图1A中布局的顶视图。图6B是根据一些实施例的在蚀刻介电层104和108以形成金属沟槽122和通路孔120之后的图5B中的集成电路结构的截面图。在这个步骤中可以使用干蚀刻工艺。例如,C2F6或者CF4可以用来干蚀刻包括SiO2的介电层104和108。
图7是根据一些实施例的在去除金属图案化层110之后图6B中集成电路结构的截面图。例如,可以通过O2灰化工艺去除包括光刻胶的金属图案化层110。
然后,可以使用金属填充金属沟槽122和通路孔120以分别形成金属线和通孔。例如,可以使用电化学镀工艺沉积Cu。在一些实施例中,在填充金属沟槽122和通路孔120之前,通过PVD在金属沟槽122和通路孔120中形成厚度介于2nm至10nm的Cu晶种层。在一些实施例中,在填充金属沟槽122和通路孔120之后实施诸如化学机械抛光的抛光工艺以去除过量的材料(例如,填充在金属沟槽122上方的金属的顶部)。
通过使用上文描述的方法,可以根据金属沟槽的形状(例如,宽度)通过使用金属图案化层110限定通孔。与传统的双镶嵌工艺的两次曝光相比,这种方法通过金属图案化层110的单次光刻曝光以及使用间隔层112完成通孔的限定。因此,用于传统工艺的两个掩模图案可以减少为一个掩模,这减少了来自多次曝光的成本和形状(topography)影响。
根据一些实施例,一种方法包括在第一介电层上方限定金属图案化层。第一介电层设置在蚀刻停止层上方,且蚀刻停止层设置在第二介电层上方。在金属图案化层和第一介电层上方生长间隔层。在第一介电层中形成具有金属宽度的金属沟槽。在第二介电层中形成具有通孔宽度的通路孔。
根据一些实施例,一种集成电路包括在通孔层中具有通孔宽度的通孔。金属层中的金属线设置在通孔层上方。金属线具有用于第一区域的第一宽度以及用于第二区域的第二宽度,其中,第一区域不直接位于通孔上方,第二区域直接位于通孔上方。第二宽度大于第一宽度。
本领域技术人员应该理解本发明可具有许多实施例的变化。尽管已经详细地描述了实施例及其优势,但应该理解,可以在不背离所实施例的主旨和范围的情况下,做出各种改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、手段、方法和步骤的特定实施例。作为本领域普通技术人员应理解,根据本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、手段、方法或步骤本发明可以被使用。
上述方法实施例示出了示例性的步骤,但是没有必要按照所示顺序执行这些步骤。根据本发明的实施例的主旨和范围,可以适当地对这些步骤进行添加、替换、改变顺序和/或删除。结合了不同权利要求和/或不同实施例的实施例都处在本发明的范围内并且在阅读完本发明之后,其对本领域的技术人员是显而易见的。
Claims (10)
1.一种方法,包括:
在第一介电层上方限定金属图案层,其中,所述第一介电层设置在蚀刻停止层上方,且所述蚀刻停止层设置在第二介电层上方;
在所述金属图案层和所述第一介电层上方生长间隔层;
在所述第一介电层中形成具有金属宽度的金属沟槽;以及
在所述第二介电层中形成具有通孔宽度的通路孔。
2.根据权利要求1所述的方法,进一步包括:蚀刻所述间隔层以与所述通孔宽度相匹配。
3.根据权利要求2所述的方法,其中,使用湿蚀刻工艺。
4.根据权利要求1所述的方法,进一步包括:蚀刻所述第一介电层以与所述通孔宽度相匹配。
5.根据权利要求4所述的方法,进一步包括:在蚀刻所述第一介电层之后,去除所述间隔层。
6.根据权利要求5所述的方法,其中,使用湿蚀刻工艺以去除所述间隔层。
7.根据权利要求1所述的方法,进一步包括:去除所述金属图案层。
8.根据权利要求1所述的方法,进一步包括:将金属层填充到所述金属沟槽和所述通路孔中。
9.一种集成电路,包括:
通孔,在通孔层中具有通孔宽度;以及
金属线,位于金属层中,设置于所述通孔层上方,
其中,所述金属线具有用于第一区域的第一宽度以及用于第二区域的第二宽度,所述第一区域不直接位于所述通孔上方,所述第二区域直接位于所述通孔上方,所述第二宽度大于所述第一宽度。
10.一种方法,包括:
在第一介电层上方限定金属图案层,其中,所述第一介电层设置在蚀刻停止层上方,所述蚀刻停止层设置在第二介电层上方;
在所述金属图案层和所述第一介电层上方生长间隔层;
蚀刻所述间隔层以与预定的通孔宽度相匹配;
蚀刻所述第一介电层以与所述通孔宽度相匹配;
在蚀刻所述第一介电层之后,去除所述间隔层;
在所述第一介电层中形成具有金属宽度的金属沟槽;
在所述第二介电层中形成具有通孔宽度的通路孔;以及去除所述金属图案层。
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