CN104347517A - 半导体结构的形成方法 - Google Patents
半导体结构的形成方法 Download PDFInfo
- Publication number
- CN104347517A CN104347517A CN201310337245.9A CN201310337245A CN104347517A CN 104347517 A CN104347517 A CN 104347517A CN 201310337245 A CN201310337245 A CN 201310337245A CN 104347517 A CN104347517 A CN 104347517A
- Authority
- CN
- China
- Prior art keywords
- layer
- stop
- sacrifice layer
- formation method
- isolation structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000007667 floating Methods 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000003989 dielectric material Substances 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims description 98
- 239000000463 material Substances 0.000 claims description 62
- 230000015572 biosynthetic process Effects 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 239000011248 coating agent Substances 0.000 claims description 24
- 238000000576 coating method Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000151 deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000002459 sustained effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310337245.9A CN104347517B (zh) | 2013-08-05 | 2013-08-05 | 半导体结构的形成方法 |
US14/266,693 US9515078B2 (en) | 2013-08-05 | 2014-04-30 | Semiconductor structure and method for forming the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310337245.9A CN104347517B (zh) | 2013-08-05 | 2013-08-05 | 半导体结构的形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104347517A true CN104347517A (zh) | 2015-02-11 |
CN104347517B CN104347517B (zh) | 2018-10-16 |
Family
ID=52426880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310337245.9A Active CN104347517B (zh) | 2013-08-05 | 2013-08-05 | 半导体结构的形成方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9515078B2 (zh) |
CN (1) | CN104347517B (zh) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105990249A (zh) * | 2015-02-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN107863294A (zh) * | 2016-09-22 | 2018-03-30 | 英飞凌科技股份有限公司 | 半导体晶片和方法 |
CN109309094A (zh) * | 2018-10-31 | 2019-02-05 | 上海华力微电子有限公司 | 闪存的制造方法 |
CN109524405A (zh) * | 2017-09-20 | 2019-03-26 | 华邦电子股份有限公司 | 半导体元件的制造方法 |
CN109755246A (zh) * | 2017-11-03 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法 |
CN116281846A (zh) * | 2023-05-12 | 2023-06-23 | 润芯感知科技(南昌)有限公司 | 一种半导体器件及其制造方法 |
CN117476549A (zh) * | 2023-12-25 | 2024-01-30 | 合肥晶合集成电路股份有限公司 | 半导体叠层结构的制造方法及半导体结构 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115148676B (zh) * | 2021-03-31 | 2024-05-07 | 长鑫存储技术有限公司 | 半导体结构的制备方法及半导体结构 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060068547A1 (en) * | 2004-07-12 | 2006-03-30 | Sang-Hoon Lee | Methods of forming self-aligned floating gates using multi-etching |
WO2006118673A2 (en) * | 2005-04-29 | 2006-11-09 | Atmel Corporation | Method of forming shallow trench isolation structures in the logic and memory areas |
US20100200905A1 (en) * | 2009-02-09 | 2010-08-12 | Chun-Sung Huang | Nand memory cells and manufacturing method thereof |
CN101901785A (zh) * | 2009-05-26 | 2010-12-01 | 和舰科技(苏州)有限公司 | 一种改善栅氧化层tddb失效的方法 |
CN102005376A (zh) * | 2009-09-02 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | 构造浮栅的方法 |
CN102117761A (zh) * | 2010-01-05 | 2011-07-06 | 上海华虹Nec电子有限公司 | 改善浅沟槽隔离顶部倒角圆滑性的湿法工艺方法 |
-
2013
- 2013-08-05 CN CN201310337245.9A patent/CN104347517B/zh active Active
-
2014
- 2014-04-30 US US14/266,693 patent/US9515078B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060068547A1 (en) * | 2004-07-12 | 2006-03-30 | Sang-Hoon Lee | Methods of forming self-aligned floating gates using multi-etching |
WO2006118673A2 (en) * | 2005-04-29 | 2006-11-09 | Atmel Corporation | Method of forming shallow trench isolation structures in the logic and memory areas |
US20100200905A1 (en) * | 2009-02-09 | 2010-08-12 | Chun-Sung Huang | Nand memory cells and manufacturing method thereof |
CN101901785A (zh) * | 2009-05-26 | 2010-12-01 | 和舰科技(苏州)有限公司 | 一种改善栅氧化层tddb失效的方法 |
CN102005376A (zh) * | 2009-09-02 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | 构造浮栅的方法 |
CN102117761A (zh) * | 2010-01-05 | 2011-07-06 | 上海华虹Nec电子有限公司 | 改善浅沟槽隔离顶部倒角圆滑性的湿法工艺方法 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105990249A (zh) * | 2015-02-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN107863294A (zh) * | 2016-09-22 | 2018-03-30 | 英飞凌科技股份有限公司 | 半导体晶片和方法 |
CN107863294B (zh) * | 2016-09-22 | 2021-09-03 | 英飞凌科技股份有限公司 | 半导体晶片和方法 |
CN109524405A (zh) * | 2017-09-20 | 2019-03-26 | 华邦电子股份有限公司 | 半导体元件的制造方法 |
CN109524405B (zh) * | 2017-09-20 | 2020-10-09 | 华邦电子股份有限公司 | 半导体元件的制造方法 |
CN109755246A (zh) * | 2017-11-03 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法 |
CN109309094A (zh) * | 2018-10-31 | 2019-02-05 | 上海华力微电子有限公司 | 闪存的制造方法 |
CN116281846A (zh) * | 2023-05-12 | 2023-06-23 | 润芯感知科技(南昌)有限公司 | 一种半导体器件及其制造方法 |
CN116281846B (zh) * | 2023-05-12 | 2023-08-01 | 润芯感知科技(南昌)有限公司 | 一种半导体器件及其制造方法 |
CN117476549A (zh) * | 2023-12-25 | 2024-01-30 | 合肥晶合集成电路股份有限公司 | 半导体叠层结构的制造方法及半导体结构 |
CN117476549B (zh) * | 2023-12-25 | 2024-04-09 | 合肥晶合集成电路股份有限公司 | 半导体叠层结构的制造方法及半导体结构 |
Also Published As
Publication number | Publication date |
---|---|
CN104347517B (zh) | 2018-10-16 |
US20150035038A1 (en) | 2015-02-05 |
US9515078B2 (en) | 2016-12-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104347517A (zh) | 半导体结构的形成方法 | |
EP3196937A2 (en) | A nand flash memory and fabrication method thereof | |
CN104752363A (zh) | 快闪存储器的形成方法 | |
KR102302231B1 (ko) | 비휘발성 메모리 소자 및 그 제조 방법 | |
CN105448717A (zh) | 鳍式场效应管的形成方法 | |
US7888208B2 (en) | Method of fabricating non-volatile memory device | |
CN105336695A (zh) | 半导体器件的形成方法 | |
CN103794476A (zh) | 自对准三重图形的形成方法 | |
CN104347371A (zh) | 半导体结构的形成方法 | |
CN103794490A (zh) | 自对准双图形的形成方法 | |
CN104752361A (zh) | 半导体结构的形成方法 | |
CN102347227A (zh) | 一种金属栅极的形成方法 | |
CN106206598A (zh) | 分栅式闪存器件制造方法 | |
CN102005375B (zh) | 构造浮栅的方法 | |
CN103177948B (zh) | 鳍式场效应管的鳍部以及鳍式场效应管的形成方法 | |
CN101599419A (zh) | 沟槽的形成方法 | |
CN108615733A (zh) | 半导体结构及其形成方法 | |
CN103035575B (zh) | 闪存的存储单元的形成方法 | |
CN102479691A (zh) | 金属栅极及mos晶体管的形成方法 | |
CN101847655B (zh) | 一种可提高沟槽栅mos器件性能的沟槽栅及其制造方法 | |
CN104091786A (zh) | 闪存存储器的形成方法 | |
CN105655341B (zh) | 半导体器件的形成方法 | |
CN104217986A (zh) | 浅沟槽隔离结构的制作方法和nand闪存的制作方法 | |
CN101097894A (zh) | 与非闪存装置的制造方法 | |
CN105513954A (zh) | 半导体器件的形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20190807 Address after: No. 18 Wenchang Avenue, Beijing Economic and Technological Development Zone, Daxing District, Beijing Co-patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Zhongxin North Integrated Circuit Manufacturing (Beijing) Co., Ltd. Address before: 100176 Daxing District economic and Technological Development Zone, Wenchang Road, No. 18, No. Co-patentee before: Semiconductor Manufacturing International (Shanghai) Corporation Patentee before: Semiconductor Manufacturing International (Beijing) Corporation |