CN104321655B - 能够生成用于扫描测试的测试模式控制信号的集成电路 - Google Patents

能够生成用于扫描测试的测试模式控制信号的集成电路 Download PDF

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Publication number
CN104321655B
CN104321655B CN201380022743.2A CN201380022743A CN104321655B CN 104321655 B CN104321655 B CN 104321655B CN 201380022743 A CN201380022743 A CN 201380022743A CN 104321655 B CN104321655 B CN 104321655B
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shift
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capture
counter
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CN201380022743.2A
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Chinese (zh)
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CN104321655A (zh
Inventor
R·米塔尔
P·萨巴瑞瓦
P·纳拉亚南
R·A·帕瑞克基
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Texas Instruments Inc
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Texas Instruments Japan Ltd
Texas Instruments Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318569—Error indication, logging circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201380022743.2A 2012-05-14 2013-05-10 能够生成用于扫描测试的测试模式控制信号的集成电路 Active CN104321655B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/470,863 2012-05-14
US13/470,863 US8972807B2 (en) 2012-05-14 2012-05-14 Integrated circuits capable of generating test mode control signals for scan tests
PCT/US2013/040609 WO2013173192A1 (en) 2012-05-14 2013-05-10 Integrated circuits capable of generating test mode control signals for scan tests

Publications (2)

Publication Number Publication Date
CN104321655A CN104321655A (zh) 2015-01-28
CN104321655B true CN104321655B (zh) 2017-04-05

Family

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CN201380022743.2A Active CN104321655B (zh) 2012-05-14 2013-05-10 能够生成用于扫描测试的测试模式控制信号的集成电路

Country Status (4)

Country Link
US (1) US8972807B2 (enExample)
JP (1) JP6544772B2 (enExample)
CN (1) CN104321655B (enExample)
WO (1) WO2013173192A1 (enExample)

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US9310436B2 (en) * 2014-01-28 2016-04-12 Omnivision Technologies, Inc. System and method for scan-testing of idle functional units in operating systems
JP6211971B2 (ja) * 2014-03-26 2017-10-11 旭化成エレクトロニクス株式会社 半導体テスト回路及びｉｃチップ
US9380297B1 (en) * 2014-12-04 2016-06-28 Spirent Communications, Inc. Video streaming and video telephony uplink performance analysis system
US10606723B2 (en) 2015-12-18 2020-03-31 Texas Instruments Incorporated Systems and methods for optimal trim calibrations in integrated circuits
US10060979B2 (en) 2016-08-02 2018-08-28 Texas Instruments Incorporated Generating multiple pseudo static control signals using on-chip JTAG state machine
CN106541702B (zh) * 2016-10-27 2018-11-23 杭州电子科技大学 一种印刷质量校正系统及其方法
US11405695B2 (en) 2019-04-08 2022-08-02 Spirent Communications, Inc. Training an encrypted video stream network scoring system with non-reference video scores
US12335579B2 (en) 2019-04-08 2025-06-17 Spirent Communications, Inc. Cloud gaming benchmark testing
US11221864B1 (en) * 2019-06-03 2022-01-11 Synopsys, Inc. Combinatorial and sequential logic compaction in electronic circuit design emulation
US10852353B1 (en) * 2019-07-02 2020-12-01 Texas Instruments Incorporated Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface
KR102278648B1 (ko) * 2020-02-13 2021-07-16 포스필 주식회사 피시험 디바이스를 테스트하기 위한 방법 및 장치
US11309047B2 (en) * 2020-09-14 2022-04-19 Micron Technology, Inc. Test circuit using clock signals having mutually different frequency
CN112462244B (zh) * 2020-10-28 2022-07-01 苏州浪潮智能科技有限公司 一种扫描链测试的时钟控制装置
US11726140B2 (en) * 2021-02-01 2023-08-15 Stmicroelectronics International N.V. Scan circuit and method
CN114089157B (zh) * 2021-11-02 2024-04-12 广州昂宝电子有限公司 芯片测试方法及系统
US11782092B1 (en) 2022-05-18 2023-10-10 Stmicroelectronics International N.V. Scan compression through pin data encoding
US20240426908A1 (en) * 2023-06-21 2024-12-26 Stmicroelectronics International N.V. Scan-testable electronic circuit and corresponding method of testing an electronic circuit
US12480993B2 (en) 2024-03-18 2025-11-25 Stmicroelectronics International N.V. Low pin count scan with no dedicated scan enable pin

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US7444567B2 (en) * 2002-04-09 2008-10-28 Syntest Technologies, Inc. Method and apparatus for unifying self-test with scan-test during prototype debug and production test
US6671839B1 (en) 2002-06-27 2003-12-30 Logicvision, Inc. Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith
JP2004325124A (ja) 2003-04-22 2004-11-18 Matsushita Electric Ind Co Ltd 半導体装置
JP2005037995A (ja) * 2003-07-15 2005-02-10 Toshiba Corp 半導体集積回路の検証システム
JP2005147772A (ja) 2003-11-13 2005-06-09 Matsushita Electric Ind Co Ltd 半導体検査装置
US7380189B2 (en) * 2004-06-15 2008-05-27 Broadcom Corporation Circuit for PLL-based at-speed scan testing
US7334172B2 (en) * 2004-10-20 2008-02-19 Lsi Logic Corporation Transition fault detection register with extended shift mode
JP4922055B2 (ja) 2007-04-27 2012-04-25 ルネサスエレクトロニクス株式会社 スキャンテスト回路、及びスキャンテスト制御方法
JP5167904B2 (ja) * 2008-03-28 2013-03-21 富士通株式会社 スキャン制御方法、スキャン制御回路及び装置
JP2011058847A (ja) * 2009-09-07 2011-03-24 Renesas Electronics Corp 半導体集積回路装置
US8205125B2 (en) * 2009-10-23 2012-06-19 Texas Instruments Incorporated Enhanced control in scan tests of integrated circuits with partitioned scan chains
US8332698B2 (en) * 2010-05-21 2012-12-11 Apple Inc. Scan latch with phase-free scan enable
CN101975922A (zh) * 2010-10-11 2011-02-16 上海电力学院 低功耗扫描测试电路及运行方法
US8799713B2 (en) * 2011-03-01 2014-08-05 Texas Instruments Incorporated Interruptible non-destructive run-time built-in self-test for field testing
US8412991B2 (en) * 2011-09-02 2013-04-02 Teseda Corporation Scan chain fault diagnosis

Also Published As

Publication number Publication date
US20130305106A1 (en) 2013-11-14
US8972807B2 (en) 2015-03-03
JP2015522800A (ja) 2015-08-06
WO2013173192A1 (en) 2013-11-21
CN104321655A (zh) 2015-01-28
JP6544772B2 (ja) 2019-07-17

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