CN104253095A - 具有减小耦合的引线接合壁的半导体封装 - Google Patents
具有减小耦合的引线接合壁的半导体封装 Download PDFInfo
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Abstract
本发明涉及具有减小耦合的引线接合壁的半导体封装。呈现了包括了引线接合壁(50)以减小耦合的封装(20)的系统及方法。所述封装包括衬底(74)、在所述衬底上的第一电路(22)。所述第一电路包括第一电气器件(100,102,104)、第二电气器件(100,102,104)以及互连了所述第一电气器件和所述第二电气器件的第一引线接合阵列(112)。所述封装包括在所述衬底上与所述第一电路相邻的第二电路(24),所述第二电路包括互联了所述第三电气器件(106,108,110)和所述第四电气器件(106,108,110)的第二引线接合阵列(114)。所述封装包括包括了在所述第一电路和所述第二电路之间的所述衬底上的多个引线接合(122)的引线接合壁。所述引线接合壁被配置成在所述第一电路和第二电路中的至少一个的操作期间减小所述第一电路和所述第二电路之间的电磁耦合。
Description
技术领域
本公开通常涉及器件封装,更具体地说,涉及包含了减小相邻器件之间的耦合的引线接合壁的器件封装。
背景技术
无线通信系统通常采用功率放大器以用于增大信号的功率。在无线通信系统中,功率放大器通常是传输链(输出级)中的最后放大器。高增益、高线性、稳定性和高水平功率附加效率(即,在输出功率和输入功率至DC电源之间的差的比)是理想放大器的特性。
通常,当功率放大器传输峰值输出功率的时候,功率放大器以最大功率效率操作。然而,由于输出功率减小,功率效率趋于恶化。近日,由于架构的高功率附加效率,Doherty功率放大器架构已经不仅是基站而且是移动端子的关注焦点。
Doherty功率放大器通常包括两个或多个放大器,诸如载波放大器和峰值放大器。这些放大器与通过偏移传输线连接的它们的输出并联连接,其中该偏移传输线执行了阻抗转换。由于载波放大器饱和,峰值放大器传送电流,从而减小了在载波放大器的输出处可见的阻抗。因此,由于“负载牵引”的效果,当载波放大器饱和的时候,载波放大器给负载传送更多的电流。由于载波放大器保持接近饱和,所以Doherty功率放大器能够传输峰值输出功率,使得系统的总效率仍然保持相对高。
Doherty架构的高效率使得该架构可期望用于当前和下一代无线系统。然而,架构在半导体封装设计方面呈现出挑战。当前的Doherty功率放大器半导体封装设计要求使用离散器件和集成电路,其可能涉及包括了载波放大器的一个器件和包括了峰值放大器的独立器件。这些离散器件与封装保持距离以便限制在载波和峰值放大器之间发生的串扰问题。
半导体封装架构中串扰的一个来源是在信号线的阵列之间,被称为引线接合阵列,其可被连接在构成载波和峰值放大器中的每个的各种电气器件之间。即,Doherty功率放大器的性能可以受到Doherty功率放大器的相应的组件的相邻引线接合阵列之间的耦合(即,能量通过共享的磁场或电场从一个电路组件转移到另一个)的不利影响。耦合可以是两种类型,电气(通常被称为电容性耦合)和磁性(与电感性耦合同义地使用)。当变化的磁场存在于彼此靠近的载流平行导体之间的时候,电感耦合或磁耦合出现,从而引发穿过接收导体的电压。
遗憾的是,在封装中维持放大器之间的空间距离限制了半导体封装的小型化的可能性。限制小型化是不理想的,其中低成本、低重量以及小体积是各种应用的重要封装属性。
附图说明
本公开通过举例的方式说明,实施例等等并没有被附图所限制,在附图中相同的参考符号表示相同的元素。附图中的元素说明是为了简便以及清晰,并且不一定按比例绘制。附图连同详细说明书被并入并构成说明书的一部分,并且用于进一步说明例子、实施例等等,并根据本公开解释各种原理和优点,其中:
图1是Doherty功率放大器半导体封装的框图。
图2A是Doherty功率放大器半导体封装的载波和峰值放大器电路的俯视示意图。
图2B是图2A的Doherty功率放大器半导体封装的立体图。
图3A和3B是描绘了替代引线接合壁配置的封装的截面图。
图4A和4B示出了图2A的封装,其中引线接合壁被连接到多个附加器件。
图5A和5B是示出示例器件的测试结果的曲线图,其中该示例器件包括分离了载波放大器和峰值放大器的引线接合壁。
具体实施方式
以下详细描述在本质上是示例性的,并不旨在限制本发明或本申请以及其使用。此外,不旨在被先前技术领域、背景、或以下详细描述中的任何明示或暗示的理论所限制。
为了简便和清楚地说明,附图说明了构造的一般方式,并且可省略众所周知的特征和技术的描述和细节以避免不必要地模糊本发明。此外,附图中的元件不一定按比例绘制。例如,附图中的一些元件或区域的尺寸相对于其它元件或区域可被夸大以帮助提高对本发明实施例的理解。
说明书和权利要求中的术语“第一”、“第二”、“第三”、“第四”等等,如果有的话,是用于区分类似元件,而不一定用于描述特定顺序或时间顺序。应了解术语的这种用法在适当的情况下是可以互换的,以便在此描述的实施例例如能够在除了本发明中所描述的那些说明的顺序进行操作。此外,术语“包括”、“包含”、“具有”及其任何变体都旨在涵盖非排他性,以便包括一列元件的过程、方法、制品、或装置不一定限定于那些元件,而可能包括其它没有明确列出的或是这个过程、方法、制品、或装置固有的元件。如在此使用的,术语“耦合”被定义为直接或间接连接的电气或非电气方式。如在此使用的,术语“实质的”和“实质地”意味着足以以一种实用的方式完成所陈述的目的,并且小缺陷,如果有的话,对所陈述的目的不是非常重要。
本公开通常涉及器件封装,更具体地说,涉及合并了减小在封装中形成的相邻器件之间的耦合的引线接合壁的器件封装。
在一个实现中,封装包括Doherty放大器阵容。在本设计中,在Doherty放大器的两个放大器(即,载波放大器和峰值放大器)之间的干扰和/或串扰被减小,使得Doherty功率放大器的载波和峰值放大器可在单个封装,在此被称为双路径半导体封装中用更高的效率被实施。在各个其它实现中,将了解,本系统可在各个封装中被使用,其中该封装包括彼此隔离的多个组件或电路。
本方法可被用于改进在基站功率放大器、蜂窝电话、蓝牙器件以及依赖于半导体封装的其它器件中的Doherty功率放大器半导体封装的可用性,其中低成本、低重量和小容量是理想的。在此描述的实施例减小了在Doherty功率放大器中的引线接合阵列之间的电感耦合。然而,将变得明显的是,下面描述的用于减小电感耦合的技术可在各种半导体器件设计中被实现。
图1示出了Doherty功率放大器半导体封装20的框图。Doherty功率放大器半导体封装20包括并联连接的载波放大器电路22和峰值放大器电路24。输入信号26被输入分离器28分成两个信号。所得到的输入信号中的一个被传递给载波放大器电路22的输入32,另一个输入信号被传递给峰值放大器电路24的输入36。输出信号从载波放大器电路22的输出40被传递。同样,输出信号从峰值放大器电路24的输出44被传递。这两个输出信号通过功率组合器(PWR CMB)46被组合以产生组合的输出信号48。本领域所属技术人员将认识到Doherty功率放大器半导体封装通常包括为了说明的简单起见未在此示出的附加电气器件和电路。
在一个实施例中,载波放大器电路22被配置成对于Doherty功率放大器半导体封装20的整个输出功率范围为接通。峰值放大器电路24被配置成仅当载波放大器电路22饱和的时候为开启。进行操作以将来自载波放大器电路22的输出信号与来自峰值放大器电路24的输出信号进行组合的功率合成器46可以是四分之一波长的阻抗转换器。四分之一波长的阻抗转换器可以将90度的滞后添加到来自载波放大器电路22的输出信号。峰值放大器电路24的相位通常被设计成90度滞后载波放大器电路22,使得当输出信号在功率合成器46的输出处被组合以形成组合的输出信号48的时候,两个输出信号同相相加。
在图1所示的例子中,载波放大器电路22和峰值放大器电路24中的每个可以包括多个有源和无源电气元件。例如,载波放大器电路22可以包括耦合于输入32的电容器。电容器可以耦合于晶体管,该晶体管将适当的放大应用于在输入32接收到的输入信号。该晶体管的输出可以被连接到第二电容器。电容器可以操作以调节在输入32接收到的输入信号并被晶体管放大。类似地,峰值放大器24可以包括耦合于输入36的电容器。电容器可以耦合于晶体管,该晶体管将适当的放大应用于在输入36接收到的输入信号。该晶体管的输出可以被连接到第二电容器。电容器可以操作以调节在输入36接收到的输入信号并被晶体管放大。本领域所属技术人员将认识到载波放大器电路22和峰值放大器电路24可以包括为了说明的简单起见未在此示出的其它电气器件。
在Doherty放大器封装20中,构成了载波放大器22和峰值放大器24中的每个的单独的电气器件可使用多个平行导线,被称为引线接合,互相连接。在实际应用中,载波放大器电路22的一个或多个信号路径(例如,在输入、输出、电容器和晶体管之间)可使用引线接合被建立。同样,峰值放大器电路24的一个或多个信号路径(例如,在输入、输出、电容器和晶体管之间)可以使用引线接合被建立。
在Doherty功率放大器封装中,因为它们被封装到单一外壳中,这些各种引线接合阵列可被放置的彼此非常靠近。互连了每个放大器的组件的各种的引线接合的信号路径之间的小距离可以导致相邻引线接合阵列之间的相对较高水平的电感耦合。这种电感耦合可以限制封装中Doherty放大器的功率能力。
因此,在本Doherty放大器封装中,引线接合壁50形成于两个放大器22和24之间以提供每个放大器(例如,载波放大器22和峰值放大器24)的引线接合阵列之间的电隔离。引线接合壁50,如下面进一步描述的,根据形成于构成了载波和峰值放大器的电路之间的封装中的多个引线接合连接被构造。根据封装20的实现,引线接合壁50可在各种衬底上建立或直接在封装20的引线框上建立。连同封装20的其它组件,引线接合壁50可以用密封剂超模压或者可以是气腔封装的一部分。在各个实现中,引线接合壁50可以被直接连接到接地或接地端子,其进而可以被连接到接地电压,或者被连接到各种集成无源器件(IPD)或其它有源器件和电路。通常,引线接合壁50作为屏蔽或围栏进行操作以中断和防止Doherty放大器的载波放大器电路和峰值放大器电路之间的电感耦合。
图2A是Doherty功率放大器的半导体封装20的载波放大器电路22和峰值放大器电路24的俯视示意图。图2B是2A的Doherty功率放大器半导体封装20的立体图。虽然根据Doherty放大器的组件来解释本例子,但是应了解,本系统和方法可以被用于给在衬底上形成的任何电路提供电隔离,其中Doherty放大器的组件仅仅是一个例子。根据本公开,引线接合壁可被用于提供在特定封装中适当配置的任何组件之间的电隔离。例如,参照图2A和图2B,载波放大器22可以被包括了多个互连的电气器件的任何电路所替换,并且峰值放大器24可以类似地被替换。
在封装20中,载波放大器22包括输入端子32和输出端子40,它们在Doherty配置中可以分别构成了载波放大器22的栅极端子和漏极端子。类似地,峰值放大器24包括输入端子36和输出端子44,它们在Doherty配置中可以分别构成了峰值放大器24的栅极端子和漏极端子。
载波放大器22包括多个电气器件,诸如被制作和/或随后被安装到共同(即,单一)载波的表面,诸如封装接地平面74的电容器100和104以及晶体管102(具有栅极盘103和漏极盘105)。电容器100和104可以例如是被安装在接地平面74上的金属-氧化物-半导体(MOS)电容器。类似地,峰值放大器24包括多个电气装置,诸如被制作和/或随后被安装到共同(即,单一)载波的表面,诸如封装接地平面74的电容器106和110以及晶体管108(具有栅极盘109和漏极盘111)。电容器106和111可以例如是被安装在接地平面74上的金属-氧化物-半导体(MOS)电容器。
如图2A和图2B所示,载波放大器22的组件(包括电容器100和104、晶体管102以及端子32和40)通过形成了引线接合阵列的多个引线接合112被连接。峰值放大器24的组件(包括电容器106和110、晶体管108、端子36和44)类似地通过自身形成了引线接合阵列的多个引线接合114被连接。在各个实现中,任何数目的引线接合可以被用于互连载波放大器22和峰值放大器24的各个组件,或者互连可以在接地平面74的表面上形成的任何其它组件。
在所描绘的封装20中,载波和峰值放大器电路22和24的对称布局可以导致载波放大器电路22的对应组件与峰值放大器电路24的对应组件相邻。因此,每个放大器的各个组件的布置(包括,特别是,携带高频信号的每个放大器的引线接合112和114)彼此相邻并且在几何上彼此平行。载波放大器22和峰值放大器24的引线接合阵列的这些特性可以导致器件之间的耦合,这可以降低整个器件的性能。
为了最小化载波放大器22和峰值放大器24之间的耦合,封装20包括分离了载波放大器22和峰值放大器24的引线接合壁50。引线接合壁包括端子116和118,在一个实现中,它们分别被连接到接地。多个连接盘120在接地平面74的表面上形成。在一个实现中,每个连接盘120被连接到接地电压,例如,通过将连接盘120连接到封装20的接地平面(例如,接地平面74),或者连接到然后可以被连接到接地电压的多个接地端子。然后,多个引线接合122在连接盘120和端子116和118之间形成。连接盘120的位置和几何结构使得构成了引线接合壁50的各个引线接合122能够通过适当的间距距离隔开,这取决于封装20的实现。在一个实现中,间距距离在5和6毫米(mm)之间。
总的来说,引线接合122形式了接地引线接合的壁或丝网,接地引线接合进行操作以将载波放大器22与峰值放大器24电隔离。引线接合122可由一种适当的导线金属形成,其中该金属与引线接合112和/或114的金属相同或不同。示例材料包括金、铜、铝或银。在一个实现中,引线接合壁50及其引线接合122作为无源器件进行操作,其中该无源器件被配置成吸收,并由此阻止或抑制由载波放大器22和峰值放大器24生成的电场互相影响。根据实现,引线接合122的配置可以被调整或调谐以服务特定需求,诸如,以阻止特定频率范围或特定带宽。这些调整可能涉及改变构成了引线接合壁50的单个引线接合122的长度和各个引线接合互相重叠的程度。一旦形成,则一种密封剂(未示出)可在封装20上沉积以给引线接合以及封装20的其它组件提供物理保护。
在各个实现中,引线接合壁50包括沿着彼此隔离的两个电路或组件之间的路线形成的多个引线接合。当引线接合壁50沿着一条直线行进的时候,构成了引线接合壁50的引线接合122分别大致彼此平行而形成。如图2B所示,引线接合壁50可以沿着垂直于在载波放大器22和峰值放大器24之间绘制的一条线的路线或路径行进。通常,引线接合壁50沿着接地平面74的位于载波放大器22和峰值放大器24之间的区域行进。在引线接合壁50内,个别引线接合122可以在单行中形成,或者如在图2A中描绘的多行中形成。图2A示出了包括三行引线接合122的引线接合壁50。此外,如图2B所示,构成了引线接合壁50的引线接合122可以被连接到引线接合壁50的每个连接盘120,或者在一些情况下,可以跳过连接盘120。
当引线接合壁由多行引线接合组成的时候,一种用于构造引线接合壁的方法是对于每个连接盘,假定来自一行引线接合壁的至少一个引线接合被连接到连接盘,以及来自另一行的至少一个引线接合未被连接到连接盘。当从侧面看的时候,这种方法可以假定构成了引线接合壁的引线接合形成了丝网,它的开口比如果每行引线接合被相同地连接的开口小。
除了沿着一条直线行进,引线接合壁可以沿着非直线路径形成。在一些情况下,被隔离的电路的布局和/或几何形状可要求非直线路线。在其它实现中,引线接合壁可基本上围绕特定电路形成。这可以使封装中的电路不仅与封装中的其它电路隔离,而且与封装外部的辐射源隔离。
为了说明引线接合壁50的一些不同配置,图3A和3B是描绘了替代引线接合壁配置的封装的截面图。截面图可能,例如,沿着图2A中所示的线3-3取得,但图示了不同于图2A中所示的引线接合壁配置。在图3A中,引线接合壁300是由互连了连接盘304和端子116以及118的多个引线接合302形成的。一种保护性密封剂306在引线接合302上形成。在图3B中,引线接合壁310是由在接地平面或连接盘结构上并且互连了端子116和118的多个引线接合312形成的。一种保护性密封剂316在引线接合312上形成。与图3A的相比,图3B中所示的配置包括更大数目的引线接合,因此,当从侧面看的时候,图3B的引线接合壁具有更大的密度,从而降低了引线接合壁50中的开口的平均尺寸。
通常,引线接合壁50的配置被选择以吸收,并从而阻止电磁在特定频率范围内的传输。在很多情况下,被阻止的频率是在封装中形成的器件的操作频率。对于给定实现,多个候选引线接合壁配置可以被模拟,其中各个候选包括变化数目的引线接合、变化长度的引线接合、变化数目的引线接合行以及不同数量的重叠引线接合以确定它们对特定输入信号的响应。用于执行这种模拟的一个例子工具包括HFSS,它是一种对天线设计有用的工具。然后,按照所需的电路性能,可以选择特定引线接合壁设计。
在图2A和图2B中,引线接合壁50可以被接地或浮动和通常作为封装20的无源组件进行操作。在本质上,当被接地的时候,引线接合壁50作为被配置成吸收载波放大器22或峰值放大器24的电磁辐射的调谐天线进行操作以防止那些辐射影响到其它电路。
在一些实现中,引线接合壁50可以被连接到一个或多个无源或有源器件以进一步控制和/或优化引线接合壁50的响应。附加器件可以在封装20中形成,或者也可以在封装20外部形成。为了说明,图4A和4B示出了封装20,其中引线接合壁50被连接到多个附加器件。如图4A所示,引线接合壁50被连接到IPD400。IPD400可以包括在封装20中形成的电阻器、电容器和电感器的组合。通常,IPD400的电容和/或电感将被选择,使得当被连接到引线接合壁50的时候,引线接合壁50结合IPD400的阻抗被调谐以阻止信号频率的所需范围。该阻抗匹配起到最小化载波放大器22和峰值放大器24之间的耦合的作用,从而改进了封装20的效率。通过合并IPD400调谐引线接合壁50的性能,可以在特定频率范围上实现耦合的减小。图4B图示了包括2个IPD402和404的替代实施例,其中IPD402和404彼此平行行进。IPD402和404耦合于引线接合壁50。在各个实现中,任何数目的IPD可以结合引线接合壁50被提供以提供封装20的组件的电隔离。
在其它实现中,引线接合壁50也可以被连接到一个或多个有源器件,其中这些有源器件可以被配置成根据载波放大器22和峰值放大器24(或封装20的其它电路)或其它系统组件的操作属性来修改引线接合壁50的阻抗。在这种情况下,根据封装20的电路的特定操作频率,有源器件可以是可调谐的例如以满足特定频率和/或带宽要求。
除了提供上述的电隔离的好处,本引线接合壁实现也是另有好处的,因为它可以使用用于制作封装20的剩余部分的类似制作技术被构造。例如,在一些实现中,引线接合壁的引线接合可以使用用于互连载波放大器22和峰值放大器24的组件的相同导线接合技术被制作。这与可能要求封装20的结构的彻底的重新设计的一些其它隔离技术形成对比。例如,如果固体金属壁被部署在载波放大器22和峰值放大器24之间以试图提供电隔离,则全新的制作技术(以及潜在的机械)将被开发并用于在现有封装设计中安装这样的结构。事实上,在很多情况下,封装将必须完全被重新设计以合并这样的组件。
在模拟中,本引线接合壁结构的实施例已证明了对于传统封装的性能的改进。在包括了根据图3B中描述的被配置并以大约2GHz进行操作的引线接合壁的Doherty结构的一个模拟中,接地的引线接合壁减小了大约3dB的检测耦合,并且带有集成IPD的引线接合壁减小了大约17dB的检测耦合。为了进行比较,当固体金属壁被放置在Doherty放大器的组件之间的时候,在模拟中仅观察到5dB的减小。
图5A和5B是示出示例器件的模拟结果的曲线图,其中该示例器件包括根据图3B中描绘的并在单一封装中分离了载波放大器和峰值放大器的引线接合壁,其中引线接合壁被连接到适当配置的IPD。曲线图描绘了在封装中的节点(纵轴,dB)对频率(横轴,GHz)之间的耦合量。图5A描绘了在图2A的元件105和44之间测量的测试结果。图5B描绘了在图2A的元件40和44之间测量的测试结果。
在图5A中,线502示出了传统器件(包括无引线接合壁)的结果以及线504示出了图2B的器件(包括引线接合壁50)的结果。如图5A所示,在Doherty放大器的操作频率(大约2GHz)周围有急剧减小的耦合。在图5B中,线506示出了传统器件(包括无引线接合壁)的结果以及线508示出了图2B的器件(包括引线接合壁50)的结果。如图5A所示,在Doherty放大器的操作频率(大约2GHz)周围有急剧减小的耦合。由引线接合壁提供的耦合的这个减小使放大器更高效地进行操作。
在一个实现中,本公开提供了封装,所述封装包括衬底、和在所述衬底上的第一电路。所述第一电路包括第一电气器件、第二电气器件以及互连了所述第一电气器件和所述第二电气器件的第一引线接合阵列。所述封装包括在所述衬底上与所述第一电路相邻的第二电路。所述第二电路包括第三电气器件、第四电气器件以及互连了所述第三电气器件和所述第四电气器件的第二引线接合阵列。所述封装包括引线接合壁,所述引线接合壁包括在所述第一电路和所述第二电路之间的所述衬底上的多个引线接合。所述引线接合壁被配置成在所述第一电路和第二电路中的至少一个的操作期间减小所述第一电路和所述第二电路之间的电磁耦合。
在另一个实现中,本公开提供了Doherty放大器封装。所述Doherty放大器封装包括衬底、在所述衬底上的载波放大器、在所述衬底上与所述载波放大器相邻的峰值放大器以及在所述衬底上的多个引线接合。所述多个引线接合互连并沿着所述衬底的位于所述峰值放大器和所述载波放大器的至少一部分之间的区域行进。所述多个引线接合形成了引线接合壁,所述引线接合壁被配置成在所述载波放大器和所述峰值放大器中的至少一个的操作期间减小所述载波放大器和所述峰值放大器之间的电磁耦合。
在另一个实现中,本公开提供了一种方法。所述方法包括将载波放大器附接在衬底上、将峰值放大器与所述载波放大器相邻地附接在所述衬底上以及沿着所述衬底的位于所述载波放大器和所述峰值放大器的至少一部分之间的区域在所述衬底上形成多个互连的引线接合。所述多个引线接合形成了引线接合壁,所述引线接合壁被配置成在所述载波放大器和所述峰值放大器中的至少一个的操作期间减小所述载波放大器和所述峰值放大器之间的电磁耦合。
虽然本公开描述了具体例子、实施例等等,但是如权利要求所陈述的,在不脱离本公开的范围的情况下,可以进行各种修改以及变化。例如,虽然在此描述的示例性方法、器件和系统结合上述提到的器件的配置,本领域所属技术人员将很容易认识到示例性方法、器件和系统可被用于其它方法、器件和系统并且根据需要可被配置成对应于这样的其它示例性方法、器件和系统。此外,虽然至少一个实施例在上述详细说明书中被呈现,但是会存在很多变体。因此,说明书以及附图被认为是说明性而不是限制性的,并且所有这样的修改意在包括在本公开的范围内。关于具体实施例,在此描述的任何好处、优点或解决方案都不旨在被解释为任何或所有权利要求的关键的、必需的、或必要的特征或元素。
Claims (20)
1.一种封装,包括:
衬底;
在所述衬底上的第一电路,所述第一电路包括第一电气器件、第二电气器件以及互连了所述第一电气器件和所述第二电气器件的第一引线接合阵列;
在所述衬底上与所述第一电路相邻的第二电路,所述第二电路包括第三电气器件、第四电气器件以及互连了所述第三电气器件和所述第四电气器件的第二引线接合阵列;以及
包括在所述第一电路和所述第二电路之间的所述衬底上的多个引线接合的引线接合壁,所述引线接合壁被配置成在所述第一电路和所述第二电路中的至少一个的操作期间减小所述第一电路和所述第二电路之间的电磁耦合。
2.根据权利要求1所述的封装,其中所述多个引线接合互连并沿着所述衬底的处于所述第二电路和所述第一电路的至少一部分之间的区域行进。
3.根据权利要求2所述的封装,包括在所述衬底上的多个连接盘,并且其中所述引线接合壁的所述引线结合电互连所述连接盘。
4.根据权利要求1所述的封装,其中所述第一电路是Doherty放大器的载波放大器。
5.根据权利要求4所述的封装,其中所述第二电路是所述Doherty放大器的峰值放大器。
6.根据权利要求1所述的封装,其中所述引线接合壁被连接到接地电压端子。
7.根据权利要求1所述的封装,其中所述引线接合壁被连接到集成无源器件。
8.根据权利要求7所述的封装,其中当所述集成无源器件被连接到所述引线接合壁的时候,所述集成无源器件的电容和电感中的至少一个被选择以在频率范围内减小所述第一电路和所述第二电路之间的电磁耦合。
9.根据权利要求1所述的封装,其中所述第一电气器件、第二电气器件、第三电气器件以及第四电气器件中的至少一个包括电容器和晶体管中的至少一个。
10.一种Doherty放大器封装,包括:
衬底;
在所述衬底上的载波放大器;
在所述衬底上与所述载波放大器相邻的峰值放大器;以及
在所述衬底上的多个引线接合,所述多个引线接合互连并沿着所述衬底的位于所述峰值放大器和所述载波放大器的至少一部分之间的区域行进,所述多个引线接合形成了引线接合壁,所述引线接合壁被配置成在所述载波放大器和所述峰值放大器中的至少一个的操作期间减小所述载波放大器和所述峰值放大器之间的电磁耦合。
11.根据权利要求10所述的Doherty放大器封装,包括在所述衬底上的多个连接盘,并且其中所述多个引线接合电互连所述连接盘。
12.根据权利要求11所述的Doherty放大器封装,其中所述多个连接盘被连接到接地电压。
13.根据权利要求10所述的Doherty放大器封装,其中所述多个引线接合被连接到接地电压端子。
14.根据权利要求10所述的Doherty放大器封装,其中所述多个引线接合被连接到集成无源器件。
15.根据权利要求14所述的Doherty放大器封装,其中当所述集成无源器件被连接到所述多个引线接合的时候并且在所述载波放大器和所述峰值放大器中的至少一个的操作期间,所述集成无源器件选择电容和电感中的至少一个以减小所述载波放大器和所述峰值放大器之间的电磁耦合。
16.根据权利要求10所述的Doherty放大器封装,其中:
所述载波放大器包括第一引线接合阵列,所述第一引线接合阵列互连了所述载波放大器的第一电气器件和所述载波放大器的第二电气器件;以及
所述峰值放大器包括第二引线接合阵列,所述第二引线接合阵列互连了所述载波放大器的第三电气器件和所述载波放大器的第四电气器件。
17.一种方法,包括:
将载波放大器附接在衬底上;
将峰值放大器与所述载波放大器相邻地附接在所述衬底上;以及
沿着所述衬底的位于所述峰值放大器和所述载波放大器的至少一部分之间的区域在所述衬底上形成多个互连的引线接合,所述多个引线接合形成了引线接合壁,所述引线接合壁被配置成在所述载波放大器和所述峰值放大器中的至少一个的操作期间减小所述载波放大器和所述峰值放大器之间的电磁耦合。
18.根据权利要求17所述的方法,包括在所述衬底上形成多个连接盘,其中所述多个引线接合电互连所述连接盘。
19.根据权利要求18所述的方法,包括将所述多个连接盘连接到接地电压端子。
20.根据权利要求17所述的方法,包括:
将集成无源器件安装到所述衬底;以及
将所述多个引线接合连接到所述集成无源器件。
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CN102281707A (zh) * | 2010-06-11 | 2011-12-14 | 株式会社村田制作所 | 电路模块 |
Cited By (4)
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US10573594B2 (en) | 2012-07-20 | 2020-02-25 | Nxp Usa, Inc. | Semiconductor package design providing reduced electromagnetic coupling between circuit components |
US10269729B2 (en) | 2013-06-27 | 2019-04-23 | Nxp Usa, Inc. | Semiconductor packages having wire bond wall to reduce coupling |
CN107123637A (zh) * | 2016-02-24 | 2017-09-01 | 恩智浦美国有限公司 | 具有隔离壁的半导体封装 |
CN107123637B (zh) * | 2016-02-24 | 2022-04-29 | 恩智浦美国有限公司 | 具有隔离壁的半导体封装 |
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JP2015012609A (ja) | 2015-01-19 |
JP6530893B2 (ja) | 2019-06-12 |
CN104253095B (zh) | 2018-04-10 |
US9401342B2 (en) | 2016-07-26 |
US20150002226A1 (en) | 2015-01-01 |
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